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i965: Always flush caches after blitting to a GL buffer object. 

When we blit data into a buffer object, we may need to invalidate any
caches that might contain stale data, so the new data becomes visible.

For example, if the buffer object is bound as a vertex buffer, we need
to invalidate the vertex fetch cache.

While this flushing was missing, it usually happened implicitly for
non-obvious reasons: we're usually on the render ring, and calling
intel_emit_linear_blit() would require switching to the BLT ring,
causing an implicit flush.  This likely provoked the kernel to do
PIPE_CONTROLs on our behalf.  Although, Gen4-5 wouldn't have this
behavior.  At any rate, we should do it ourselves.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Kenneth Graunke 2017-08-28 22:04:01 -07:00
parent df8f4bfc02
commit 3efedf98e8
1 changed files with 3 additions and 1 deletions
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4
src/mesa/drivers/dri/i965/intel_buffer_objects.c
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@ -298,6 +298,7 @@ brw_buffer_subdata(struct gl_context *ctx,
intel_obj->buffer, offset,
temp_bo, 0,
size);
brw_emit_mi_flush(brw);
brw_bo_unreference(temp_bo);
mark_buffer_valid_data(intel_obj, offset, size);
@ -541,6 +542,7 @@ brw_flush_mapped_buffer_range(struct gl_context *ctx,
mark_buffer_gpu_usage(intel_obj,
obj->Mappings[index].Offset + offset,
length);
brw_emit_mi_flush(brw);
}
@ -570,6 +572,7 @@ brw_unmap_buffer(struct gl_context *ctx,
obj->Mappings[index].Length);
mark_buffer_gpu_usage(intel_obj, obj->Mappings[index].Offset,
obj->Mappings[index].Length);
brw_emit_mi_flush(brw);
}
/* Since we've emitted some blits to buffers that will (likely) be used
@ -577,7 +580,6 @@ brw_unmap_buffer(struct gl_context *ctx,
* flush. Once again, we wish for a domain tracker in libdrm to cover
* usage inside of a batchbuffer.
*/
brw_emit_mi_flush(brw);
brw_bo_unreference(intel_obj->range_map_bo[index]);
intel_obj->range_map_bo[index] = NULL;