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i965: drop brw->is_baytrail in favor of devinfo->is_baytrail 

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
This commit is contained in:
Lionel Landwerlin 2017-08-30 09:12:49 +01:00
parent 990c24ad85
commit d324197de9
8 changed files with 13 additions and 13 deletions
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1
src/mesa/drivers/dri/i965/brw_context.c
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@ -858,7 +858,6 @@ brwCreateContext(gl_api api,
brw->screen = screen;
brw->bufmgr = screen->bufmgr;
brw->is_baytrail = devinfo->is_baytrail;
brw->is_haswell = devinfo->is_haswell;
brw->is_cherryview = devinfo->is_cherryview;
brw->is_broxton = devinfo->is_broxton || devinfo->is_geminilake;

1
src/mesa/drivers/dri/i965/brw_context.h
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@ -746,7 +746,6 @@ struct brw_context
uint64_t max_gtt_map_object_size;
bool is_baytrail;
bool is_haswell;
bool is_cherryview;
bool is_broxton;

2
src/mesa/drivers/dri/i965/brw_draw_upload.c
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@ -254,7 +254,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
int size = glarray->Size;
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const bool is_ivybridge_or_older =
devinfo->gen <= 7 && !brw->is_baytrail && !brw->is_haswell;
devinfo->gen <= 7 && !devinfo->is_baytrail && !brw->is_haswell;
if (unlikely(INTEL_DEBUG & DEBUG_VERTS))
fprintf(stderr, "type %s size %d normalized %d\n",

6
src/mesa/drivers/dri/i965/gen7_l3_state.c
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@ -141,11 +141,11 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
* client (URB for all validated configurations) set to the
* lower-bandwidth 2-bank address hashing mode.
*/
const bool urb_low_bw = has_slm && !brw->is_baytrail;
const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
/* Minimum number of ways that can be allocated to the URB. */
const unsigned n0_urb = (brw->is_baytrail ? 32 : 0);
const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0);
assert(cfg->n[GEN_L3P_URB] >= n0_urb);
BEGIN_BATCH(7);
@ -154,7 +154,7 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
/* Demote any clients with no ways assigned to LLC. */
OUT_BATCH(GEN7_L3SQCREG1);
OUT_BATCH((brw->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
brw->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
(has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) |
(has_is ? 0 : GEN7_L3SQCREG1_CONV_IS_UC) |

4
src/mesa/drivers/dri/i965/gen7_urb.c
View File

@ -146,7 +146,7 @@ gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
*
* No such restriction exists for Haswell or Baytrail.
*/
if (devinfo->gen < 8 && !brw->is_haswell && !brw->is_baytrail)
if (devinfo->gen < 8 && !brw->is_haswell && !devinfo->is_baytrail)
gen7_emit_cs_stall_flush(brw);
}
@ -224,7 +224,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
gen_get_urb_config(devinfo, 1024 * push_size_kB, 1024 * brw->urb.size,
tess_present, gs_present, entry_size, entries, start);
if (devinfo->gen == 7 && !brw->is_haswell && !brw->is_baytrail)
if (devinfo->gen == 7 && !brw->is_haswell && !devinfo->is_baytrail)
gen7_emit_vs_workaround_flush(brw);
BEGIN_BATCH(8);

6
src/mesa/drivers/dri/i965/genX_state_upload.c
View File

@ -431,6 +431,7 @@ upload_format_size(uint32_t upload_format)
static void
genX(emit_vertices)(struct brw_context *brw)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
uint32_t *dw;
brw_prepare_vertices(brw);
@ -563,7 +564,7 @@ genX(emit_vertices)(struct brw_context *brw)
* vertex element may poke over the end of the buffer by 2 bytes.
*/
const unsigned padding =
(GEN_GEN <= 7 && !GEN_IS_HASWELL && !brw->is_baytrail) * 2;
(GEN_GEN <= 7 && !GEN_IS_HASWELL && !devinfo->is_baytrail) * 2;
const unsigned end = buffer->offset + buffer->size + padding;
dw = genX(emit_vertex_buffer_state)(brw, dw, i, buffer->bo,
buffer->offset,
@ -3018,6 +3019,7 @@ UNUSED static const uint32_t push_constant_opcodes[] = {
static void
genX(upload_push_constant_packets)(struct brw_context *brw)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
UNUSED uint32_t mocs = GEN_GEN < 8 ? GEN7_MOCS_L3 : 0;
@ -3030,7 +3032,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw)
&brw->wm.base,
};
if (GEN_GEN == 7 && !GEN_IS_HASWELL && !brw->is_baytrail &&
if (GEN_GEN == 7 && !GEN_IS_HASWELL && !devinfo->is_baytrail &&
stage_states[MESA_SHADER_VERTEX]->push_constants_dirty)
gen7_emit_vs_workaround_flush(brw);

4
src/mesa/drivers/dri/i965/intel_extensions.c
View File

@ -255,7 +255,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.OES_viewport_array = true;
}
if (devinfo->gen >= 8 || brw->is_haswell || brw->is_baytrail) {
if (devinfo->gen >= 8 || brw->is_haswell || devinfo->is_baytrail) {
ctx->Extensions.ARB_robust_buffer_access_behavior = true;
}
@ -263,7 +263,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.ARB_query_buffer_object = true;
}
if (devinfo->gen >= 8 || brw->is_baytrail) {
if (devinfo->gen >= 8 || devinfo->is_baytrail) {
/* For now, we only enable OES_copy_image on platforms that support
* ETC2 natively in hardware. We would need more hacks to support it
* elsewhere.

2
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View File

@ -371,7 +371,7 @@ intel_lower_compressed_format(struct brw_context *brw, mesa_format format)
/* No need to lower ETC formats on these platforms,
* they are supported natively.
*/
if (devinfo->gen >= 8 || brw->is_baytrail)
if (devinfo->gen >= 8 || devinfo->is_baytrail)
return format;
switch (format) {