dfa8e758c2
radeonsi/gfx10: disable clear state
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
0dd57f0fc0
radeonsi/gfx10: disable DPBB
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
815fd77a47
radeonsi/gfx10: disable SDMA
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
f66ee5af2f
radeonsi: determine the rasterization primitive type accurately (v2)
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v2: reworked version to fix bugs and make it more efficient
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
a4b3eea325
radeonsi/gfx10: consolidate & improve input_prim determination for NGG
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
969e5176c2
ac: rework ac_build_waitcnt for gfx10
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
214ddfb688
radeonsi/gfx10: implement si_shader_vs
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Only used with tessellation + GS instancing.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
6cf2fb1fc4
radeonsi/gfx10: unpack GS invocation ID
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
32694456f7
radeonsi/gfx10: jump over the shader query atomic if the queries are disabled
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
244a8e6798
radeonsi/gfx10: cosmetic changes
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
09a905d930
radeonsi/gfx10: set cache control registers
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
b680f723f8
radeonsi/gfx10: export correct PrimitiveID from NGG vertex shaders
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
3203a74dcb
radeonsi/gfx10: set PA_SC_TILE_STEERING_OVERRIDE
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
07aacdbfd5
radeonsi/gfx10: add a workaround for stencil HTILE with mipmapping
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
51db950419
radeonsi/gfx10: disable DCC with MSAA
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It was only enabled for 2x MSAA anyway.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
6920f09f4b
radeonsi/gfx10: fix GL_LINE polygon mode for decomposed primitives
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We need to tell PA to accept edge flags generated by the input assembler,
because decomposed primitives shouldn't draw inner edges.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
e39d4594da
radeonsi/gfx10: fix NGG GS color clamping
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Just need to pass the input from ES to GS. Everything else is done.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
40e7c65590
radeonsi/gfx10: fix vertex color clamping for TES
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
cc7875150a
radeonsi/gfx10: unbind NGG shaders when destroyed
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This fixes glsl-max-varyings, which creates shaders, draws, and then
destroys them.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
b90ddff477
radeonsi/gfx10: don't use the GS workaround for triangle strips w/ adjancency
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
c3ac22a620
radeonsi/gfx10: don't do the query buffer atomic for blit shaders
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
adbec817d3
radeonsi/gfx10: update spi_map if API VS (as NGG) changes and PS doesn't
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
1e39c21c23
radeonsi/gfx10: fix a possible hang with exp pos0 with done=0 and exec=0
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
683cf11b81
radeonsi/gfx10: prefetch HW GS when NGG is used
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
76898a8062
amd/common/gfx10: set DLC for llvm.amdgcn.s.buffer.load
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
7f71579064
radeonsi/gfx10: fix PS exports for SPI_SHADER_32_AR
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
4bdf44724f
radeonsi/gfx10: set DLC for loads when GLC is set
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This fixes L1 shader array cache coherency.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
f81aa6b0c8
radeonsi/gfx10: fix shader images
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Don't promote 2D image instructions to 3D, and don't set z=BASE_ARRAY.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
7c805a7c67
radeonsi/gfx10: set the DCC constant encoding flag
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
6eb219e963
radeonsi/gfx10: fix intensity formats
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move the ALPHA_IS_ON_MSB fixup into vi_alpha_is_on_msb
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
6944f99176
radeonsi/gfx10: allocate GDS BOs for streamout
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
395185912d
radeonsi/gfx10: make sure GDS is idle between IBs
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
5ff3aff0d6
radeonsi/gfx10: implement streamout
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
792a638b03
radeonsi/gfx10: implement streamout-related queries
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The NGG hardware pipeline doesn't track these statistics automatically,
and in fact *cannot* track them automatically when API geometry shaders
are involved, so we accumulate statistics in the shader using atomic
adds.
This implementation accumulates statistics via the memory system and
the RW buffer descriptor setup. We could use GDS, but since these
atomics aren't latency-sensitive, that basically just trades off
L2$ bandwidth vs. export bus bandwidth. One single memory transaction
per shader workgroup doesn't seem too bad. The result ring buffer in
memory is needed either way to avoid pipeline stalls.
The shader code contains the atomic unconditionally, though the
GFX10_GS_QUERY_BUF is a null buffer when no queries are active. The
atomic is simply discarded by the shader hardware in that case.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
bcd2d2e194
radeonsi/gfx10: enable the workaround for unaligned vertex fetch
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Yes, really. Note that non-format buffer loads are unaffected and work
just fine with unaligned pointers (as long as SH_MEM_CONFIG is setup
correctly, which amdgpu ensures).
Fixes e.g. KHR-GL45.vertex_attrib_64bit.vao
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
22b85bfc02
radeonsi/gfx10: re-order the initialization order in si_compile_tgsi_main
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It's useful to be able to access gs_ngg_scratch before creating the
main wrapping branch.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
3aa622aab1
radeonsi/gfx10: apply DCC MSAA blend workaround
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
bc25ccfe22
radeonsi/gfx10: implement si_emit_global_shader_pointers
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
6bcc273de8
radeonsi/gfx10: implement si_init_tess_factor_ring
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
2492cfde66
radeonsi/gfx10: initialize EXEC for TES-as-NGG (without geometry shader)
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
591537c7fa
radeonsi/gfx10: use correct VGPR for instance ID in LS shader
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
f3b9a37278
radeonsi/gfx10: implement si_shader_hs
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
e4d6b4daae
radeonsi/gfx10: implement si_create_sampler_state
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
0bf3e6fae7
radeonsi/gfx10: double the number of tessellation offchip buffers per SE
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Each gfx10 shader engine corresponds to two gfx9 shader engines, so scale
the number of offchip buffers accordingly.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
2afd3c421d
radeonsi/gfx10: implement get_tess_ring_descriptor
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
d028440f57
radeonsi/gfx10: mask DCC tile swizzle by alignment
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DCC alignment can be less than the alignment of the main surface. In that
case, the DCC tile swizzle needs to be masked accordingly. Should have no
impact on pre-gfx10.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
1666ee183e
radeonsi/gfx10: implement hardware MSAA resolve
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MSAA is only supported for 64KB_{R,Z}_X modes, so the micro tile
optimization that we use on gfx9 and earlier does not work.
Be very explicit about how the swizzle mode of the temporary surface is
selected.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
69c41fb8ff
radeonsi/gfx10: fix binding on si_update_scratch_relocs
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
fd8758366b
radeonsi/gfx10: set llvm_has_working_vgpr_indexing
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
48810ad02d
radeonsi/gfx10: implement load_const_buffer_desc_fast_path
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
Nicolai Hähnle
Marek Olšák