Commit Graph

51721 Commits

Author SHA1 Message Date
Christian König 1fb8ee62fa radeonsi: fix shader binding
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 15:01:51 +02:00
Christian König f18fd255cf radeonsi: fix dummy export in shaders v2
v2: add assertion for vertex shader

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 15:01:34 +02:00
Christian König b15e3ae5b4 radeonsi: fix vertex buffer and elements
Let's just use the T# descriptors until we get a fetch shader.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 14:45:32 +02:00
Christian König d51b9b70d5 radeonsi: fix shader size and handling
We should always upload the shader here.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 14:45:08 +02:00
Christian König fe41287ffa radeonsi: rename r600_resource to si_resource
Also split it into seperate header and add
some helper functions.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 14:44:38 +02:00
Kenneth Graunke dcf8754cce glcpp: Add a newline to expanded #line directives.
Otherwise, the preprocessor happily outputs

    #line 2 4 <your next line of code>

and the main compiler gets horribly confused and fails to compile.

This is not the right solution (line numbers in error messages will
likely be off-by-one in certain circumstances), but until Carl comes
up with a proper fix, this gets programs running again.

Fixes regressions in Regnum Online, Overgrowth, Piglit, and others since
commit aac78ce823.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51802
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51506
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41152
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-28 13:33:50 -07:00
Christoph Bumiller 5d5af7d359 gallium: specify resource_resolve destination via a pipe_surface
The format member of pipe_surface may differ from that of the
pipe_resource, which is used to communicate, for instance, whether
sRGB encode should be enabled in the resolve operation or not.

Fixes resolve to sRGB surfaces in mesa/st when GL_FRAMEBUFFER_SRGB
is disabled.

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-07-28 14:58:18 +02:00
Christoph Bumiller 51e41a0d89 st/mesa: call update_renderbuffer_surface for sRGB renderbuffers, too
sRGBEnabled should affect both textures and renderbuffers, so we need
to check/update the pipe_surface format for both.

Fixes, for instance, rendering appearing too bright in wine applications
using sRGB multisample renderbuffers.

NOTE: This is a candidate for the 8.0 branch.

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-07-28 13:14:30 +02:00
Christoph Bumiller acd66ec033 nv50: fix depth/stencil multisample memory storage types
Leftover from libdrm_nouveau v2 interface change.
2012-07-28 13:14:03 +02:00
Christoph Bumiller cd3d85b63d nv50: fix resource_resolve shader start offsets 2012-07-28 13:11:56 +02:00
Brian Paul f612e55e45 st/mesa: undo a couple static asserts
Hmm, gcc didn't catch these mistakes, but MSVC did.
2012-07-27 16:10:58 -06:00
Brian Paul 322a2938f3 st/mesa: use STATIC_ASSERT in a few places 2012-07-27 15:47:38 -06:00
Brian Paul 59c67f8116 mesa: whitespace, etc. fixes in program.h 2012-07-27 15:43:53 -06:00
Brian Paul 906febaf8b meta: fix glDrawPixels fallback test, stencil drawing
Remove the check for pixel transfer ops.  If any RGB/depth scale/bias
is in effect, it'll be applied in the glTexImage step.

If drawing stencil pixels we need to disable pixel transfer so that
alpha scale/bias are not applied to the stencil data.

These issues were spotted by Roland.

Fixes Blender performance issues reported in
http://bugs.freedesktop.org/show_bug.cgi?id=47375

NOTE: This is a candidate for the 8.0 branch.

Tested-by: Barto <mister.freeman@laposte.net>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2012-07-27 14:53:16 -06:00
Brian Paul a80b7407f3 radeon: fix 'sowftware' typo 2012-07-27 14:53:16 -06:00
Eric Anholt fbf86c7f0f i965/gen7: Reduce GT1 WM thread count according to updated BSpec.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

https://bugs.freedesktop.org/show_bug.cgi?id=52382
2012-07-27 11:42:19 -07:00
Kenneth Graunke cbcf750d5f i965: Fix typo in shader channel select field name.
"chanel" isn't very searchable.  I can type, honest!

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-27 11:31:07 -07:00
Paul Berry ee9f6a34cc i965/msaa: Use MESA_FORMAT_R8 for MCS buffer.
No functional change.  This patch modifies intel_miptree_alloc_mcs to
allocate the 4x MCS buffer using MESA_FORMAT_R8 instead of
MESA_FORMAT_A8.  In principle it doesn't matter, since we only access
the buffer using MCS-specific hardware mechanisms, so all that's
important is to use a format with the correct size.  However,
MESA_FORMAT_A8 has enough unusual behaviours that it seems prudent to
avoid it.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-27 10:42:19 -07:00
Zou Nan hai 588881430a intel: increase wm thread number to 80 on gen6 GT2
It seems reset is not required for setting the max_wm_threads to 80
on gen6 GT2.

Increases performance in the Counter-Strike: Source video stress test
by 7.18% (n=5).

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Matt Turner <mattst88@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
2012-07-27 10:32:17 -07:00
Tom Stellard fdd8df20e4 r600g: Emit dispatch state for compute directly to the cs
We no longer rely on an evergreen_compute_resource for emitting dispatch
state.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-07-27 17:08:09 +00:00
Tom Stellard dc0b8a4628 r600g: Initialize VGT_PRIMITIVE_TYPE in the start_cs_cmd atom
The value of this register will always be DI_PT_POINTLIST for compute
shaders.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-07-27 17:08:09 +00:00
Tom Stellard d3b0130491 r600g: Atomize compute shader state
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-07-27 17:08:09 +00:00
Tom Stellard 5497391067 r600g: Add helper functions for emitting compute SET_CONTEXT packets
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-07-27 17:08:09 +00:00
Tom Stellard c9ef27276f radeon/llvm: Add instruction defs for branches on SI 2012-07-27 17:08:09 +00:00
Tom Stellard ee0f0f03c6 radeon/llvm: Fix VOPC and V_CNDMASK encoding 2012-07-27 17:08:09 +00:00
Tom Stellard d4bdd09d47 radeon/llvm: Assert if we try to copy SCC reg 2012-07-27 17:08:09 +00:00
Tom Stellard fd1f19a191 radeon/llvm: Add SI DAG optimizations for setcc, select_cc
These are needed for correctly lowering branch instructions in some
cases.
2012-07-27 17:08:08 +00:00
Tom Stellard cd5d4c5073 radeon/llvm: Add support for encoding SI branch instructions 2012-07-27 17:08:08 +00:00
Tom Stellard 50ff2dc0a4 radeon/llvm: Add special nodes for SALU operations on VCC
The VCC register is tricky because the SALU views it as 64-bit, but the
VALU views it as 1-bit.  In order to deal with this we've added some
special bitcast and binary operations to help convert from the 64-bit
SALU view to the 1-bit VALU view and vice versa.
2012-07-27 17:08:08 +00:00
Tom Stellard c424975572 radeon/llvm: Add i1 registers for SI. 2012-07-27 17:08:08 +00:00
Tom Stellard bdda1cb914 radeon/llvm: Fix CCReg definitions on SI 2012-07-27 17:08:08 +00:00
Tom Stellard ae9be358f2 radeonsi: Enable PIPE_SHADER_CAP_INTEGERS 2012-07-27 17:08:08 +00:00
Tom Stellard 022b54359a radeonsi: Add support for loading integers from constant memory 2012-07-27 17:08:07 +00:00
Tom Stellard ad95bcb31f radeon/llvm: Add bitconvert patterns for SI 2012-07-27 17:08:07 +00:00
Tom Stellard 4cab682184 radeon/llvm: Add custom lowering for SELECT_CC nodes on SI 2012-07-27 17:08:07 +00:00
Tom Stellard ba76684292 radeon/llvm: Move conditional pattern leafs to common tablegen file 2012-07-27 17:08:07 +00:00
Tom Stellard d36455ba2c radeon/llvm: Implement getSetCCResultType for SI 2012-07-27 17:08:07 +00:00
Tom Stellard e8825ce6e1 radeon/llvm: Custom lower BR_CC for SI 2012-07-27 17:08:07 +00:00
Tom Stellard 87272e9e25 radeon/llvm: Move lowering of BR_CC node to R600ISelLowering
SI will handle BR_CC different from R600, so we need to move it
out of the shared instruction selector.
2012-07-27 17:08:07 +00:00
Tom Stellard 92823fb72a radeon/llvm: Move lowering of SETCC node to R600ISelLowering
SI will handle SETCC different from R600, so we need to move it
out of the shared instruction selector.
2012-07-27 17:08:06 +00:00
Tom Stellard 46d12c99a2 radeon/llvm: Use correct node type when lowering SETCC 2012-07-27 17:08:06 +00:00
Tom Stellard 47d1b0a809 radeon/llvm: Move LowerSELECT_CC into R600ISelLowering
SI will handle SELECT_CC different from R600, so we need to move it out
of the shared instruction selector.
2012-07-27 17:08:06 +00:00
Eric Anholt 11ff18fcf5 automake: Remove OPT_FLAGS.
If you want to change your compiler arguments, just set CFLAGS/CXXFLAGS.
Having Mesa have this separate variable is a great way to have your arguments
not thoroughly propagated to all compiler invocations.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-26 17:30:06 -07:00
Eric Anholt 87a1c4f233 automake: Remove ARCH_FLAGS.
In all current uses, it was appended to CFLAGS, which already had -m32.  If
you want to do some other flag supplied to compiler invocations, there's
CFLAGS/CXXFLAGS.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-26 17:30:06 -07:00
Paul Berry 4df2848786 i965/msaa: use ROUND_DOWN_TO macro.
No functional change.  This patch modifies brw_blorp_blit.cpp to use
the ROUND_DOWN_TO macro instead of open-coded bit manipulations, for
clarity.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-26 15:02:10 -07:00
Brian Paul f37f1a7209 svga: initialize svga_compile_key to zeros to be safe 2012-07-26 16:00:31 -06:00
Brian Paul dafa77201f svga: fix invalid memory reference in needs_to_create_zero()
The emit->key.fkey info is only valid if we're generating a fragment shader.
We should not look at it if we're generating a vertex shader.

When generating a vertex shader, the value of emit->key.fkey.num_textures was
garbage and the loop over num_textures would read invalid data.  At best
this would cause us to emit an unused constant.  At worse, we could segfault.
Just by dumb luck, fkey.num_textures was usually a smallish integer.

NOTE: This is a candidate for the 8.0 branch.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-07-26 16:00:31 -06:00
Brian Paul 38184dcd54 radeon: fix Base/base typo
Fixes http://bugs.freedesktop.org/show_bug.cgi?id=52563
2012-07-26 15:57:20 -06:00
Daniel Charles 948c8f502a android-build: fix dricore build for autogenerated files (v3)
Recently more files were removed from control to be auto-generated
in the dricore library. Android build was not able to locate the
new files if they were not created beforehand.

LOCAL_SRC_FILES includes some of those files and Android.gen.mk
re-defines this variable by filtering out the auto-generated files.
Unfortunately for this variable it is not the same to have the SRCDIR
variable defined as the current directory.

By re-defining SRCDIR for the autotools build the Android build system
is happy again and the new files were actually removed from the sources
to use the auto generated versions.

Also patch d5c1801a01 was partially reverted as the files
can not be compiled to the LOCAL_PATH, instead they should live on the
intermediates folder so that a clean can wipe them out.

v3: [chad] Fix the definition of SRCDIR in libdricore/Makefile.am.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Signed-off-by: Daniel Charles <daniel.charles@intel.com>
2012-07-26 14:51:20 -07:00
Brian Paul 0e893b4261 radeon: set swrast_renderbuffer::ColorType field when mapping renderbuffers
Fixes http://bugs.freedesktop.org/show_bug.cgi?id=47375

NOTE: This is a candidate for the 8.0 branch.

Tested-by: Barto <mister.freeman@laposte.net>
2012-07-26 13:59:44 -06:00