r600g: Emit dispatch state for compute directly to the cs
We no longer rely on an evergreen_compute_resource for emitting dispatch state. Reviewed-by: Marek Olšák <maraeo@gmail.com>
This commit is contained in:
Tom Stellard
parent
dc0b8a4628
commit
fdd8df20e4
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@ -249,37 +249,21 @@ void evergreen_compute_upload_input(
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shader->input_size, 0);
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}
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void evergreen_direct_dispatch(
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struct pipe_context *ctx_,
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static void evergreen_emit_direct_dispatch(
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struct r600_context *rctx,
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const uint *block_layout, const uint *grid_layout)
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{
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/* This struct r600_context* must be called rctx, because the
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* r600_pipe_state_add_reg macro assumes there is a local variable
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* of type struct r600_context* called rctx.
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*/
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struct r600_context *rctx = (struct r600_context *)ctx_;
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struct r600_pipe_compute *shader = rctx->cs_shader_state.shader;
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int i;
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struct evergreen_compute_resource* res = get_empty_res(shader,
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COMPUTE_RESOURCE_DISPATCH, 0);
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/* Set CB_TARGET_MASK */
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evergreen_reg_set(res, R_028238_CB_TARGET_MASK, rctx->compute_cb_target_mask);
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evergreen_reg_set(res, R_00899C_VGT_COMPUTE_START_X, 0);
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evergreen_reg_set(res, R_0089A0_VGT_COMPUTE_START_Y, 0);
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evergreen_reg_set(res, R_0089A4_VGT_COMPUTE_START_Z, 0);
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evergreen_reg_set(res, R_0286EC_SPI_COMPUTE_NUM_THREAD_X, block_layout[0]);
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evergreen_reg_set(res, R_0286F0_SPI_COMPUTE_NUM_THREAD_Y, block_layout[1]);
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evergreen_reg_set(res, R_0286F4_SPI_COMPUTE_NUM_THREAD_Z, block_layout[2]);
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struct radeon_winsys_cs *cs = rctx->cs;
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unsigned num_waves;
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unsigned num_pipes = rctx->screen->info.r600_max_pipes;
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unsigned wave_divisor = (16 * num_pipes);
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int group_size = 1;
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int grid_size = 1;
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/* XXX: Enable lds and get size from cs_shader_state */
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unsigned lds_size = 0;
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/* Calculate group_size/grid_size */
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for (i = 0; i < 3; i++) {
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group_size *= block_layout[i];
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}
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@ -288,18 +272,50 @@ void evergreen_direct_dispatch(
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grid_size *= grid_layout[i];
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}
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evergreen_reg_set(res, R_008970_VGT_NUM_INDICES, group_size);
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evergreen_reg_set(res, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE, group_size);
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/* num_waves = ceil((tg_size.x * tg_size.y, tg_size.z) / (16 * num_pipes)) */
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num_waves = (block_layout[0] * block_layout[1] * block_layout[2] +
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wave_divisor - 1) / wave_divisor;
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evergreen_emit_raw_value(res, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0));
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evergreen_emit_raw_value(res, grid_layout[0]);
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evergreen_emit_raw_value(res, grid_layout[1]);
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evergreen_emit_raw_value(res, grid_layout[2]);
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///VGT_DISPATCH_INITIATOR = COMPUTE_SHADER_EN
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evergreen_emit_raw_value(res, 1);
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COMPUTE_DBG("Using %u pipes, there are %u wavefronts per thread block\n",
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num_pipes, num_waves);
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/* XXX: Partition the LDS between PS/CS. By default half (4096 dwords
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* on Evergreen) oes to Pixel Shaders and half goes to Compute Shaders.
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* We may need to allocat the entire LDS space for Compute Shaders.
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*
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* EG: R_008E2C_SQ_LDS_RESOURCE_MGMT := S_008E2C_NUM_LS_LDS(lds_dwords)
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* CM: CM_R_0286FC_SPI_LDS_MGMT := S_0286FC_NUM_LS_LDS(lds_dwords)
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*/
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r600_write_config_reg(cs, R_008970_VGT_NUM_INDICES, group_size);
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r600_write_config_reg_seq(cs, R_00899C_VGT_COMPUTE_START_X, 3);
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r600_write_value(cs, 0); /* R_00899C_VGT_COMPUTE_START_X */
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r600_write_value(cs, 0); /* R_0089A0_VGT_COMPUTE_START_Y */
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r600_write_value(cs, 0); /* R_0089A4_VGT_COMPUTE_START_Z */
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r600_write_config_reg(cs, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE,
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group_size);
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r600_write_compute_context_reg_seq(cs, R_0286EC_SPI_COMPUTE_NUM_THREAD_X, 3);
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r600_write_value(cs, block_layout[0]); /* R_0286EC_SPI_COMPUTE_NUM_THREAD_X */
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r600_write_value(cs, block_layout[1]); /* R_0286F0_SPI_COMPUTE_NUM_THREAD_Y */
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r600_write_value(cs, block_layout[2]); /* R_0286F4_SPI_COMPUTE_NUM_THREAD_Z */
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r600_write_compute_context_reg(cs, CM_R_0288E8_SQ_LDS_ALLOC,
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lds_size | (num_waves << 14));
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/* Dispatch packet */
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r600_write_value(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0));
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r600_write_value(cs, grid_layout[0]);
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r600_write_value(cs, grid_layout[1]);
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r600_write_value(cs, grid_layout[2]);
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/* VGT_DISPATCH_INITIATOR = COMPUTE_SHADER_EN */
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r600_write_value(cs, 1);
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}
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static void compute_emit_cs(struct r600_context *ctx)
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static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout,
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const uint *grid_layout)
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{
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struct radeon_winsys_cs *cs = ctx->cs;
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int i;
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@ -330,6 +346,11 @@ static void compute_emit_cs(struct r600_context *ctx)
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cb_state = ctx->states[R600_PIPE_STATE_FRAMEBUFFER];
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r600_context_pipe_state_emit(ctx, cb_state, RADEON_CP_PACKET3_COMPUTE_MODE);
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/* Set CB_TARGET_MASK XXX: Use cb_misc_state */
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r600_write_compute_context_reg(cs, R_028238_CB_TARGET_MASK,
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ctx->compute_cb_target_mask);
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/* Emit vertex buffer state */
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ctx->cs_vertex_buffer_state.atom.num_dw = 12 * util_bitcount(ctx->cs_vertex_buffer_state.dirty_mask);
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r600_emit_atom(ctx, &ctx->cs_vertex_buffer_state.atom);
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@ -370,6 +391,9 @@ static void compute_emit_cs(struct r600_context *ctx)
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}
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}
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/* Emit dispatch state and dispatch packet */
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evergreen_emit_direct_dispatch(ctx, block_layout, grid_layout);
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/* r600_flush_framebuffer() updates the cb_flush_flags and then
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* calls r600_emit_atom() on the ctx->surface_sync_cmd.atom, which emits
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* a SURFACE_SYNC packet via r600_emit_surface_sync().
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@ -438,24 +462,12 @@ static void evergreen_launch_grid(
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const uint *block_layout, const uint *grid_layout,
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uint32_t pc, const void *input)
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{
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struct r600_context *ctx = (struct r600_context *)ctx_;
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COMPUTE_DBG("PC: %i\n", pc);
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struct r600_context *ctx = (struct r600_context *)ctx_;
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unsigned num_waves;
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unsigned num_pipes = ctx->screen->info.r600_max_pipes;
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unsigned wave_divisor = (16 * num_pipes);
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/* num_waves = ceil((tg_size.x * tg_size.y, tg_size.z) / (16 * num_pipes)) */
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num_waves = (block_layout[0] * block_layout[1] * block_layout[2] +
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wave_divisor - 1) / wave_divisor;
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COMPUTE_DBG("Using %u pipes, there are %u wavefronts per thread block\n",
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num_pipes, num_waves);
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evergreen_set_lds(ctx->cs_shader_state.shader, 0, 0, num_waves);
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evergreen_compute_upload_input(ctx_, block_layout, grid_layout, input);
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evergreen_direct_dispatch(ctx_, block_layout, grid_layout);
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compute_emit_cs(ctx);
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compute_emit_cs(ctx, block_layout, grid_layout);
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}
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static void evergreen_set_compute_resources(struct pipe_context * ctx_,
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@ -34,7 +34,6 @@ struct evergreen_compute_resource;
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void *evergreen_create_compute_state(struct pipe_context *ctx, const const struct pipe_compute_state *cso);
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void evergreen_delete_compute_state(struct pipe_context *ctx, void *state);
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void evergreen_direct_dispatch( struct pipe_context *context, const uint *block_layout, const uint *grid_layout);
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void evergreen_compute_upload_input(struct pipe_context *context, const uint *block_layout, const uint *grid_layout, const void *input);
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void evergreen_init_atom_start_compute_cs(struct r600_context *rctx);
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void evergreen_init_compute_state_functions(struct r600_context *rctx);
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@ -301,25 +301,6 @@ void evergreen_set_rat(
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r600_context_pipe_state_set(pipe->ctx, state);
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}
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void evergreen_set_lds(
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struct r600_pipe_compute *pipe,
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int num_lds,
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int size,
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int num_waves)
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{
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struct evergreen_compute_resource* res =
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get_empty_res(pipe, COMPUTE_RESOURCE_LDS, 0);
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if (pipe->ctx->chip_class < CAYMAN) {
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evergreen_reg_set(res, R_008E2C_SQ_LDS_RESOURCE_MGMT,
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S_008E2C_NUM_LS_LDS(num_lds));
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} else {
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evergreen_reg_set(res, CM_R_0286FC_SPI_LDS_MGMT,
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S_0286FC_NUM_LS_LDS(num_lds));
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}
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evergreen_reg_set(res, CM_R_0288E8_SQ_LDS_ALLOC, size | num_waves << 14);
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}
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void evergreen_set_gds(
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struct r600_pipe_compute *pipe,
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uint32_t addr,
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@ -102,7 +102,6 @@ int get_compute_resource_num(void);
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#define evergreen_mult_reg_set(res, index, array) evergreen_mult_reg_set_(res, index, array, sizeof(array))
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void evergreen_set_rat(struct r600_pipe_compute *pipe, int id, struct r600_resource* bo, int start, int size);
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void evergreen_set_lds(struct r600_pipe_compute *pipe, int num_lds, int size, int num_waves);
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void evergreen_set_gds(struct r600_pipe_compute *pipe, uint32_t addr, uint32_t size);
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void evergreen_set_export(struct r600_pipe_compute *pipe, struct r600_resource* bo, int offset, int size);
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void evergreen_set_loop_const(struct r600_pipe_compute *pipe, int id, int count, int init, int inc);
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