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ac/gpu_info: remove vram_size and gtt_size in favor of *_kb variants 

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
This commit is contained in:
Marek Olšák 2022-07-07 19:22:31 -04:00 committed by Marge Bot
parent 983223de5d
commit 12c5d64fae
18 changed files with 49 additions and 57 deletions
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25
src/amd/common/ac_gpu_info.c
View File

@ -654,9 +654,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
}
/* Note: usable_heap_size values can be random and can't be relied on. */
info->gart_size = meminfo.gtt.total_heap_size;
info->vram_size = fix_vram_size(meminfo.vram.total_heap_size);
info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
info->gart_size_kb = DIV_ROUND_UP(meminfo.gtt.total_heap_size, 1024);
info->vram_size_kb = DIV_ROUND_UP(fix_vram_size(meminfo.vram.total_heap_size), 1024);
info->vram_vis_size_kb = DIV_ROUND_UP(meminfo.cpu_accessible_vram.total_heap_size, 1024);
} else {
/* This is a deprecated interface, which reports usable sizes
* (total minus pinned), but the pinned size computation is
@ -684,14 +684,11 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
return false;
}
info->gart_size = gtt.heap_size;
info->vram_size = fix_vram_size(vram.heap_size);
info->vram_vis_size = vram_vis.heap_size;
info->gart_size_kb = DIV_ROUND_UP(gtt.heap_size, 1024);
info->vram_size_kb = DIV_ROUND_UP(fix_vram_size(vram.heap_size), 1024);
info->vram_vis_size_kb = DIV_ROUND_UP(vram_vis.heap_size, 1024);
}
info->gart_size_kb = MIN2(DIV_ROUND_UP(info->gart_size, 1024), UINT32_MAX);
info->vram_size_kb = MIN2(DIV_ROUND_UP(info->vram_size, 1024), UINT32_MAX);
if (info->drm_minor >= 41) {
amdgpu_query_video_caps_info(dev, AMDGPU_INFO_VIDEO_CAPS_DECODE,
sizeof(info->dec_caps), &(info->dec_caps));
@ -700,7 +697,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
}
/* Add some margin of error, though this shouldn't be needed in theory. */
info->all_vram_visible = info->vram_size * 0.9 < info->vram_vis_size;
info->all_vram_visible = info->vram_size_kb * 0.9 < info->vram_vis_size_kb;
/* Set chip identification. */
info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
@ -931,7 +928,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->num_tcc_blocks = info->max_tcc_blocks - util_bitcount64(device_info.tcc_disabled_mask);
} else {
/* This is a hack, but it's all we can do without a kernel upgrade. */
info->num_tcc_blocks = info->vram_size / (512 * 1024 * 1024);
info->num_tcc_blocks = info->vram_size_kb / (512 * 1024);
if (info->num_tcc_blocks > info->max_tcc_blocks)
info->num_tcc_blocks /= 2;
}
@ -1451,9 +1448,9 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
fprintf(f, "Memory info:\n");
fprintf(f, " pte_fragment_size = %u\n", info->pte_fragment_size);
fprintf(f, " gart_page_size = %u\n", info->gart_page_size);
fprintf(f, " gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024 * 1024));
fprintf(f, " vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024 * 1024));
fprintf(f, " vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024 * 1024));
fprintf(f, " gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size_kb, 1024));
fprintf(f, " vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size_kb, 1024));
fprintf(f, " vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size_kb, 1024));
fprintf(f, " vram_type = %i\n", info->vram_type);
fprintf(f, " max_heap_size_kb = %i MB\n", (int)DIV_ROUND_UP(info->max_heap_size_kb, 1024));
fprintf(f, " min_alloc_size = %u\n", info->min_alloc_size);

4
src/amd/common/ac_gpu_info.h
View File

@ -126,9 +126,7 @@ struct radeon_info {
uint32_t gart_page_size;
uint32_t gart_size_kb;
uint32_t vram_size_kb;
uint64_t gart_size;
uint64_t vram_size;
uint64_t vram_vis_size;
uint64_t vram_vis_size_kb;
uint32_t vram_type;
uint32_t max_heap_size_kb;
uint32_t min_alloc_size;

2
src/amd/common/ac_rgp.c
View File

@ -487,7 +487,7 @@ static void ac_sqtt_fill_asic_info(struct radeon_info *rad_info,
chunk->ce_ram_size_compute = 0;
chunk->vram_bus_width = rad_info->memory_bus_width;
chunk->vram_size = rad_info->vram_size;
chunk->vram_size = (uint64_t)rad_info->vram_size_kb * 1024;
chunk->l2_cache_size = rad_info->l2_cache_size;
chunk->l1_cache_size = rad_info->l1_cache_size;
chunk->lds_size = rad_info->lds_size_per_workgroup;

10
src/amd/vulkan/radv_device.c
View File

@ -164,21 +164,21 @@ radv_get_adjusted_vram_size(struct radv_physical_device *device)
{
int ov = driQueryOptioni(&device->instance->dri_options, "override_vram_size");
if (ov >= 0)
return MIN2(device->rad_info.vram_size, (uint64_t)ov << 20);
return device->rad_info.vram_size;
return MIN2((uint64_t)device->rad_info.vram_size_kb * 1024, (uint64_t)ov << 20);
return (uint64_t)device->rad_info.vram_size_kb * 1024;
}
static uint64_t
radv_get_visible_vram_size(struct radv_physical_device *device)
{
return MIN2(radv_get_adjusted_vram_size(device), device->rad_info.vram_vis_size);
return MIN2(radv_get_adjusted_vram_size(device), (uint64_t)device->rad_info.vram_vis_size_kb * 1024);
}
static uint64_t
radv_get_vram_size(struct radv_physical_device *device)
{
uint64_t total_size = radv_get_adjusted_vram_size(device);
return total_size - MIN2(total_size, device->rad_info.vram_vis_size);
return total_size - MIN2(total_size, (uint64_t)device->rad_info.vram_vis_size_kb * 1024);
}
enum radv_heap {
@ -193,7 +193,7 @@ radv_physical_device_init_mem_types(struct radv_physical_device *device)
{
uint64_t visible_vram_size = radv_get_visible_vram_size(device);
uint64_t vram_size = radv_get_vram_size(device);
uint64_t gtt_size = device->rad_info.gart_size;
uint64_t gtt_size = (uint64_t)device->rad_info.gart_size_kb * 1024;
int vram_index = -1, visible_vram_index = -1, gart_index = -1;
device->memory_properties.memoryHeapCount = 0;

2
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
View File

@ -213,7 +213,7 @@ radv_amdgpu_cs_domain(const struct radeon_winsys *_ws)
const struct radv_amdgpu_winsys *ws = (const struct radv_amdgpu_winsys *)_ws;
bool enough_vram = ws->info.all_vram_visible ||
p_atomic_read_relaxed(&ws->allocated_vram_vis) * 2 <= ws->info.vram_vis_size;
p_atomic_read_relaxed(&ws->allocated_vram_vis) * 2 <= (uint64_t)ws->info.vram_vis_size_kb * 1024;
bool use_sam =
(enough_vram && ws->info.has_dedicated_vram && !(ws->perftest & RADV_PERFTEST_NO_SAM)) ||
(ws->perftest & RADV_PERFTEST_SAM);

6
src/gallium/drivers/r300/r300_context.c
View File

@ -511,7 +511,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
#endif
fprintf(stderr,
"r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
"r300: GART size: %"PRIu64" MB, VRAM size: %"PRIu64" MB\n"
"r300: GART size: %u MB, VRAM size: %u MB\n"
"r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
r300->screen->info.drm_major,
r300->screen->info.drm_minor,
@ -520,8 +520,8 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
r300->screen->info.pci_id,
r300->screen->info.r300_num_gb_pipes,
r300->screen->info.r300_num_z_pipes,
r300->screen->info.gart_size >> 20,
r300->screen->info.vram_size >> 20,
r300->screen->info.gart_size_kb >> 10,
r300->screen->info.vram_size_kb >> 10,
"YES", /* XXX really? */
r300->screen->caps.zmask_ram ? "YES" : "NO",
r300->screen->caps.hiz_ram ? "YES" : "NO");

2
src/gallium/drivers/r300/r300_screen.c
View File

@ -230,7 +230,7 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_ACCELERATED:
return 1;
case PIPE_CAP_VIDEO_MEMORY:
return r300screen->info.vram_size >> 20;
return r300screen->info.vram_size_kb >> 10;
case PIPE_CAP_UMA:
return 0;
case PIPE_CAP_PCI_GROUP:

4
src/gallium/drivers/r300/r300_texture.c
View File

@ -1074,12 +1074,12 @@ r300_texture_create_object(struct r300_screen *rscreen,
/* Figure out the ideal placement for the texture.. */
if (tex->domain & RADEON_DOMAIN_VRAM &&
tex->tex.size_in_bytes >= rscreen->info.vram_size) {
tex->tex.size_in_bytes >= (uint64_t)rscreen->info.vram_size_kb * 1024) {
tex->domain &= ~RADEON_DOMAIN_VRAM;
tex->domain |= RADEON_DOMAIN_GTT;
}
if (tex->domain & RADEON_DOMAIN_GTT &&
tex->tex.size_in_bytes >= rscreen->info.gart_size) {
tex->tex.size_in_bytes >= (uint64_t)rscreen->info.gart_size_kb * 1024) {
tex->domain &= ~RADEON_DOMAIN_GTT;
}
/* Just fail if the texture is too large. */

6
src/gallium/drivers/r600/r600_cs.h
View File

@ -49,11 +49,11 @@ radeon_cs_memory_below_limit(struct r600_common_screen *screen,
gtt += (uint64_t)cs->used_gart_kb * 1024;
/* Anything that goes above the VRAM size should go to GTT. */
if (vram > screen->info.vram_size)
gtt += vram - screen->info.vram_size;
if (vram > (uint64_t)screen->info.vram_size_kb * 1024)
gtt += vram - (uint64_t)screen->info.vram_size_kb * 1024;
/* Now we just need to check if we have enough GTT. */
return gtt < screen->info.gart_size * 0.7;
return gtt < (uint64_t)screen->info.gart_size_kb * 1024 * 0.7;
}
/**

2
src/gallium/drivers/r600/r600_pipe.c
View File

@ -522,7 +522,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_ACCELERATED:
return 1;
case PIPE_CAP_VIDEO_MEMORY:
return rscreen->b.info.vram_size >> 20;
return rscreen->b.info.vram_size_kb >> 10;
case PIPE_CAP_UMA:
return 0;
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:

10
src/gallium/drivers/r600/r600_pipe_common.c
View File

@ -1137,8 +1137,8 @@ static void r600_query_memory_info(struct pipe_screen *screen,
struct radeon_winsys *ws = rscreen->ws;
unsigned vram_usage, gtt_usage;
info->total_device_memory = rscreen->info.vram_size / 1024;
info->total_staging_memory = rscreen->info.gart_size / 1024;
info->total_device_memory = rscreen->info.vram_size_kb;
info->total_staging_memory = rscreen->info.gart_size_kb;
/* The real TTM memory usage is somewhat random, because:
*
@ -1286,9 +1286,9 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
printf("gfx_level = %i\n", rscreen->info.gfx_level);
printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size_kb, 1024));
printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size_kb, 1024));
printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size_kb, 1024));
printf("max_heap_size = %i MB\n",
(int)DIV_ROUND_UP(rscreen->info.max_heap_size_kb, 1024));
printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);

6
src/gallium/drivers/r600/r600_query.c
View File

@ -2058,18 +2058,18 @@ static int r600_get_driver_query_info(struct pipe_screen *screen,
case R600_QUERY_REQUESTED_VRAM:
case R600_QUERY_VRAM_USAGE:
case R600_QUERY_MAPPED_VRAM:
info->max_value.u64 = rscreen->info.vram_size;
info->max_value.u64 = (uint64_t)rscreen->info.vram_size_kb * 1024;
break;
case R600_QUERY_REQUESTED_GTT:
case R600_QUERY_GTT_USAGE:
case R600_QUERY_MAPPED_GTT:
info->max_value.u64 = rscreen->info.gart_size;
info->max_value.u64 = (uint64_t)rscreen->info.gart_size_kb * 1024;
break;
case R600_QUERY_GPU_TEMPERATURE:
info->max_value.u64 = 125;
break;
case R600_QUERY_VRAM_VIS_USAGE:
info->max_value.u64 = rscreen->info.vram_vis_size;
info->max_value.u64 = (uint64_t)rscreen->info.vram_vis_size_kb * 1024;
break;
}

2
src/gallium/drivers/r600/r600_texture.c
View File

@ -1506,7 +1506,7 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
*
* The result is that the kernel memory manager is never a bottleneck.
*/
if (rctx->num_alloc_tex_transfer_bytes > rctx->screen->info.gart_size / 4) {
if (rctx->num_alloc_tex_transfer_bytes > (uint64_t)rctx->screen->info.gart_size_kb * 1024 / 4) {
rctx->gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
rctx->num_alloc_tex_transfer_bytes = 0;
}

2
src/gallium/drivers/radeonsi/si_get.c
View File

@ -393,7 +393,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_DEVICE_ID:
return sscreen->info.pci_id;
case PIPE_CAP_VIDEO_MEMORY:
return sscreen->info.vram_size >> 20;
return sscreen->info.vram_size_kb >> 10;
case PIPE_CAP_PCI_GROUP:
return sscreen->info.pci_domain;
case PIPE_CAP_PCI_BUS:

6
src/gallium/drivers/radeonsi/si_query.c
View File

@ -1885,19 +1885,19 @@ static int si_get_driver_query_info(struct pipe_screen *screen, unsigned index,
case SI_QUERY_VRAM_USAGE:
case SI_QUERY_MAPPED_VRAM:
case SI_QUERY_SLAB_WASTED_VRAM:
info->max_value.u64 = sscreen->info.vram_size;
info->max_value.u64 = (uint64_t)sscreen->info.vram_size_kb * 1024;
break;
case SI_QUERY_REQUESTED_GTT:
case SI_QUERY_GTT_USAGE:
case SI_QUERY_MAPPED_GTT:
case SI_QUERY_SLAB_WASTED_GTT:
info->max_value.u64 = sscreen->info.gart_size;
info->max_value.u64 = (uint64_t)sscreen->info.gart_size_kb * 1024;
break;
case SI_QUERY_GPU_TEMPERATURE:
info->max_value.u64 = 125;
break;
case SI_QUERY_VRAM_VIS_USAGE:
info->max_value.u64 = sscreen->info.vram_vis_size;
info->max_value.u64 = (uint64_t)sscreen->info.vram_vis_size_kb * 1024;
break;
}

2
src/gallium/drivers/radeonsi/si_texture.c
View File

@ -1981,7 +1981,7 @@ static void si_texture_transfer_unmap(struct pipe_context *ctx, struct pipe_tran
*
* The result is that the kernel memory manager is never a bottleneck.
*/
if (sctx->num_alloc_tex_transfer_bytes > sctx->screen->info.gart_size / 4) {
if (sctx->num_alloc_tex_transfer_bytes > (uint64_t)sctx->screen->info.gart_size_kb * 1024 / 4) {
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
sctx->num_alloc_tex_transfer_bytes = 0;
}

2
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View File

@ -453,7 +453,7 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
/* Create managers. */
pb_cache_init(&aws->bo_cache, RADEON_NUM_HEAPS,
500000, aws->check_vm ? 1.0f : 2.0f, 0,
(aws->info.vram_size + aws->info.gart_size) / 8, aws,
((uint64_t)aws->info.vram_size_kb + aws->info.gart_size_kb) * 1024 / 8, aws,
/* Cast to void* because one of the function parameters
* is a struct pointer instead of void*. */
(void*)amdgpu_bo_destroy, (void*)amdgpu_bo_can_reclaim);

13
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View File

@ -360,17 +360,14 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
retval);
return false;
}
ws->info.gart_size = gem_info.gart_size;
ws->info.vram_size = gem_info.vram_size;
ws->info.vram_vis_size = gem_info.vram_visible;
ws->info.gart_size_kb = DIV_ROUND_UP(gem_info.gart_size, 1024);
ws->info.vram_size_kb = DIV_ROUND_UP(gem_info.vram_size, 1024);
ws->info.vram_vis_size_kb = DIV_ROUND_UP(gem_info.vram_visible, 1024);
/* Older versions of the kernel driver reported incorrect values, and
* didn't support more than 256MB of visible VRAM anyway
*/
if (ws->info.drm_minor < 49)
ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024);
ws->info.gart_size_kb = DIV_ROUND_UP(ws->info.gart_size, 1024);
ws->info.vram_size_kb = DIV_ROUND_UP(ws->info.vram_size, 1024);
ws->info.vram_vis_size_kb = MIN2(ws->info.vram_vis_size_kb, 256*1024);
/* Radeon allocates all buffers contiguously, which makes large allocations
* unlikely to succeed. */
@ -859,7 +856,7 @@ radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
pb_cache_init(&ws->bo_cache, RADEON_NUM_HEAPS,
500000, ws->check_vm ? 1.0f : 2.0f, 0,
MIN2(ws->info.vram_size, ws->info.gart_size), NULL,
(uint64_t)MIN2(ws->info.vram_size_kb, ws->info.gart_size_kb) * 1024, NULL,
radeon_bo_destroy,
radeon_bo_can_reclaim);