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amd: require amdgpu DRM 3.2.0 from April 2016 

This removes an early bug workaround.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
This commit is contained in:
Marek Olšák 2022-07-07 20:08:43 -04:00 committed by Marge Bot
parent ff19666a0d
commit 3657cdafd6
5 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/amd/common/ac_gpu_info.c
View File

@ -538,6 +538,13 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
assert(info->drm_major == 3);
info->is_amdgpu = true;
if (info->drm_minor < 2) {
fprintf(stderr, "amdgpu: DRM version is %u.%u.%u, but this driver is "
"only compatible with 3.2.0 (kernel 4.7) or later.\n",
info->drm_major, info->drm_minor, info->drm_patchlevel);
return false;
}
/* Query hardware and driver information. */
r = amdgpu_query_gpu_info(dev, amdinfo);
if (r) {
@ -888,8 +895,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->has_gpu_reset_status_query = true;
info->has_eqaa_surface_allocator = info->gfx_level < GFX11;
info->has_format_bc1_through_bc7 = true;
/* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
info->kernel_flushes_tc_l2_after_ib = info->gfx_level != GFX8 || info->drm_minor >= 2;
info->has_indirect_compute_dispatch = true;
/* GFX6 doesn't support unaligned loads. */
info->has_unaligned_shader_loads = info->gfx_level != GFX6;
@ -1500,7 +1505,6 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
fprintf(f, " has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
fprintf(f, " has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
fprintf(f, " has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
fprintf(f, " kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
fprintf(f, " has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
fprintf(f, " has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
fprintf(f, " has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);

1
src/amd/common/ac_gpu_info.h
View File

@ -190,7 +190,6 @@ struct radeon_info {
bool has_gpu_reset_status_query;
bool has_eqaa_surface_allocator;
bool has_format_bc1_through_bc7;
bool kernel_flushes_tc_l2_after_ib;
bool has_indirect_compute_dispatch;
bool has_unaligned_shader_loads;
bool has_sparse_vm_mappings;

4
src/gallium/drivers/radeonsi/si_debug.c
View File

@ -308,8 +308,8 @@ static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
fprintf(f, "Memory-mapped registers:\n");
si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
/* No other registers can be read on DRM < 3.1.0. */
if (!sctx->screen->info.is_amdgpu || sctx->screen->info.drm_minor < 1) {
/* No other registers can be read on radeon. */
if (!sctx->screen->info.is_amdgpu) {
fprintf(f, "\n");
return;
}

4
src/gallium/drivers/radeonsi/si_gfx_cs.c
View File

@ -55,9 +55,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h
if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 39)
flags |= RADEON_FLUSH_START_NEXT_GFX_IB_NOW;
if (!sscreen->info.kernel_flushes_tc_l2_after_ib) {
wait_flags |= wait_ps_cs | SI_CONTEXT_INV_L2;
} else if (ctx->gfx_level == GFX6) {
if (ctx->gfx_level == GFX6) {
/* The kernel flushes L2 before shaders are finished. */
wait_flags |= wait_ps_cs;
} else if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW) ||

1
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View File

@ -586,7 +586,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43;
ws->info.has_eqaa_surface_allocator = false;
ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
ws->info.kernel_flushes_tc_l2_after_ib = true;
/* Old kernels disallowed register writes via COPY_DATA
* that are used for indirect compute dispatches. */
ws->info.has_indirect_compute_dispatch = ws->info.gfx_level == GFX7 ||