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gallium/radeon: require radeon DRM 2.50.0 (kernel 4.12) from July 2017 

This is the latest radeon DRM version.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
This commit is contained in:
Marek Olšák 2022-07-11 00:43:07 -04:00 committed by Marge Bot
parent 8426cf9132
commit 9f6a64b1c3
5 changed files with 4 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/amd/common/ac_gpu_info.c
View File

@ -964,7 +964,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
info->has_timeline_syncobj = has_timeline_syncobj(fd);
info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
info->has_local_buffers = info->drm_minor >= 20;
info->si_TA_CS_BC_BASE_ADDR_allowed = true;
info->has_bo_metadata = true;
info->has_eqaa_surface_allocator = info->gfx_level < GFX11;
/* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
@ -1565,7 +1564,6 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
fprintf(f, " has_timeline_syncobj = %u\n", info->has_timeline_syncobj);
fprintf(f, " has_fence_to_handle = %u\n", info->has_fence_to_handle);
fprintf(f, " has_local_buffers = %u\n", info->has_local_buffers);
fprintf(f, " si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
fprintf(f, " has_bo_metadata = %u\n", info->has_bo_metadata);
fprintf(f, " has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
fprintf(f, " has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);

1
src/amd/common/ac_gpu_info.h
View File

@ -183,7 +183,6 @@ struct radeon_info {
bool has_timeline_syncobj;
bool has_fence_to_handle;
bool has_local_buffers;
bool si_TA_CS_BC_BASE_ADDR_allowed;
bool has_bo_metadata;
bool has_eqaa_surface_allocator;
bool has_sparse_vm_mappings;

3
src/gallium/drivers/r600/r600_hw_context.c
View File

@ -438,8 +438,7 @@ void r600_emit_pfp_sync_me(struct r600_context *rctx)
{
struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
if (rctx->b.gfx_level >= EVERGREEN &&
rctx->b.screen->info.drm_minor >= 46) {
if (rctx->b.gfx_level >= EVERGREEN) {
radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
radeon_emit(cs, 0);
} else {

7
src/gallium/drivers/radeonsi/si_compute.c
View File

@ -394,12 +394,7 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
* (number of compute units) * 4 * (waves per simd) - 1
*/
radeon_set_sh_reg(R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
uint64_t bc_va = sctx->border_color_buffer->gpu_address;
radeon_set_config_reg(R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
}
radeon_set_config_reg(R_00950C_TA_CS_BC_BASE_ADDR, sctx->border_color_buffer->gpu_address >> 8);
}
if (sctx->gfx_level >= GFX7) {

10
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View File

@ -153,9 +153,9 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
/* Get DRM version. */
version = drmGetVersion(ws->fd);
if (version->version_major != 2 ||
version->version_minor < 45) {
version->version_minor < 50) {
fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
"only compatible with 2.45.0 (kernel 4.7) or later.\n",
"only compatible with 2.50.0 (kernel 4.12) or later.\n",
__FUNCTION__,
version->version_major,
version->version_minor,
@ -358,11 +358,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.gart_size_kb = DIV_ROUND_UP(gem_info.gart_size, 1024);
ws->info.vram_size_kb = DIV_ROUND_UP(gem_info.vram_size, 1024);
ws->info.vram_vis_size_kb = DIV_ROUND_UP(gem_info.vram_visible, 1024);
/* Older versions of the kernel driver reported incorrect values, and
* didn't support more than 256MB of visible VRAM anyway
*/
if (ws->info.drm_minor < 49)
ws->info.vram_vis_size_kb = MIN2(ws->info.vram_vis_size_kb, 256*1024);
/* Radeon allocates all buffers contiguously, which makes large allocations
* unlikely to succeed. */
@ -570,7 +565,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->accel_working2 < 3);
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
ws->info.ib_alignment = 4096;
ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
ws->info.has_bo_metadata = false;
ws->info.has_eqaa_surface_allocator = false;
ws->info.has_sparse_vm_mappings = false;