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mesa/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp

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i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
/*
* Copyright © 2011 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include "brw_vec4.h"
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
#include "brw_cfg.h"
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
#include "glsl/ir_uniform.h"
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
#include "program/sampler.h"
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
namespace brw {
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst,
i965/vec4: Pass const references to vec4_instruction(). text data bss dec hex filename 4244821 123200 39648 4407669 434175 i965_dri.so 4231165 123200 39648 4394013 430c1d i965_dri.so Cuts 13k of .text and saves a bunch of useless struct copies. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-28 21:46:29 +01:00
const src_reg &src0, const src_reg &src1,
const src_reg &src2)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
i965/vs: Restructure emit() functions around a vec4_instruction constructor. We sometimes want to put an instruction somewhere besides the end of the instruction stream, and we also want per-opcode instruction generation to enable compile-time checking of operands.
2011-08-27 00:37:37 +01:00
this->opcode = opcode;
this->dst = dst;
this->src[0] = src0;
this->src[1] = src1;
this->src[2] = src2;
i965: Initialize all member variables of vec4_instruction on construction. The vec4_instruction object relies on the memory allocator zeroing out its contents before it's initialized, which is quite an unusual practice in the C++ world because it ties objects to some specific allocation scheme, and gives unpredictable results when an object is created with a different allocator -- Stack allocation, array allocation, or aggregation inside a different object are some of the useful possibilities that come to my mind. Initialize all fields from the constructor and stop using the zeroing allocator. Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-12 00:20:18 +01:00
this->saturate = false;
this->force_writemask_all = false;
this->no_dd_clear = false;
this->no_dd_check = false;
i965: Add writes_accumulator flag Our hardware has an "accumulator" register, which can be used to store intermediate results across multiple instructions. Many instructions can implicitly write a value to the accumulator in addition to their normal destination register. This is enabled by the "AccWrEn" flag. This patch introduces a new flag, inst->writes_accumulator, which allows us to express the AccWrEn notion in the IR. It also creates a n ALU2_ACC macro to easily define emitters for instructions that implicitly write the accumulator. Previously, we only supported implicit accumulator writes from the ADDC, SUBB, and MACH instructions. We always enabled them on those instructions, and left them disabled for other instructions. To take advantage of the MAC (multiply-accumulate) instruction, we need to be able to set AccWrEn on other types of instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-04-04 14:51:59 +01:00
this->writes_accumulator = false;
i965: Initialize all member variables of vec4_instruction on construction. The vec4_instruction object relies on the memory allocator zeroing out its contents before it's initialized, which is quite an unusual practice in the C++ world because it ties objects to some specific allocation scheme, and gives unpredictable results when an object is created with a different allocator -- Stack allocation, array allocation, or aggregation inside a different object are some of the useful possibilities that come to my mind. Initialize all fields from the constructor and stop using the zeroing allocator. Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-12 00:20:18 +01:00
this->conditional_mod = BRW_CONDITIONAL_NONE;
i965/vec4: Initialize vec4_instruction::predicate and ::predicate_inverse. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-03 13:31:46 +00:00
this->predicate = BRW_PREDICATE_NONE;
this->predicate_inverse = false;
i965: Initialize all member variables of vec4_instruction on construction. The vec4_instruction object relies on the memory allocator zeroing out its contents before it's initialized, which is quite an unusual practice in the C++ world because it ties objects to some specific allocation scheme, and gives unpredictable results when an object is created with a different allocator -- Stack allocation, array allocation, or aggregation inside a different object are some of the useful possibilities that come to my mind. Initialize all fields from the constructor and stop using the zeroing allocator. Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-12 00:20:18 +01:00
this->target = 0;
i965: Move up fs_inst::regs_written to backend_instruction. It will also be useful in the VEC4 back-end. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:27:40 +00:00
this->regs_written = (dst.file == BAD_FILE ? 0 : 1);
i965: Initialize all member variables of vec4_instruction on construction. The vec4_instruction object relies on the memory allocator zeroing out its contents before it's initialized, which is quite an unusual practice in the C++ world because it ties objects to some specific allocation scheme, and gives unpredictable results when an object is created with a different allocator -- Stack allocation, array allocation, or aggregation inside a different object are some of the useful possibilities that come to my mind. Initialize all fields from the constructor and stop using the zeroing allocator. Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-12 00:20:18 +01:00
this->shadow_compare = false;
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
this->ir = NULL;
i965: Initialize all member variables of vec4_instruction on construction. The vec4_instruction object relies on the memory allocator zeroing out its contents before it's initialized, which is quite an unusual practice in the C++ world because it ties objects to some specific allocation scheme, and gives unpredictable results when an object is created with a different allocator -- Stack allocation, array allocation, or aggregation inside a different object are some of the useful possibilities that come to my mind. Initialize all fields from the constructor and stop using the zeroing allocator. Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-12 00:20:18 +01:00
this->urb_write_flags = BRW_URB_WRITE_NO_FLAGS;
this->header_present = false;
i965: Move up fs_inst::flag_subreg to backend_instruction. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:28:12 +00:00
this->flag_subreg = 0;
i965: Initialize all member variables of vec4_instruction on construction. The vec4_instruction object relies on the memory allocator zeroing out its contents before it's initialized, which is quite an unusual practice in the C++ world because it ties objects to some specific allocation scheme, and gives unpredictable results when an object is created with a different allocator -- Stack allocation, array allocation, or aggregation inside a different object are some of the useful possibilities that come to my mind. Initialize all fields from the constructor and stop using the zeroing allocator. Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-12 00:20:18 +01:00
this->mlen = 0;
this->base_mrf = 0;
this->offset = 0;
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
this->annotation = NULL;
i965/vs: Restructure emit() functions around a vec4_instruction constructor. We sometimes want to put an instruction somewhere besides the end of the instruction stream, and we also want per-opcode instruction generation to enable compile-time checking of operands.
2011-08-27 00:37:37 +01:00
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: Restructure emit() functions around a vec4_instruction constructor. We sometimes want to put an instruction somewhere besides the end of the instruction stream, and we also want per-opcode instruction generation to enable compile-time checking of operands.
2011-08-27 00:37:37 +01:00
vec4_instruction *
vec4_visitor::emit(vec4_instruction *inst)
{
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
inst->ir = this->base_ir;
inst->annotation = this->current_annotation;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
this->instructions.push_tail(inst);
return inst;
}
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 19:13:33 +01:00
vec4_instruction *
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
vec4_visitor::emit_before(bblock_t *block, vec4_instruction *inst,
vec4_instruction *new_inst)
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 19:13:33 +01:00
{
new_inst->ir = inst->ir;
new_inst->annotation = inst->annotation;
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
inst->insert_before(block, new_inst);
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 19:13:33 +01:00
return inst;
}
i965/vs: Restructure emit() functions around a vec4_instruction constructor. We sometimes want to put an instruction somewhere besides the end of the instruction stream, and we also want per-opcode instruction generation to enable compile-time checking of operands.
2011-08-27 00:37:37 +01:00
vec4_instruction *
i965/vec4: Use const references in emit() functions. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-11-11 01:20:37 +00:00
vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
const src_reg &src1, const src_reg &src2)
i965/vs: Restructure emit() functions around a vec4_instruction constructor. We sometimes want to put an instruction somewhere besides the end of the instruction stream, and we also want per-opcode instruction generation to enable compile-time checking of operands.
2011-08-27 00:37:37 +01:00
{
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1, src2));
i965/vs: Restructure emit() functions around a vec4_instruction constructor. We sometimes want to put an instruction somewhere besides the end of the instruction stream, and we also want per-opcode instruction generation to enable compile-time checking of operands.
2011-08-27 00:37:37 +01:00
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
vec4_instruction *
i965/vec4: Use const references in emit() functions. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-11-11 01:20:37 +00:00
vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
const src_reg &src1)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
vec4_instruction *
i965/vec4: Use const references in emit() functions. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-11-11 01:20:37 +00:00
vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vec4: Add the ability to emit opcodes with just a dst register. This is needed for GS_OPCODE_PREPARE_CHANNEL_MASKS. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-21 16:51:33 +01:00
vec4_instruction *
i965/vec4: Use const references in emit() functions. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-11-11 01:20:37 +00:00
vec4_visitor::emit(enum opcode opcode, const dst_reg &dst)
i965/vec4: Add the ability to emit opcodes with just a dst register. This is needed for GS_OPCODE_PREPARE_CHANNEL_MASKS. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-21 16:51:33 +01:00
{
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
return emit(new(mem_ctx) vec4_instruction(opcode, dst));
i965/vec4: Add the ability to emit opcodes with just a dst register. This is needed for GS_OPCODE_PREPARE_CHANNEL_MASKS. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-21 16:51:33 +01:00
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
vec4_instruction *
vec4_visitor::emit(enum opcode opcode)
{
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
return emit(new(mem_ctx) vec4_instruction(opcode, dst_reg()));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
#define ALU1(op) \
vec4_instruction * \
i965/vec4: Pass const references to instruction functions. text data bss dec hex filename 4231165 123200 39648 4394013 430c1d i965_dri.so 4186277 123200 39648 4349125 425cc5 i965_dri.so Cuts 43k of .text and saves a bunch of useless struct copies. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-28 21:53:55 +01:00
vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
{ \
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, src0); \
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
}
#define ALU2(op) \
vec4_instruction * \
i965/vec4: Pass const references to instruction functions. text data bss dec hex filename 4231165 123200 39648 4394013 430c1d i965_dri.so 4186277 123200 39648 4349125 425cc5 i965_dri.so Cuts 43k of .text and saves a bunch of useless struct copies. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-28 21:53:55 +01:00
vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
const src_reg &src1) \
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
{ \
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
src0, src1); \
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
}
i965: Add writes_accumulator flag Our hardware has an "accumulator" register, which can be used to store intermediate results across multiple instructions. Many instructions can implicitly write a value to the accumulator in addition to their normal destination register. This is enabled by the "AccWrEn" flag. This patch introduces a new flag, inst->writes_accumulator, which allows us to express the AccWrEn notion in the IR. It also creates a n ALU2_ACC macro to easily define emitters for instructions that implicitly write the accumulator. Previously, we only supported implicit accumulator writes from the ADDC, SUBB, and MACH instructions. We always enabled them on those instructions, and left them disabled for other instructions. To take advantage of the MAC (multiply-accumulate) instruction, we need to be able to set AccWrEn on other types of instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-04-04 14:51:59 +01:00
#define ALU2_ACC(op) \
vec4_instruction * \
i965/vec4: Pass const references to instruction functions. text data bss dec hex filename 4231165 123200 39648 4394013 430c1d i965_dri.so 4186277 123200 39648 4349125 425cc5 i965_dri.so Cuts 43k of .text and saves a bunch of useless struct copies. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-28 21:53:55 +01:00
vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
const src_reg &src1) \
i965: Add writes_accumulator flag Our hardware has an "accumulator" register, which can be used to store intermediate results across multiple instructions. Many instructions can implicitly write a value to the accumulator in addition to their normal destination register. This is enabled by the "AccWrEn" flag. This patch introduces a new flag, inst->writes_accumulator, which allows us to express the AccWrEn notion in the IR. It also creates a n ALU2_ACC macro to easily define emitters for instructions that implicitly write the accumulator. Previously, we only supported implicit accumulator writes from the ADDC, SUBB, and MACH instructions. We always enabled them on those instructions, and left them disabled for other instructions. To take advantage of the MAC (multiply-accumulate) instruction, we need to be able to set AccWrEn on other types of instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-04-04 14:51:59 +01:00
{ \
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
vec4_instruction *inst = new(mem_ctx) vec4_instruction( \
i965: Add writes_accumulator flag Our hardware has an "accumulator" register, which can be used to store intermediate results across multiple instructions. Many instructions can implicitly write a value to the accumulator in addition to their normal destination register. This is enabled by the "AccWrEn" flag. This patch introduces a new flag, inst->writes_accumulator, which allows us to express the AccWrEn notion in the IR. It also creates a n ALU2_ACC macro to easily define emitters for instructions that implicitly write the accumulator. Previously, we only supported implicit accumulator writes from the ADDC, SUBB, and MACH instructions. We always enabled them on those instructions, and left them disabled for other instructions. To take advantage of the MAC (multiply-accumulate) instruction, we need to be able to set AccWrEn on other types of instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-04-04 14:51:59 +01:00
BRW_OPCODE_##op, dst, src0, src1); \
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
inst->writes_accumulator = true; \
return inst; \
i965: Add writes_accumulator flag Our hardware has an "accumulator" register, which can be used to store intermediate results across multiple instructions. Many instructions can implicitly write a value to the accumulator in addition to their normal destination register. This is enabled by the "AccWrEn" flag. This patch introduces a new flag, inst->writes_accumulator, which allows us to express the AccWrEn notion in the IR. It also creates a n ALU2_ACC macro to easily define emitters for instructions that implicitly write the accumulator. Previously, we only supported implicit accumulator writes from the ADDC, SUBB, and MACH instructions. We always enabled them on those instructions, and left them disabled for other instructions. To take advantage of the MAC (multiply-accumulate) instruction, we need to be able to set AccWrEn on other types of instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-04-04 14:51:59 +01:00
}
i965/vs: Add support for LRP instruction. Only 13 affected programs in shader-db, but they were all helped. total instructions in shared programs: 368877 -> 368851 (-0.01%) instructions in affected programs: 1576 -> 1550 (-1.65%) Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-04-25 19:03:38 +01:00
#define ALU3(op) \
vec4_instruction * \
i965/vec4: Pass const references to instruction functions. text data bss dec hex filename 4231165 123200 39648 4394013 430c1d i965_dri.so 4186277 123200 39648 4349125 425cc5 i965_dri.so Cuts 43k of .text and saves a bunch of useless struct copies. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-28 21:53:55 +01:00
vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
const src_reg &src1, const src_reg &src2) \
i965/vs: Add support for LRP instruction. Only 13 affected programs in shader-db, but they were all helped. total instructions in shared programs: 368877 -> 368851 (-0.01%) instructions in affected programs: 1576 -> 1550 (-1.65%) Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-04-25 19:03:38 +01:00
{ \
i965/vec4: Add a brw->gen >= 6 assertion in three-source emitters. Three source instructions didn't exist until Gen6. vec4_generator has assertions to catch this, but catching it in the visitor provides a nicer backtrace. Cc: "10.1" <mesa-stable@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Acked-by: Eric Anholt <eric@anholt.net>
2014-02-24 00:08:56 +00:00
assert(brw->gen >= 6); \
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
i965/vs: Add support for LRP instruction. Only 13 affected programs in shader-db, but they were all helped. total instructions in shared programs: 368877 -> 368851 (-0.01%) instructions in affected programs: 1576 -> 1550 (-1.65%) Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-04-25 19:03:38 +01:00
src0, src1, src2); \
}
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
ALU1(NOT)
ALU1(MOV)
ALU1(FRC)
ALU1(RNDD)
ALU1(RNDE)
ALU1(RNDZ)
i965/vs/gen7: Emit code for GLSL ES 3.00 pack/unpack operations (v3) FIXME: This patch emits VS code that violates documented hardware restrictions and then relies on undocumented behavior that results from that violation. This patch passes all tests, but should be fixed ASAP to conform to the hardware documentation. v2: Explain undocumented hardware behavior. Improve comments. v3: Use ALU1 helper methods F32TO16() and F16TO32(). [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:44:31 +00:00
ALU1(F32TO16)
ALU1(F16TO32)
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
ALU2(ADD)
ALU2(MUL)
i965: Add writes_accumulator flag Our hardware has an "accumulator" register, which can be used to store intermediate results across multiple instructions. Many instructions can implicitly write a value to the accumulator in addition to their normal destination register. This is enabled by the "AccWrEn" flag. This patch introduces a new flag, inst->writes_accumulator, which allows us to express the AccWrEn notion in the IR. It also creates a n ALU2_ACC macro to easily define emitters for instructions that implicitly write the accumulator. Previously, we only supported implicit accumulator writes from the ADDC, SUBB, and MACH instructions. We always enabled them on those instructions, and left them disabled for other instructions. To take advantage of the MAC (multiply-accumulate) instruction, we need to be able to set AccWrEn on other types of instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-04-04 14:51:59 +01:00
ALU2_ACC(MACH)
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
ALU2(AND)
ALU2(OR)
ALU2(XOR)
ALU2(DP3)
ALU2(DP4)
i965/vs: Add support for emitting DPH opcodes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-10-08 18:26:13 +01:00
ALU2(DPH)
i965/vs: add support for emitting SHL, SHR, ASR Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-22 03:23:23 +00:00
ALU2(SHL)
ALU2(SHR)
ALU2(ASR)
i965/vs: Add support for LRP instruction. Only 13 affected programs in shader-db, but they were all helped. total instructions in shared programs: 368877 -> 368851 (-0.01%) instructions in affected programs: 1576 -> 1550 (-1.65%) Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-04-25 19:03:38 +01:00
ALU3(LRP)
i965/vs: Add support for bit instructions. v2: Rebase on LRP addition. Use fix_3src_operand() when emitting BFE and BFI2. Add BFE and BFI2 to is_3src_inst check in brw_vec4_copy_propagation.cpp. Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-04-18 02:57:58 +01:00
ALU1(BFREV)
ALU3(BFE)
ALU2(BFI1)
ALU3(BFI2)
ALU1(FBH)
ALU1(FBL)
ALU1(CBIT)
i965/vs: Add support for translating ir_triop_fma into MAD. Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-08-02 18:28:16 +01:00
ALU3(MAD)
i965: Add writes_accumulator flag Our hardware has an "accumulator" register, which can be used to store intermediate results across multiple instructions. Many instructions can implicitly write a value to the accumulator in addition to their normal destination register. This is enabled by the "AccWrEn" flag. This patch introduces a new flag, inst->writes_accumulator, which allows us to express the AccWrEn notion in the IR. It also creates a n ALU2_ACC macro to easily define emitters for instructions that implicitly write the accumulator. Previously, we only supported implicit accumulator writes from the ADDC, SUBB, and MACH instructions. We always enabled them on those instructions, and left them disabled for other instructions. To take advantage of the MAC (multiply-accumulate) instruction, we need to be able to set AccWrEn on other types of instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-04-04 14:51:59 +01:00
ALU2_ACC(ADDC)
ALU2_ACC(SUBB)
i965/vec4: Add support for the MAC instruction. This allows us to generate the MAC (multiply-accumulate) instruction, which can be used to implement some expressions in fewer instructions than doing a series of MUL and ADDs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-03-28 13:28:30 +00:00
ALU2(MAC)
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
/** Gen4 predicated IF. */
vec4_instruction *
i965: Make a brw_predicate enum. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-06-30 01:58:59 +01:00
vec4_visitor::IF(enum brw_predicate predicate)
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
{
vec4_instruction *inst;
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
inst = new(mem_ctx) vec4_instruction(BRW_OPCODE_IF);
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
inst->predicate = predicate;
return inst;
}
i965: Assert that IF with cmod is Gen6 only. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-11-14 18:36:12 +00:00
/** Gen6 IF with embedded comparison. */
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
vec4_instruction *
i965: Make a brw_conditional_mod enum. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-06-30 01:50:20 +01:00
vec4_visitor::IF(src_reg src0, src_reg src1,
enum brw_conditional_mod condition)
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
{
i965: Assert that IF with cmod is Gen6 only. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-11-14 18:36:12 +00:00
assert(brw->gen == 6);
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
vec4_instruction *inst;
i965/vs: Fix comparisons with uint negation. The condmod instruction ends up generating garbage condition codes, because apparently the comparison happens on the accumulator value (33 bits for UD), not the truncated value that would be written. Fixes vs-op-neg-* Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-10-03 23:31:52 +01:00
resolve_ud_negate(&src0);
resolve_ud_negate(&src1);
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
inst = new(mem_ctx) vec4_instruction(BRW_OPCODE_IF, dst_null_d(),
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
src0, src1);
inst->conditional_mod = condition;
return inst;
}
i965/vs: Move logic for weird CMP type handling to CMP generators. v2: Don't bother with the no-dst-reg version of CMP() Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:59:43 +01:00
/**
* CMP: Sets the low bit of the destination channels with the result
* of the comparison, while the upper bits are undefined, and updates
* the flag register with the packed 16 bits of the result.
*/
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
vec4_instruction *
i965: Make a brw_conditional_mod enum. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-06-30 01:50:20 +01:00
vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1,
enum brw_conditional_mod condition)
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
{
vec4_instruction *inst;
i965: Set CMP's destination type to src0's type. Allows CMP instructions with float sources to be compacted and coissued. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-01-07 19:52:05 +00:00
/* Take the instruction:
*
* CMP null<d> src0<f> src1<f>
*
* Original gen4 does type conversion to the destination type before
* comparison, producing garbage results for floating point comparisons.
*
* The destination type doesn't matter on newer generations, so we set the
* type to match src0 so we can compact the instruction.
i965/vs: Move logic for weird CMP type handling to CMP generators. v2: Don't bother with the no-dst-reg version of CMP() Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:59:43 +01:00
*/
i965: Set CMP's destination type to src0's type. Allows CMP instructions with float sources to be compacted and coissued. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-01-07 19:52:05 +00:00
dst.type = src0.type;
if (dst.file == HW_REG)
dst.fixed_hw_reg.type = dst.type;
i965/vs: Move logic for weird CMP type handling to CMP generators. v2: Don't bother with the no-dst-reg version of CMP() Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:59:43 +01:00
i965/vs: Fix comparisons with uint negation. The condmod instruction ends up generating garbage condition codes, because apparently the comparison happens on the accumulator value (33 bits for UD), not the truncated value that would be written. Fixes vs-op-neg-* Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-10-03 23:31:52 +01:00
resolve_ud_negate(&src0);
resolve_ud_negate(&src1);
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
inst = new(mem_ctx) vec4_instruction(BRW_OPCODE_CMP, dst, src0, src1);
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 00:43:06 +01:00
inst->conditional_mod = condition;
return inst;
}
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 19:13:33 +01:00
vec4_instruction *
i965/vec4: Pass const references to instruction functions. text data bss dec hex filename 4231165 123200 39648 4394013 430c1d i965_dri.so 4186277 123200 39648 4349125 425cc5 i965_dri.so Cuts 43k of .text and saves a bunch of useless struct copies. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-28 21:53:55 +01:00
vec4_visitor::SCRATCH_READ(const dst_reg &dst, const src_reg &index)
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 19:13:33 +01:00
{
vec4_instruction *inst;
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ,
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 19:13:33 +01:00
dst, index);
inst->base_mrf = 14;
i965/vs: Fix the mlen of scratch read/write messages. These messages always have m0 = g0 and m1 = offset, and write has m2 = data. Avoids regression in opt_compute_to_mrf() with a change to scratch writes to set up the data as an MRF write in the IR. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-04 00:15:07 +01:00
inst->mlen = 2;
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 19:13:33 +01:00
return inst;
}
vec4_instruction *
i965/vec4: Pass const references to instruction functions. text data bss dec hex filename 4231165 123200 39648 4394013 430c1d i965_dri.so 4186277 123200 39648 4349125 425cc5 i965_dri.so Cuts 43k of .text and saves a bunch of useless struct copies. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-28 21:53:55 +01:00
vec4_visitor::SCRATCH_WRITE(const dst_reg &dst, const src_reg &src,
const src_reg &index)
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 19:13:33 +01:00
{
vec4_instruction *inst;
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE,
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 19:13:33 +01:00
dst, src, index);
inst->base_mrf = 13;
i965/vs: Fix the mlen of scratch read/write messages. These messages always have m0 = g0 and m1 = offset, and write has m2 = data. Avoids regression in opt_compute_to_mrf() with a change to scratch writes to set up the data as an MRF write in the IR. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-04 00:15:07 +01:00
inst->mlen = 3;
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 19:13:33 +01:00
return inst;
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
void
vec4_visitor::emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements)
{
static enum opcode dot_opcodes[] = {
BRW_OPCODE_DP2, BRW_OPCODE_DP3, BRW_OPCODE_DP4
};
emit(dot_opcodes[elements - 2], dst, src0, src1);
}
i965/vs: Add a function to fix-up uniform arguments for 3-src insts. Three-source instructions have a vertical stride overloaded to 4, which prevents directly using vec4 uniforms as arguments. Instead we need to insert a MOV instruction to do the replication for the three-source instruction. With this in place, we can use three-source instructions in the vertex shader. While some thought needs to go into deciding whether its better to use a three-source instruction rather than a sequence of equivalent instructions (when one or more sources are uniforms or immediates), this will allow us to skip a lot of ugly lowering code and use the BFE and BFI2 instructions directly. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-04-25 19:02:02 +01:00
src_reg
vec4_visitor::fix_3src_operand(src_reg src)
{
/* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
* able to use vertical stride of zero to replicate the vec4 uniform, like
*
* g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
*
* But you can't, since vertical stride is always four in three-source
* instructions. Instead, insert a MOV instruction to do the replication so
* that the three-source instruction can consume it.
*/
/* The MOV is only needed if the source is a uniform or immediate. */
if (src.file != UNIFORM && src.file != IMM)
return src;
i965/vec4: Don't fix-up scalar uniforms for 3 src instructions. Removes unnecessary MOV instructions in L4D2, TF2, Dota2, and many other Steam games. total instructions in shared programs: 1668126 -> 1657509 (-0.64%) instructions in affected programs: 242235 -> 231618 (-4.38%) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-03-08 20:16:13 +00:00
if (src.file == UNIFORM && brw_is_single_value_swizzle(src.swizzle))
return src;
i965/vs: Add a function to fix-up uniform arguments for 3-src insts. Three-source instructions have a vertical stride overloaded to 4, which prevents directly using vec4 uniforms as arguments. Instead we need to insert a MOV instruction to do the replication for the three-source instruction. With this in place, we can use three-source instructions in the vertex shader. While some thought needs to go into deciding whether its better to use a three-source instruction rather than a sequence of equivalent instructions (when one or more sources are uniforms or immediates), this will allow us to skip a lot of ugly lowering code and use the BFE and BFI2 instructions directly. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-04-25 19:02:02 +01:00
dst_reg expanded = dst_reg(this, glsl_type::vec4_type);
expanded.type = src.type;
i965/vec4: Allow CSE on uniform-vec4 expansion MOVs. Three source instructions cannot directly source a packed vec4 (<0,4,1> regioning) like vec4 uniforms, so we emit a MOV that expands the vec4 to both halves of a register. If these uniform values are used by multiple three-source instructions, we'll emit multiple expansion moves, which we cannot combine in CSE (because CSE emits moves itself). So emit a virtual instruction that we can CSE. Sometimes we demote a uniform to to a pull constant after emitting an expansion move for it. In that case, recognize in opt_algebraic that if the .file of the new instruction is GRF then it's just a real move that we can copy propagate and such. total instructions in shared programs: 5822418 -> 5812335 (-0.17%) instructions in affected programs: 351841 -> 341758 (-2.87%) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-24 07:22:09 +01:00
emit(VEC4_OPCODE_UNPACK_UNIFORM, expanded, src);
i965/vs: Add a function to fix-up uniform arguments for 3-src insts. Three-source instructions have a vertical stride overloaded to 4, which prevents directly using vec4 uniforms as arguments. Instead we need to insert a MOV instruction to do the replication for the three-source instruction. With this in place, we can use three-source instructions in the vertex shader. While some thought needs to go into deciding whether its better to use a three-source instruction rather than a sequence of equivalent instructions (when one or more sources are uniforms or immediates), this will allow us to skip a lot of ugly lowering code and use the BFE and BFI2 instructions directly. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-04-25 19:02:02 +01:00
return src_reg(expanded);
}
i965/vs: Fix gen6+ math operand quirks in one place This causes immediate values to get moved to a temp on gen7, which is needed for an upcoming change but hadn't happened in the visitor until then. v2: Drop gen > 7 checks (doesn't exist), and style-fix comments (changes by anholt). Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-09 09:03:49 +00:00
src_reg
vec4_visitor::fix_math_operand(src_reg src)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
i965/vec4: Combine all the math emitters. 17 insertions(+), 102 deletions(-). Works just as well. v2: Make emit_math take const references (suggested by Matt), drop redundant WRITEMASK_XYZW setting (Matt and Curro). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-11-11 22:40:08 +00:00
if (brw->gen < 6 || brw->gen >= 8 || src.file == BAD_FILE)
return src;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
/* The gen6 math instruction ignores the source modifiers --
* swizzle, abs, negate, and at least some parts of the register
i965/vs: Apply the gen6 math workaround for math1 instructions. Fixes glsl-vs-masked-cos.
2011-08-06 04:16:21 +01:00
* region description.
i965/vs: Pack live uniform vectors together in the push constant upload. At some point we need to also move uniform accesses out to pull constants when there are just too many in use, but we lack tests for that at the moment. Fixes glsl-vs-large-uniform-array. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-23 20:13:14 +01:00
*
i965/vs: Fix gen6+ math operand quirks in one place This causes immediate values to get moved to a temp on gen7, which is needed for an upcoming change but hadn't happened in the visitor until then. v2: Drop gen > 7 checks (doesn't exist), and style-fix comments (changes by anholt). Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-09 09:03:49 +00:00
* Rather than trying to enumerate all these cases, *always* expand the
* operand to a temp GRF for gen6.
*
* For gen7, keep the operand as-is, except if immediate, which gen7 still
* can't use.
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
*/
i965/vs: Fix gen6+ math operand quirks in one place This causes immediate values to get moved to a temp on gen7, which is needed for an upcoming change but hadn't happened in the visitor until then. v2: Drop gen > 7 checks (doesn't exist), and style-fix comments (changes by anholt). Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-09 09:03:49 +00:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen == 7 && src.file != IMM)
i965/vs: Fix gen6+ math operand quirks in one place This causes immediate values to get moved to a temp on gen7, which is needed for an upcoming change but hadn't happened in the visitor until then. v2: Drop gen > 7 checks (doesn't exist), and style-fix comments (changes by anholt). Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-09 09:03:49 +00:00
return src;
dst_reg expanded = dst_reg(this, glsl_type::vec4_type);
expanded.type = src.type;
emit(MOV(expanded, src));
return src_reg(expanded);
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
void
vec4_visitor::emit_math(enum opcode opcode,
i965/vec4: Combine all the math emitters. 17 insertions(+), 102 deletions(-). Works just as well. v2: Make emit_math take const references (suggested by Matt), drop redundant WRITEMASK_XYZW setting (Matt and Curro). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-11-11 22:40:08 +00:00
const dst_reg &dst,
const src_reg &src0, const src_reg &src1)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
i965/vec4: Combine all the math emitters. 17 insertions(+), 102 deletions(-). Works just as well. v2: Make emit_math take const references (suggested by Matt), drop redundant WRITEMASK_XYZW setting (Matt and Curro). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-11-11 22:40:08 +00:00
vec4_instruction *math =
emit(opcode, dst, fix_math_operand(src0), fix_math_operand(src1));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vec4: Combine all the math emitters. 17 insertions(+), 102 deletions(-). Works just as well. v2: Make emit_math take const references (suggested by Matt), drop redundant WRITEMASK_XYZW setting (Matt and Curro). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-11-11 22:40:08 +00:00
if (brw->gen == 6 && dst.writemask != WRITEMASK_XYZW) {
/* MATH on Gen6 must be align1, so we can't do writemasks. */
math->dst = dst_reg(this, glsl_type::vec4_type);
math->dst.type = dst.type;
emit(MOV(dst, src_reg(math->dst)));
} else if (brw->gen < 6) {
math->base_mrf = 1;
math->mlen = src1.file == BAD_FILE ? 1 : 2;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
}
i965/vs/gen7: Emit code for GLSL ES 3.00 pack/unpack operations (v3) FIXME: This patch emits VS code that violates documented hardware restrictions and then relies on undocumented behavior that results from that violation. This patch passes all tests, but should be fixed ASAP to conform to the hardware documentation. v2: Explain undocumented hardware behavior. Improve comments. v3: Use ALU1 helper methods F32TO16() and F16TO32(). [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:44:31 +00:00
void
vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0)
{
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
if (brw->gen < 7) {
unreachable("ir_unop_pack_half_2x16 should be lowered");
}
i965/vs/gen7: Emit code for GLSL ES 3.00 pack/unpack operations (v3) FIXME: This patch emits VS code that violates documented hardware restrictions and then relies on undocumented behavior that results from that violation. This patch passes all tests, but should be fixed ASAP to conform to the hardware documentation. v2: Explain undocumented hardware behavior. Improve comments. v3: Use ALU1 helper methods F32TO16() and F16TO32(). [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:44:31 +00:00
assert(dst.type == BRW_REGISTER_TYPE_UD);
assert(src0.type == BRW_REGISTER_TYPE_F);
/* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
*
* Because this instruction does not have a 16-bit floating-point type,
* the destination data type must be Word (W).
*
* The destination must be DWord-aligned and specify a horizontal stride
* (HorzStride) of 2. The 16-bit result is stored in the lower word of
* each destination channel and the upper word is not modified.
*
* The above restriction implies that the f32to16 instruction must use
* align1 mode, because only in align1 mode is it possible to specify
* horizontal stride. We choose here to defy the hardware docs and emit
* align16 instructions.
*
* (I [chadv] did attempt to emit align1 instructions for VS f32to16
* instructions. I was partially successful in that the code passed all
* tests. However, the code was dubiously correct and fragile, and the
* tests were not harsh enough to probe that frailty. Not trusting the
* code, I chose instead to remain in align16 mode in defiance of the hw
* docs).
*
* I've [chadv] experimentally confirmed that, on gen7 hardware and the
* simulator, emitting a f32to16 in align16 mode with UD as destination
* data type is safe. The behavior differs from that specified in the PRM
* in that the upper word of each destination channel is cleared to 0.
*/
dst_reg tmp_dst(this, glsl_type::uvec2_type);
src_reg tmp_src(tmp_dst);
#if 0
/* Verify the undocumented behavior on which the following instructions
* rely. If f32to16 fails to clear the upper word of the X and Y channels,
* then the result of the bit-or instruction below will be incorrect.
*
* You should inspect the disasm output in order to verify that the MOV is
* not optimized away.
*/
emit(MOV(tmp_dst, src_reg(0x12345678u)));
#endif
/* Give tmp the form below, where "." means untouched.
*
* w z y x w z y x
* |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
*
* That the upper word of each write-channel be 0 is required for the
* following bit-shift and bit-or instructions to work. Note that this
* relies on the undocumented hardware behavior mentioned above.
*/
tmp_dst.writemask = WRITEMASK_XY;
emit(F32TO16(tmp_dst, src0));
/* Give the write-channels of dst the form:
* 0xhhhh0000
*/
i965/vec4: Fix confusion between SWIZZLE and BRW_SWIZZLE macros. Most of the VEC4 back-end agrees on src_reg::swizzle being one of the BRW_SWIZZLE macros defined in brw_reg.h, except in two places where we use Mesa's SWIZZLE macros. There is even a doxygen comment saying that Mesa's macros are the right ones. They are incompatible swizzle representations (3 bits vs. 2 bits per component), and the code using Mesa's works by pure luck. Fix it. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-28 06:21:45 +00:00
tmp_src.swizzle = BRW_SWIZZLE_YYYY;
i965/vs/gen7: Emit code for GLSL ES 3.00 pack/unpack operations (v3) FIXME: This patch emits VS code that violates documented hardware restrictions and then relies on undocumented behavior that results from that violation. This patch passes all tests, but should be fixed ASAP to conform to the hardware documentation. v2: Explain undocumented hardware behavior. Improve comments. v3: Use ALU1 helper methods F32TO16() and F16TO32(). [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:44:31 +00:00
emit(SHL(dst, tmp_src, src_reg(16u)));
/* Finally, give the write-channels of dst the form of packHalf2x16's
* output:
* 0xhhhhllll
*/
i965/vec4: Fix confusion between SWIZZLE and BRW_SWIZZLE macros. Most of the VEC4 back-end agrees on src_reg::swizzle being one of the BRW_SWIZZLE macros defined in brw_reg.h, except in two places where we use Mesa's SWIZZLE macros. There is even a doxygen comment saying that Mesa's macros are the right ones. They are incompatible swizzle representations (3 bits vs. 2 bits per component), and the code using Mesa's works by pure luck. Fix it. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-28 06:21:45 +00:00
tmp_src.swizzle = BRW_SWIZZLE_XXXX;
i965/vs/gen7: Emit code for GLSL ES 3.00 pack/unpack operations (v3) FIXME: This patch emits VS code that violates documented hardware restrictions and then relies on undocumented behavior that results from that violation. This patch passes all tests, but should be fixed ASAP to conform to the hardware documentation. v2: Explain undocumented hardware behavior. Improve comments. v3: Use ALU1 helper methods F32TO16() and F16TO32(). [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:44:31 +00:00
emit(OR(dst, src_reg(dst), tmp_src));
}
void
vec4_visitor::emit_unpack_half_2x16(dst_reg dst, src_reg src0)
{
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
if (brw->gen < 7) {
unreachable("ir_unop_unpack_half_2x16 should be lowered");
}
i965/vs/gen7: Emit code for GLSL ES 3.00 pack/unpack operations (v3) FIXME: This patch emits VS code that violates documented hardware restrictions and then relies on undocumented behavior that results from that violation. This patch passes all tests, but should be fixed ASAP to conform to the hardware documentation. v2: Explain undocumented hardware behavior. Improve comments. v3: Use ALU1 helper methods F32TO16() and F16TO32(). [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:44:31 +00:00
assert(dst.type == BRW_REGISTER_TYPE_F);
assert(src0.type == BRW_REGISTER_TYPE_UD);
/* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
*
* Because this instruction does not have a 16-bit floating-point type,
* the source data type must be Word (W). The destination type must be
* F (Float).
*
* To use W as the source data type, we must adjust horizontal strides,
* which is only possible in align1 mode. All my [chadv] attempts at
* emitting align1 instructions for unpackHalf2x16 failed to pass the
* Piglit tests, so I gave up.
*
* I've verified that, on gen7 hardware and the simulator, it is safe to
* emit f16to32 in align16 mode with UD as source data type.
*/
dst_reg tmp_dst(this, glsl_type::uvec2_type);
src_reg tmp_src(tmp_dst);
tmp_dst.writemask = WRITEMASK_X;
emit(AND(tmp_dst, src0, src_reg(0xffffu)));
tmp_dst.writemask = WRITEMASK_Y;
emit(SHR(tmp_dst, src0, src_reg(16u)));
dst.writemask = WRITEMASK_XY;
emit(F16TO32(dst, tmp_src));
}
i965/vec4: Optimize unpackUnorm4x8(). Reduces the number of instructions needed to implement unpackUnorm4x8() from 11 -> 4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-03-09 01:29:33 +00:00
void
vec4_visitor::emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0)
{
/* Instead of splitting the 32-bit integer, shifting, and ORing it back
* together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
* is not suitable to generate the shift values, but we can use the packed
* vector float and a type-converting MOV.
*/
dst_reg shift(this, glsl_type::uvec4_type);
emit(MOV(shift, src_reg(0x00, 0x60, 0x70, 0x78)));
dst_reg shifted(this, glsl_type::uvec4_type);
src0.swizzle = BRW_SWIZZLE_XXXX;
emit(SHR(shifted, src0, src_reg(shift)));
shifted.type = BRW_REGISTER_TYPE_UB;
dst_reg f(this, glsl_type::vec4_type);
emit(MOV(f, src_reg(shifted)));
emit(MUL(dst, src_reg(f), src_reg(1.0f / 255.0f)));
}
i965/vec4: Optimize unpackSnorm4x8(). Reduces the number of instructions needed to implement unpackSnorm4x8() from 16 -> 6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-03-10 03:22:23 +00:00
void
vec4_visitor::emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0)
{
/* Instead of splitting the 32-bit integer, shifting, and ORing it back
* together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
* is not suitable to generate the shift values, but we can use the packed
* vector float and a type-converting MOV.
*/
dst_reg shift(this, glsl_type::uvec4_type);
emit(MOV(shift, src_reg(0x00, 0x60, 0x70, 0x78)));
dst_reg shifted(this, glsl_type::uvec4_type);
src0.swizzle = BRW_SWIZZLE_XXXX;
emit(SHR(shifted, src0, src_reg(shift)));
shifted.type = BRW_REGISTER_TYPE_B;
dst_reg f(this, glsl_type::vec4_type);
emit(MOV(f, src_reg(shifted)));
dst_reg scaled(this, glsl_type::vec4_type);
emit(MUL(scaled, src_reg(f), src_reg(1.0f / 127.0f)));
dst_reg max(this, glsl_type::vec4_type);
emit_minmax(BRW_CONDITIONAL_G, max, src_reg(scaled), src_reg(-1.0f));
emit_minmax(BRW_CONDITIONAL_L, dst, src_reg(max), src_reg(1.0f));
}
i965/vec4: Optimize packUnorm4x8(). Reduces the number of instructions needed to implement packUnorm4x8() from 11 -> 6.
2014-03-10 20:27:46 +00:00
void
vec4_visitor::emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0)
{
dst_reg saturated(this, glsl_type::vec4_type);
vec4_instruction *inst = emit(MOV(saturated, src0));
inst->saturate = true;
dst_reg scaled(this, glsl_type::vec4_type);
emit(MUL(scaled, src_reg(saturated), src_reg(255.0f)));
dst_reg rounded(this, glsl_type::vec4_type);
emit(RNDE(rounded, src_reg(scaled)));
dst_reg u(this, glsl_type::uvec4_type);
emit(MOV(u, src_reg(rounded)));
src_reg bytes(u);
emit(VEC4_OPCODE_PACK_BYTES, dst, bytes);
}
i965/vec4: Optimize packSnorm4x8(). Reduces the number of instructions needed to implement packSnorm4x8() from 13 -> 7.
2014-03-10 21:11:05 +00:00
void
vec4_visitor::emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0)
{
dst_reg max(this, glsl_type::vec4_type);
emit_minmax(BRW_CONDITIONAL_G, max, src0, src_reg(-1.0f));
dst_reg min(this, glsl_type::vec4_type);
emit_minmax(BRW_CONDITIONAL_L, min, src_reg(max), src_reg(1.0f));
dst_reg scaled(this, glsl_type::vec4_type);
emit(MUL(scaled, src_reg(min), src_reg(127.0f)));
dst_reg rounded(this, glsl_type::vec4_type);
emit(RNDE(rounded, src_reg(scaled)));
dst_reg i(this, glsl_type::ivec4_type);
emit(MOV(i, src_reg(rounded)));
src_reg bytes(i);
emit(VEC4_OPCODE_PACK_BYTES, dst, bytes);
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
void
vec4_visitor::visit_instructions(const exec_list *list)
{
i965: Use typed foreach_in_list instead of foreach_list. Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-24 23:53:19 +01:00
foreach_in_list(ir_instruction, ir, list) {
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
base_ir = ir;
ir->accept(this);
}
}
static int
type_size(const struct glsl_type *type)
{
unsigned int i;
int size;
switch (type->base_type) {
case GLSL_TYPE_UINT:
case GLSL_TYPE_INT:
case GLSL_TYPE_FLOAT:
case GLSL_TYPE_BOOL:
if (type->is_matrix()) {
return type->matrix_columns;
} else {
/* Regardless of size of vector, it gets a vec4. This is bad
* packing for things like floats, but otherwise arrays become a
* mess. Hopefully a later pass over the code can pack scalars
* down if appropriate.
*/
return 1;
}
case GLSL_TYPE_ARRAY:
assert(type->length > 0);
return type_size(type->fields.array) * type->length;
case GLSL_TYPE_STRUCT:
size = 0;
for (i = 0; i < type->length; i++) {
size += type_size(type->fields.structure[i].type);
}
return size;
case GLSL_TYPE_SAMPLER:
i965/vec4: Make type_size() return 0 for samplers. The FS backend has always used 0, and the VS backend has always used 1. I think 1 is just working around other problems, and is incorrect. Samplers are baked in; nothing uses the UNIFORM register we would create, and we shouldn't upload any constant values for them. Fixes ES3-CTS.shaders.struct.uniform.sampler_array_vertex. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Tested-by: Ian Romanick <ian.d.romanick@intel.com>
2014-09-12 06:07:41 +01:00
/* Samplers take up no register space, since they're baked in at
* link time.
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
*/
i965/vec4: Make type_size() return 0 for samplers. The FS backend has always used 0, and the VS backend has always used 1. I think 1 is just working around other problems, and is incorrect. Samplers are baked in; nothing uses the UNIFORM register we would create, and we shouldn't upload any constant values for them. Fixes ES3-CTS.shaders.struct.uniform.sampler_array_vertex. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Tested-by: Ian Romanick <ian.d.romanick@intel.com>
2014-09-12 06:07:41 +01:00
return 0;
glsl: Add new atomic_uint built-in GLSL type. v2: Fix GLSL version in which the type became available. Add contains_atomic() convenience method. Split off atomic counter comparison error checking to a separate patch that will handle all opaque types. Include new ir_variable fields for atomic types. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-10-20 20:35:47 +01:00
case GLSL_TYPE_ATOMIC_UINT:
return 0;
glsl: Add image type to the GLSL IR. v2: Reuse the glsl_sampler_dim enum for images. Reuse the glsl_type::sampler_* fields instead of creating new ones specific to image types. Reuse the same constructor as for samplers adding a new 'base_type' argument. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-25 21:50:47 +00:00
case GLSL_TYPE_IMAGE:
glsl: Replace most default cases in switches on GLSL type This makes it easier to find switch-statements that need to be updated after a new GLSL_TYPE_* is added because the compiler will generate a warning. Switch-statements that only had a small number of cases (e.g., everything in ir_constant_expression.cpp) were not modified. I may regret that decision when we eventually add support for doubles. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Carl Worth <cworth@cworth.org> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-11 20:56:03 +00:00
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
glsl: Add GLSL_TYPE_INTERFACE Interfaces are structurally identical to structures from the compiler's point of view. They have some additional restrictions, and generally GPUs use different instructions to access them. Using a different base type should make this a bit easier. This commit also adds the glsl_type::interface_packing fields. For GLSL_TYPE_INTERFACE types, this will track the specified packing mode. It is analogous to gl_uniform_buffer::_Packing. v2: Add serveral missing GLSL_TYPE_INTERFACE cases in switch-statements. v3: Add information about glsl_type::interface_packing. Move row_major checking in glsl_type::record_key_compare from this patch to the previous patch. Both suggested by Paul Berry. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-11 20:11:16 +00:00
case GLSL_TYPE_INTERFACE:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
glsl: Replace most default cases in switches on GLSL type This makes it easier to find switch-statements that need to be updated after a new GLSL_TYPE_* is added because the compiler will generate a warning. Switch-statements that only had a small number of cases (e.g., everything in ir_constant_expression.cpp) were not modified. I may regret that decision when we eventually add support for doubles. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Carl Worth <cworth@cworth.org> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-11 20:56:03 +00:00
return 0;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type)
{
init();
this->file = GRF;
i965: Factor out virtual GRF allocation to a separate object. Right now virtual GRF book-keeping and allocation is performed in each visitor class separately (among other hundred different things), leading to duplicated logic in each visitor and preventing layering as it forces any code that manipulates i965 IR and needs to allocate virtual registers to depend on the specific visitor that happens to be used to translate from GLSL IR. v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor). Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-10 13:51:34 +00:00
this->reg = v->alloc.allocate(type_size(type));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
if (type->is_array() || type->is_record()) {
this->swizzle = BRW_SWIZZLE_NOOP;
} else {
this->swizzle = swizzle_for_size(type->vector_elements);
}
this->type = brw_type_for_base_type(type);
}
i965: Provide means to create registers of a given size. Implemented by Ilia Mirkin <imirkin@alum.mit.edu>. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-16 09:00:34 +01:00
src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type, int size)
{
assert(size > 0);
init();
this->file = GRF;
i965: Factor out virtual GRF allocation to a separate object. Right now virtual GRF book-keeping and allocation is performed in each visitor class separately (among other hundred different things), leading to duplicated logic in each visitor and preventing layering as it forces any code that manipulates i965 IR and needs to allocate virtual registers to depend on the specific visitor that happens to be used to translate from GLSL IR. v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor). Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-10 13:51:34 +00:00
this->reg = v->alloc.allocate(type_size(type) * size);
i965: Provide means to create registers of a given size. Implemented by Ilia Mirkin <imirkin@alum.mit.edu>. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-16 09:00:34 +01:00
this->swizzle = BRW_SWIZZLE_NOOP;
this->type = brw_type_for_base_type(type);
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type)
{
init();
this->file = GRF;
i965: Factor out virtual GRF allocation to a separate object. Right now virtual GRF book-keeping and allocation is performed in each visitor class separately (among other hundred different things), leading to duplicated logic in each visitor and preventing layering as it forces any code that manipulates i965 IR and needs to allocate virtual registers to depend on the specific visitor that happens to be used to translate from GLSL IR. v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor). Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-10 13:51:34 +00:00
this->reg = v->alloc.allocate(type_size(type));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
if (type->is_array() || type->is_record()) {
this->writemask = WRITEMASK_XYZW;
} else {
this->writemask = (1 << type->vector_elements) - 1;
}
this->type = brw_type_for_base_type(type);
}
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
/* Our support for uniforms is piggy-backed on the struct
* gl_fragment_program, because that's where the values actually
* get stored, rather than in some global gl_shader_program uniform
* store.
*/
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
void
vec4_visitor::setup_uniform_values(ir_variable *ir)
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
{
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
int namelen = strlen(ir->name);
i965: Use native integer uniforms when the new VS backend is in use. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-19 19:51:43 +01:00
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
/* The data for our (non-builtin) uniforms is stored in a series of
* gl_uniform_driver_storage structs for each subcomponent that
* glGetUniformLocation() could name. We know it's been set up in the same
* order we'd walk the type, so walk the list of storage and find anything
* with our name, or the prefix of a component that starts with our name.
*/
i965: Rename backend_visitor::prog to shader_prog. The next patch is going to change the type of vec4_visitor::vp from struct gl_vertex_program * to struct gl_program *, and rename it. The sensible name to change it to is vec4_visitor::prog. However, prog is already used in backend_visitor (which vec4_visitor derives from). Since backend_visitor::prog is of type struct gl_shader_program *, it makes sense to rename it to shader_prog. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-09 01:17:44 +01:00
for (unsigned u = 0; u < shader_prog->NumUserUniformStorage; u++) {
struct gl_uniform_storage *storage = &shader_prog->UniformStorage[u];
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
if (strncmp(ir->name, storage->name, namelen) != 0 ||
(storage->name[namelen] != 0 &&
storage->name[namelen] != '.' &&
storage->name[namelen] != '[')) {
continue;
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
}
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
gl_constant_value *components = storage->storage;
unsigned vector_count = (MAX2(storage->array_elements, 1) *
storage->type->matrix_columns);
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
for (unsigned s = 0; s < vector_count; s++) {
i965: Assert array index on access to vec4_visitor's arrays. v2: vec4_visitor::pack_uniform_registers(): Use correct comparison in the assert, this->uniforms is already adjusted. Compare the actual value used to index uniform_size and uniform_vector_size instead. Signed-off-by: Petri Latvala <petri.latvala@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-27 14:15:05 +00:00
assert(uniforms < uniform_array_size);
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
uniform_vector_size[uniforms] = storage->type->vector_elements;
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
int i;
for (i = 0; i < uniform_vector_size[uniforms]; i++) {
i965: Store uniform constant values in a gl_constant_value instead of float The brw_stage_prog_data struct previously contained an array of float pointers to the values of parameters. These were then copied into a batch buffer to upload the values using a regular assignment. However the float values were also being overloaded to store integer values for integer uniforms. This can break if x87 floating-point registers are used to do the assignment because the fst instruction tries to fix up invalid float values. If an integer constant happened to look like an invalid float value then it would get altered when it was copied into the batch buffer. This patch changes the pointers to be gl_constant_value instead so that the assignment should end up copying without any alteration. This also makes it more obvious that the values being stored here are overloaded for multiple types. There are some static asserts where the values are uploaded to ensure that the size of gl_constant_value is the same as a float. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81150 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-11 12:21:44 +01:00
stage_prog_data->param[uniforms * 4 + i] = components;
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
components++;
}
for (; i < 4; i++) {
i965: fix compiler error in union initiliazer gcc 4.6.3 chokes with the following error: brw_vec4.cpp: In member function 'int brw::vec4_visitor::setup_uniforms(int)': brw_vec4.cpp:1496:37: error: expected primary-expression before '.' token Apparently C++ does not do named initializers for unions, except maybe as a gcc extension, which is not present here. As .f is the first element of the union, just drop it. Fixes the build error. Signed-off-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 19:17:04 +01:00
static gl_constant_value zero = { 0.0 };
i965: Move up duplicated fields from stage-specific prog_data to brw_stage_prog_data. There doesn't seem to be any reason for nr_params, nr_pull_params, param, and pull_param to be duplicated in the stage-specific subclasses of brw_stage_prog_data. Moving their definition to the common base class will allow some code sharing in a future commit, the removal of brw_vec4_prog_data_compare and brw_*_prog_data_free, and the simplification of the stage-specific brw_*_prog_data_compare. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 14:14:02 +00:00
stage_prog_data->param[uniforms * 4 + i] = &zero;
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
}
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
uniforms++;
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
}
}
}
i965 new VS: don't share clip plane constants in pre-GEN6 In pre-GEN6, when using clip planes, both the vertex shader and the clipper need access to the client-supplied clip planes, since the vertex shader needs them to set the clip flags, and the clipper needs them to determine where to insert new vertices. With the old VS backend, we used a clever optimization to avoid placing duplicate copies of these planes in the CURBE: we used the same block of memory for both the clipper and vertex shader constants, with the clip planes at the front of it, and then we instructed the clipper to read just the initial part of this block containing the clip planes. This optimization was tricky, of dubious value, and not completely working in the new VS backend, so I've removed it. Now, when using the new VS backend, separate parts of the CURBE are used for the clipper and the vertex shader. Note that this doesn't affect the number of push constants available to the vertex shader, it simply causes the CURBE to occupy a few more bytes of URB memory. The old VS backend is unaffected. GEN6+, which does clipping entirely in hardware, is also unaffected. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-09-24 05:33:50 +01:00
void
vec4_visitor::setup_uniform_clipplane_values()
{
i965 Gen6: Implement gl_ClipVertex. This patch implements proper support for gl_ClipVertex by causing the new VS backend to populate the clip distance VUE slots using VERT_RESULT_CLIP_VERTEX when appropriate, and by using the untransformed clip planes in ctx->Transform.EyeUserPlane rather than the transformed clip planes in ctx->Transform._ClipUserPlane when a GLSL-based vertex shader is in use. When not using a GLSL-based vertex shader, we use ctx->Transform._ClipUserPlane (which is what we used prior to this patch). This ensures that clipping is still performed correctly for fixed function and ARB vertex programs. A new function, brw_select_clip_planes() is used to determine whether to use _ClipUserPlane or EyeUserPlane, so that the logic for making this decision is shared between the new and old vertex shaders. Fixes the following Piglit tests on i965 Gen6: - vs-clip-vertex-const-accept - vs-clip-vertex-const-reject - vs-clip-vertex-different-from-position - vs-clip-vertex-equal-to-position - vs-clip-vertex-homogeneity - vs-clip-based-on-position - vs-clip-based-on-position-homogeneity - clip-plane-transformation clipvert_pos - clip-plane-transformation pos_clipvert - clip-plane-transformation pos Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chad Versace <chad@chad-versace.us>
2011-09-26 21:43:04 +01:00
gl_clip_plane *clip_planes = brw_select_clip_planes(ctx);
i965: get rid of clip plane compaction Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-07-07 16:46:55 +01:00
for (int i = 0; i < key->nr_userclip_plane_consts; ++i) {
i965: Assert array index on access to vec4_visitor's arrays. v2: vec4_visitor::pack_uniform_registers(): Use correct comparison in the assert, this->uniforms is already adjusted. Compare the actual value used to index uniform_size and uniform_vector_size instead. Signed-off-by: Petri Latvala <petri.latvala@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-27 14:15:05 +00:00
assert(this->uniforms < uniform_array_size);
i965: get rid of clip plane compaction Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-07-07 16:46:55 +01:00
this->uniform_vector_size[this->uniforms] = 4;
this->userplane[i] = dst_reg(UNIFORM, this->uniforms);
this->userplane[i].type = BRW_REGISTER_TYPE_F;
for (int j = 0; j < 4; ++j) {
i965: Store uniform constant values in a gl_constant_value instead of float The brw_stage_prog_data struct previously contained an array of float pointers to the values of parameters. These were then copied into a batch buffer to upload the values using a regular assignment. However the float values were also being overloaded to store integer values for integer uniforms. This can break if x87 floating-point registers are used to do the assignment because the fst instruction tries to fix up invalid float values. If an integer constant happened to look like an invalid float value then it would get altered when it was copied into the batch buffer. This patch changes the pointers to be gl_constant_value instead so that the assignment should end up copying without any alteration. This also makes it more obvious that the values being stored here are overloaded for multiple types. There are some static asserts where the values are uploaded to ensure that the size of gl_constant_value is the same as a float. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81150 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-11 12:21:44 +01:00
stage_prog_data->param[this->uniforms * 4 + j] =
(gl_constant_value *) &clip_planes[i][j];
i965 new VS: don't share clip plane constants in pre-GEN6 In pre-GEN6, when using clip planes, both the vertex shader and the clipper need access to the client-supplied clip planes, since the vertex shader needs them to set the clip flags, and the clipper needs them to determine where to insert new vertices. With the old VS backend, we used a clever optimization to avoid placing duplicate copies of these planes in the CURBE: we used the same block of memory for both the clipper and vertex shader constants, with the clip planes at the front of it, and then we instructed the clipper to read just the initial part of this block containing the clip planes. This optimization was tricky, of dubious value, and not completely working in the new VS backend, so I've removed it. Now, when using the new VS backend, separate parts of the CURBE are used for the clipper and the vertex shader. Note that this doesn't affect the number of push constants available to the vertex shader, it simply causes the CURBE to occupy a few more bytes of URB memory. The old VS backend is unaffected. GEN6+, which does clipping entirely in hardware, is also unaffected. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-09-24 05:33:50 +01:00
}
i965: get rid of clip plane compaction Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-07-07 16:46:55 +01:00
++this->uniforms;
i965 new VS: don't share clip plane constants in pre-GEN6 In pre-GEN6, when using clip planes, both the vertex shader and the clipper need access to the client-supplied clip planes, since the vertex shader needs them to set the clip flags, and the clipper needs them to determine where to insert new vertices. With the old VS backend, we used a clever optimization to avoid placing duplicate copies of these planes in the CURBE: we used the same block of memory for both the clipper and vertex shader constants, with the clip planes at the front of it, and then we instructed the clipper to read just the initial part of this block containing the clip planes. This optimization was tricky, of dubious value, and not completely working in the new VS backend, so I've removed it. Now, when using the new VS backend, separate parts of the CURBE are used for the clipper and the vertex shader. Note that this doesn't affect the number of push constants available to the vertex shader, it simply causes the CURBE to occupy a few more bytes of URB memory. The old VS backend is unaffected. GEN6+, which does clipping entirely in hardware, is also unaffected. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-09-24 05:33:50 +01:00
}
}
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
/* Our support for builtin uniforms is even scarier than non-builtin.
* It sits on top of the PROG_STATE_VAR parameters that are
* automatically updated from GL context state.
*/
void
vec4_visitor::setup_builtin_uniform_values(ir_variable *ir)
{
glsl: Make ir_variable::num_state_slots and ir_variable::state_slots private Also move num_state_slots inside ir_variable_data for better packing. The payoff for this will come in a few more patches. No change Valgrind massif results for a trimmed apitrace of dota2. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-05-15 03:47:28 +01:00
const ir_state_slot *const slots = ir->get_state_slots();
assert(slots != NULL);
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
glsl: Make ir_variable::num_state_slots and ir_variable::state_slots private Also move num_state_slots inside ir_variable_data for better packing. The payoff for this will come in a few more patches. No change Valgrind massif results for a trimmed apitrace of dota2. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-05-15 03:47:28 +01:00
for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
/* This state reference has already been setup by ir_to_mesa,
* but we'll get the same index back here. We can reference
* ParameterValues directly, since unlike brw_fs.cpp, we never
* add new state references during compile.
*/
i965/vs: Make type of vec4_visitor::vp more generic. The vec4_visitor functions don't use any VS specific data from vec4_visitor::vp. So rename it to "prog" and change its type from struct gl_vertex_program * to struct gl_program *. This will allow the code to be re-used for geometry shaders. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> v2: Use the name "prog" rather than "p". Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-16 04:19:23 +00:00
int index = _mesa_add_state_reference(this->prog->Parameters,
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
(gl_state_index *)slots[i].tokens);
i965: Store uniform constant values in a gl_constant_value instead of float The brw_stage_prog_data struct previously contained an array of float pointers to the values of parameters. These were then copied into a batch buffer to upload the values using a regular assignment. However the float values were also being overloaded to store integer values for integer uniforms. This can break if x87 floating-point registers are used to do the assignment because the fst instruction tries to fix up invalid float values. If an integer constant happened to look like an invalid float value then it would get altered when it was copied into the batch buffer. This patch changes the pointers to be gl_constant_value instead so that the assignment should end up copying without any alteration. This also makes it more obvious that the values being stored here are overloaded for multiple types. There are some static asserts where the values are uploaded to ensure that the size of gl_constant_value is the same as a float. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81150 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-11 12:21:44 +01:00
gl_constant_value *values =
&this->prog->Parameters->ParameterValues[index][0];
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
i965: Assert array index on access to vec4_visitor's arrays. v2: vec4_visitor::pack_uniform_registers(): Use correct comparison in the assert, this->uniforms is already adjusted. Compare the actual value used to index uniform_size and uniform_vector_size instead. Signed-off-by: Petri Latvala <petri.latvala@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-27 14:15:05 +00:00
assert(this->uniforms < uniform_array_size);
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
this->uniform_vector_size[this->uniforms] = 0;
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
/* Add each of the unique swizzled channels of the element.
* This will end up matching the size of the glsl_type of this field.
*/
int last_swiz = -1;
for (unsigned int j = 0; j < 4; j++) {
int swiz = GET_SWZ(slots[i].swizzle, j);
last_swiz = swiz;
i965: Move up duplicated fields from stage-specific prog_data to brw_stage_prog_data. There doesn't seem to be any reason for nr_params, nr_pull_params, param, and pull_param to be duplicated in the stage-specific subclasses of brw_stage_prog_data. Moving their definition to the common base class will allow some code sharing in a future commit, the removal of brw_vec4_prog_data_compare and brw_*_prog_data_free, and the simplification of the stage-specific brw_*_prog_data_compare. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 14:14:02 +00:00
stage_prog_data->param[this->uniforms * 4 + j] = &values[swiz];
i965: Assert array index on access to vec4_visitor's arrays. v2: vec4_visitor::pack_uniform_registers(): Use correct comparison in the assert, this->uniforms is already adjusted. Compare the actual value used to index uniform_size and uniform_vector_size instead. Signed-off-by: Petri Latvala <petri.latvala@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-27 14:15:05 +00:00
assert(this->uniforms < uniform_array_size);
i965/vs: Fix builtin uniform setup. I want to intelligently pack them at some point, but for now we have the params set up in groups of 4. Fixes glsl-vs-normalscale.
2011-08-09 22:49:29 +01:00
if (swiz <= last_swiz)
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
this->uniform_vector_size[this->uniforms]++;
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
}
this->uniforms++;
}
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
dst_reg *
vec4_visitor::variable_storage(ir_variable *var)
{
return (dst_reg *)hash_table_find(this->variable_ht, var);
}
void
i965: Make a brw_predicate enum. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-06-30 01:58:59 +01:00
vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
enum brw_predicate *predicate)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
ir_expression *expr = ir->as_expression();
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
*predicate = BRW_PREDICATE_NORMAL;
i965: Handle ir_binop_ubo_load in boolean expression code. UBO loads can be boolean-valued expressions, too, so we need to handle them in emit_bool_to_cond_code() and emit_if_gen6(). However, unlike most expressions, it doesn't make sense to evaluate their operands, then do something with the results. We just want to evaluate the UBO load as a whole---which performs the read from memory---then load the boolean result into the flag register. Instead of adding code to handle it, we can simply bypass the ir_expression handling, and fall through to the default code, which will do exactly that. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83468 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: mesa-stable@lists.freedesktop.org
2014-09-04 08:18:45 +01:00
if (expr && expr->operation != ir_binop_ubo_load) {
i965: Handle ir_triop_csel in emit_bool_to_cond_code(). ir_triop_csel can return a boolean expression, so we need to handle it here; we simply forgot when we added it. Fixes Piglit's EXT_shader_integer_mix/{vs,fs}-mix-if-bool. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: mesa-stable@lists.freedesktop.org
2014-08-22 20:19:49 +01:00
src_reg op[3];
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
vec4_instruction *inst;
i965: Handle ir_triop_csel in emit_bool_to_cond_code(). ir_triop_csel can return a boolean expression, so we need to handle it here; we simply forgot when we added it. Fixes Piglit's EXT_shader_integer_mix/{vs,fs}-mix-if-bool. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: mesa-stable@lists.freedesktop.org
2014-08-22 20:19:49 +01:00
assert(expr->get_num_operands() <= 3);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
expr->operands[i]->accept(this);
op[i] = this->result;
i965/vs: Fix comparisons with uint negation. The condmod instruction ends up generating garbage condition codes, because apparently the comparison happens on the accumulator value (33 bits for UD), not the truncated value that would be written. Fixes vs-op-neg-* Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-10-03 23:31:52 +01:00
resolve_ud_negate(&op[i]);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
switch (expr->operation) {
case ir_unop_logic_not:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
inst = emit(AND(dst_null_d(), op[0], src_reg(1)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
inst->conditional_mod = BRW_CONDITIONAL_Z;
break;
case ir_binop_logic_xor:
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
if (brw->gen <= 5) {
src_reg temp = src_reg(this, ir->type);
emit(XOR(dst_reg(temp), op[0], op[1]));
inst = emit(AND(dst_null_d(), temp, src_reg(1)));
} else {
inst = emit(XOR(dst_null_d(), op[0], op[1]));
}
inst->conditional_mod = BRW_CONDITIONAL_NZ;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_logic_or:
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
if (brw->gen <= 5) {
src_reg temp = src_reg(this, ir->type);
emit(OR(dst_reg(temp), op[0], op[1]));
inst = emit(AND(dst_null_d(), temp, src_reg(1)));
} else {
inst = emit(OR(dst_null_d(), op[0], op[1]));
}
inst->conditional_mod = BRW_CONDITIONAL_NZ;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_logic_and:
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
if (brw->gen <= 5) {
src_reg temp = src_reg(this, ir->type);
emit(AND(dst_reg(temp), op[0], op[1]));
inst = emit(AND(dst_null_d(), temp, src_reg(1)));
} else {
inst = emit(AND(dst_null_d(), op[0], op[1]));
}
inst->conditional_mod = BRW_CONDITIONAL_NZ;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_unop_f2b:
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 6) {
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(CMP(dst_null_d(), op[0], src_reg(0.0f), BRW_CONDITIONAL_NZ));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
} else {
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
inst = emit(MOV(dst_null_f(), op[0]));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
break;
case ir_unop_i2b:
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 6) {
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
} else {
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
inst = emit(MOV(dst_null_d(), op[0]));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
break;
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
case ir_binop_all_equal:
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
if (brw->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
inst = emit(CMP(dst_null_d(), op[0], op[1], BRW_CONDITIONAL_Z));
*predicate = BRW_PREDICATE_ALIGN16_ALL4H;
break;
case ir_binop_any_nequal:
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
if (brw->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
inst = emit(CMP(dst_null_d(), op[0], op[1], BRW_CONDITIONAL_NZ));
*predicate = BRW_PREDICATE_ALIGN16_ANY4H;
break;
case ir_unop_any:
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
if (brw->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
}
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
inst = emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
*predicate = BRW_PREDICATE_ALIGN16_ANY4H;
break;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_binop_greater:
case ir_binop_gequal:
case ir_binop_less:
case ir_binop_lequal:
case ir_binop_equal:
case ir_binop_nequal:
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
if (brw->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
i965/vs: Move logic for weird CMP type handling to CMP generators. v2: Don't bother with the no-dst-reg version of CMP() Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:59:43 +01:00
emit(CMP(dst_null_d(), op[0], op[1],
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
brw_conditional_for_comparison(expr->operation)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
i965: Handle ir_triop_csel in emit_bool_to_cond_code(). ir_triop_csel can return a boolean expression, so we need to handle it here; we simply forgot when we added it. Fixes Piglit's EXT_shader_integer_mix/{vs,fs}-mix-if-bool. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: mesa-stable@lists.freedesktop.org
2014-08-22 20:19:49 +01:00
case ir_triop_csel: {
/* Expand the boolean condition into the flag register. */
inst = emit(MOV(dst_null_d(), op[0]));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
/* Select which boolean to return. */
dst_reg temp(this, expr->operands[1]->type);
inst = emit(BRW_OPCODE_SEL, temp, op[1], op[2]);
inst->predicate = BRW_PREDICATE_NORMAL;
/* Expand the result to a condition code. */
inst = emit(MOV(dst_null_d(), src_reg(temp)));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
break;
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
default:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
return;
}
ir->accept(this);
i965/vs: Fix comparisons with uint negation. The condmod instruction ends up generating garbage condition codes, because apparently the comparison happens on the accumulator value (33 bits for UD), not the truncated value that would be written. Fixes vs-op-neg-* Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-10-03 23:31:52 +01:00
resolve_ud_negate(&this->result);
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
vec4_instruction *inst = emit(AND(dst_null_d(), this->result, src_reg(1)));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
/**
* Emit a gen6 IF statement with the comparison folded into the IF
* instruction.
*/
void
vec4_visitor::emit_if_gen6(ir_if *ir)
{
ir_expression *expr = ir->condition->as_expression();
i965: Handle ir_binop_ubo_load in boolean expression code. UBO loads can be boolean-valued expressions, too, so we need to handle them in emit_bool_to_cond_code() and emit_if_gen6(). However, unlike most expressions, it doesn't make sense to evaluate their operands, then do something with the results. We just want to evaluate the UBO load as a whole---which performs the read from memory---then load the boolean result into the flag register. Instead of adding code to handle it, we can simply bypass the ir_expression handling, and fall through to the default code, which will do exactly that. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83468 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: mesa-stable@lists.freedesktop.org
2014-09-04 08:18:45 +01:00
if (expr && expr->operation != ir_binop_ubo_load) {
i965: Handle ir_triop_csel in emit_if_gen6(). ir_triop_csel can return a boolean expression, so we need to handle it here; we simply forgot when we added ir_triop_csel, and forgot again when adding it to emit_bool_to_cond_code. Fixes Piglit's EXT_shader_integer_mix/{vs,fs}-mix-if-bool on Sandybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: mesa-stable@lists.freedesktop.org
2014-09-04 08:18:43 +01:00
src_reg op[3];
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
dst_reg temp;
i965: Handle ir_triop_csel in emit_if_gen6(). ir_triop_csel can return a boolean expression, so we need to handle it here; we simply forgot when we added ir_triop_csel, and forgot again when adding it to emit_bool_to_cond_code. Fixes Piglit's EXT_shader_integer_mix/{vs,fs}-mix-if-bool on Sandybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: mesa-stable@lists.freedesktop.org
2014-09-04 08:18:43 +01:00
assert(expr->get_num_operands() <= 3);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
expr->operands[i]->accept(this);
op[i] = this->result;
}
switch (expr->operation) {
case ir_unop_logic_not:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(IF(op[0], src_reg(0), BRW_CONDITIONAL_Z));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
return;
case ir_binop_logic_xor:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(IF(op[0], op[1], BRW_CONDITIONAL_NZ));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
return;
case ir_binop_logic_or:
temp = dst_reg(this, glsl_type::bool_type);
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(OR(temp, op[0], op[1]));
emit(IF(src_reg(temp), src_reg(0), BRW_CONDITIONAL_NZ));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
return;
case ir_binop_logic_and:
temp = dst_reg(this, glsl_type::bool_type);
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(AND(temp, op[0], op[1]));
emit(IF(src_reg(temp), src_reg(0), BRW_CONDITIONAL_NZ));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
return;
case ir_unop_f2b:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(IF(op[0], src_reg(0), BRW_CONDITIONAL_NZ));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
return;
case ir_unop_i2b:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(IF(op[0], src_reg(0), BRW_CONDITIONAL_NZ));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
return;
case ir_binop_greater:
case ir_binop_gequal:
case ir_binop_less:
case ir_binop_lequal:
case ir_binop_equal:
case ir_binop_nequal:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(IF(op[0], op[1],
brw_conditional_for_comparison(expr->operation)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
return;
i965/vs: Add support for if(any_nequal()) and if(all_equal()) on gen6. Fixes vs-temp-array-mat2-col-rd.shader_test.
2011-08-06 04:03:31 +01:00
case ir_binop_all_equal:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(CMP(dst_null_d(), op[0], op[1], BRW_CONDITIONAL_Z));
emit(IF(BRW_PREDICATE_ALIGN16_ALL4H));
i965/vs: Add support for if(any_nequal()) and if(all_equal()) on gen6. Fixes vs-temp-array-mat2-col-rd.shader_test.
2011-08-06 04:03:31 +01:00
return;
case ir_binop_any_nequal:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(CMP(dst_null_d(), op[0], op[1], BRW_CONDITIONAL_NZ));
emit(IF(BRW_PREDICATE_ALIGN16_ANY4H));
i965/vs: Add support for if(any(bvec)) on gen6.
2011-08-10 22:13:23 +01:00
return;
case ir_unop_any:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
emit(IF(BRW_PREDICATE_ALIGN16_ANY4H));
i965/vs: Add support for if(any_nequal()) and if(all_equal()) on gen6. Fixes vs-temp-array-mat2-col-rd.shader_test.
2011-08-06 04:03:31 +01:00
return;
i965: Handle ir_triop_csel in emit_if_gen6(). ir_triop_csel can return a boolean expression, so we need to handle it here; we simply forgot when we added ir_triop_csel, and forgot again when adding it to emit_bool_to_cond_code. Fixes Piglit's EXT_shader_integer_mix/{vs,fs}-mix-if-bool on Sandybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: mesa-stable@lists.freedesktop.org
2014-09-04 08:18:43 +01:00
case ir_triop_csel: {
/* Expand the boolean condition into the flag register. */
vec4_instruction *inst = emit(MOV(dst_null_d(), op[0]));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
/* Select which boolean to return. */
dst_reg temp(this, expr->operands[1]->type);
inst = emit(BRW_OPCODE_SEL, temp, op[1], op[2]);
inst->predicate = BRW_PREDICATE_NORMAL;
emit(IF(src_reg(temp), src_reg(0), BRW_CONDITIONAL_NZ));
return;
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
default:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
return;
}
ir->condition->accept(this);
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(IF(this->result, src_reg(0), BRW_CONDITIONAL_NZ));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
void
vec4_visitor::visit(ir_variable *ir)
{
dst_reg *reg = NULL;
if (variable_storage(ir))
return;
glsl: move variables in to ir_variable::data, part I This patch moves following bitfields in to the data structure: used, assigned, how_declared, mode, interpolation, origin_upper_left, pixel_center_integer Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-12 11:51:01 +00:00
switch (ir->data.mode) {
glsl: Eliminate ambiguity between function ins/outs and shader ins/outs This patch replaces the three ir_variable_mode enums: - ir_var_in - ir_var_out - ir_var_inout with the following five: - ir_var_shader_in - ir_var_shader_out - ir_var_function_in - ir_var_function_out - ir_var_function_inout This eliminates a frustrating ambiguity: it used to be impossible to tell whether an ir_var_{in,out} variable was a shader in/out or a function in/out without seeing where the variable was declared in the IR. This complicated some optimization and lowering passes, and would have become a problem for implementing varying structs. In the lisp-style serialization of GLSL IR to strings performed by ir_print_visitor.cpp and ir_reader.cpp, I've retained the names "in", "out", and "inout" for function parameters, to avoid introducing code churn to the src/glsl/builtins/ir/ directory. Note: a couple of comments in the code seemed to indicate that we were planning for a possible future in which geometry shaders could have shader-scope inout variables. Our GLSL grammar rejects shader-scope inout variables, and I've been unable to find any evidence in the GLSL standards documents (or extensions) that this will ever be allowed, so I've eliminated these comments. Reviewed-by: Carl Worth <cworth@cworth.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-01-11 22:39:32 +00:00
case ir_var_shader_in:
i965: Add var->location != -1 assertions. We shouldn't receive variables with invalid locations set - adding these assertions should help catch problems before they cause crashes later. Inspired by similar code in st_glsl_to_tgsi. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-12-01 21:44:04 +00:00
assert(ir->data.location != -1);
glsl: move variables in to ir_variable::data, part II This patch moves following bitfields and variables to the data structure: explicit_location, explicit_index, explicit_binding, has_initializer, is_unmatched_generic_inout, location_frac, from_named_ifc_block_nonarray, from_named_ifc_block_array, depth_layout, location, index, binding, max_array_access, atomic Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-12 13:08:59 +00:00
reg = new(mem_ctx) dst_reg(ATTR, ir->data.location);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
glsl: Eliminate ambiguity between function ins/outs and shader ins/outs This patch replaces the three ir_variable_mode enums: - ir_var_in - ir_var_out - ir_var_inout with the following five: - ir_var_shader_in - ir_var_shader_out - ir_var_function_in - ir_var_function_out - ir_var_function_inout This eliminates a frustrating ambiguity: it used to be impossible to tell whether an ir_var_{in,out} variable was a shader in/out or a function in/out without seeing where the variable was declared in the IR. This complicated some optimization and lowering passes, and would have become a problem for implementing varying structs. In the lisp-style serialization of GLSL IR to strings performed by ir_print_visitor.cpp and ir_reader.cpp, I've retained the names "in", "out", and "inout" for function parameters, to avoid introducing code churn to the src/glsl/builtins/ir/ directory. Note: a couple of comments in the code seemed to indicate that we were planning for a possible future in which geometry shaders could have shader-scope inout variables. Our GLSL grammar rejects shader-scope inout variables, and I've been unable to find any evidence in the GLSL standards documents (or extensions) that this will ever be allowed, so I've eliminated these comments. Reviewed-by: Carl Worth <cworth@cworth.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-01-11 22:39:32 +00:00
case ir_var_shader_out:
i965: Add var->location != -1 assertions. We shouldn't receive variables with invalid locations set - adding these assertions should help catch problems before they cause crashes later. Inspired by similar code in st_glsl_to_tgsi. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-12-01 21:44:04 +00:00
assert(ir->data.location != -1);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
reg = new(mem_ctx) dst_reg(this, ir->type);
for (int i = 0; i < type_size(ir->type); i++) {
glsl: move variables in to ir_variable::data, part II This patch moves following bitfields and variables to the data structure: explicit_location, explicit_index, explicit_binding, has_initializer, is_unmatched_generic_inout, location_frac, from_named_ifc_block_nonarray, from_named_ifc_block_array, depth_layout, location, index, binding, max_array_access, atomic Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-12 13:08:59 +00:00
output_reg[ir->data.location + i] = *reg;
output_reg[ir->data.location + i].reg_offset = i;
output_reg[ir->data.location + i].type =
i965: Fix flat integral varyings. Previously, the vertex and fragment shader back-ends assumed that all varyings were floats. In GLSL 1.30 this is no longer true--they can also be of integral types provided that they have an interpolation qualifier of "flat". This required two changes in each back-end: assigning the correct type to the register that holds the varying value during shader execution, and assigning the correct type to the register that ties the varying value to the rest of the graphics pipeline (the message register in the case of VS, and the payload register in the case of FS). Fixes piglit tests fs-int-interpolation and fs-uint-interpolation. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-25 01:46:26 +01:00
brw_type_for_base_type(ir->type->get_scalar_type());
glsl: move variables in to ir_variable::data, part II This patch moves following bitfields and variables to the data structure: explicit_location, explicit_index, explicit_binding, has_initializer, is_unmatched_generic_inout, location_frac, from_named_ifc_block_nonarray, from_named_ifc_block_array, depth_layout, location, index, binding, max_array_access, atomic Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-12 13:08:59 +00:00
output_reg_annotation[ir->data.location + i] = ir->name;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
break;
i965/vs: Allocate storage for "auto" variables just like temps. Fixes segfault in glsl-vs-cross-2.
2011-08-06 00:35:24 +01:00
case ir_var_auto:
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_var_temporary:
reg = new(mem_ctx) dst_reg(this, ir->type);
break;
case ir_var_uniform:
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
reg = new(this->mem_ctx) dst_reg(UNIFORM, this->uniforms);
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
/* Thanks to the lower_ubo_reference pass, we will see only
* ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
* variables, so no need for them to be in variable_ht.
i965/gen7: Handle atomic instructions from the VEC4 back-end. This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. v2: Represent atomics as GLSL intrinsics. Add support for variably indexed atomic counter arrays. v3: Add comment on why we don't need to assign uniform storage for atomic counters. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-26 00:31:35 +01:00
*
i965: Skip allocating UNIFORM file storage for uniforms of size 0. Samplers take up zero slots and therefore don't exist in the params array, nor are they included in stage_prog_data->nr_params. There's no need to store their size in param_size, as it's only used for dealing with arrays of "real" uniforms (ones uploaded as shader constants). We run into all kinds of problems trying to refer to the uniform storage for variables that don't have uniform storage. For one, we may use some other variable's index, or access out of bounds in arrays. In the FS backend, our extra 2 * MaxSamplerImageUnits params for texture rectangle rescaling paper over a lot of problems. In the VS backend, we claim samplers take up a slot, which also papers over problems. Instead, just skip allocating storage for variables that don't have any. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Tested-by: Ian Romanick <ian.d.romanick@intel.com>
2014-09-12 06:07:40 +01:00
* Some uniforms, such as samplers and atomic counters, have no actual
* storage, so we should ignore them.
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
*/
i965: Skip allocating UNIFORM file storage for uniforms of size 0. Samplers take up zero slots and therefore don't exist in the params array, nor are they included in stage_prog_data->nr_params. There's no need to store their size in param_size, as it's only used for dealing with arrays of "real" uniforms (ones uploaded as shader constants). We run into all kinds of problems trying to refer to the uniform storage for variables that don't have uniform storage. For one, we may use some other variable's index, or access out of bounds in arrays. In the FS backend, our extra 2 * MaxSamplerImageUnits params for texture rectangle rescaling paper over a lot of problems. In the VS backend, we claim samplers take up a slot, which also papers over problems. Instead, just skip allocating storage for variables that don't have any. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Tested-by: Ian Romanick <ian.d.romanick@intel.com>
2014-09-12 06:07:40 +01:00
if (ir->is_in_uniform_block() || type_size(ir->type) == 0)
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
return;
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
/* Track how big the whole uniform variable is, in case we need to put a
* copy of its data into pull constants for array access.
*/
i965: Assert array index on access to vec4_visitor's arrays. v2: vec4_visitor::pack_uniform_registers(): Use correct comparison in the assert, this->uniforms is already adjusted. Compare the actual value used to index uniform_size and uniform_vector_size instead. Signed-off-by: Petri Latvala <petri.latvala@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-27 14:15:05 +00:00
assert(this->uniforms < uniform_array_size);
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
this->uniform_size[this->uniforms] = type_size(ir->type);
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
if (!strncmp(ir->name, "gl_", 3)) {
setup_builtin_uniform_values(ir);
} else {
i965/vs: Reference the core GL uniform storage for non-builtin uniforms. Like in the FS, there's no reason to use an external copy if the ParameterValues[] relayout of it isn't the layout we need. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-21 03:18:45 +00:00
setup_uniform_values(ir);
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
i965/vs: Allocate storage for "auto" variables just like temps. Fixes segfault in glsl-vs-cross-2.
2011-08-06 00:35:24 +01:00
i965: Add support for gl_VertexID and gl_InstanceID. The compiler setup for these VF-uploaded attributes looks a little cheesy with mixing system values and real VBO-sourced attributes. It would be nice if we could just compute the ATTR[] map to GRF index up front and use it at visit time instead of using ir->location in the ATTR file. However, we don't know the reg_offset at visit(ir_variable *) time, so we can't do the mapping that early. Fixes piglit vertexid test. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-11-09 02:50:09 +00:00
case ir_var_system_value:
i965/vs: Add virtual function make_reg_for_system_value(). The system values handled by vec4_visitor::visit(ir_variable *) are VS-specific (vertex ID and instance ID). This patch moves the handling of those values into a new virtual function, make_reg_for_system_value(), so that this VS-specific code won't be inherited by geomtry shaders. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-17 16:05:52 +00:00
reg = make_reg_for_system_value(ir);
i965: Add support for gl_VertexID and gl_InstanceID. The compiler setup for these VF-uploaded attributes looks a little cheesy with mixing system values and real VBO-sourced attributes. It would be nice if we could just compute the ATTR[] map to GRF index up front and use it at visit time instead of using ir->location in the ATTR file. However, we don't know the reg_offset at visit(ir_variable *) time, so we can't do the mapping that early. Fixes piglit vertexid test. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-11-09 02:50:09 +00:00
break;
i965/vs: Allocate storage for "auto" variables just like temps. Fixes segfault in glsl-vs-cross-2.
2011-08-06 00:35:24 +01:00
default:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
reg->type = brw_type_for_base_type(ir->type);
hash_table_insert(this->variable_ht, reg, ir);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
void
vec4_visitor::visit(ir_loop *ir)
{
/* We don't want debugging output to print the whole body of the
* loop as the annotation.
*/
this->base_ir = NULL;
emit(BRW_OPCODE_DO);
visit_instructions(&ir->body_instructions);
emit(BRW_OPCODE_WHILE);
}
void
vec4_visitor::visit(ir_loop_jump *ir)
{
switch (ir->mode) {
case ir_loop_jump::jump_break:
emit(BRW_OPCODE_BREAK);
break;
case ir_loop_jump::jump_continue:
emit(BRW_OPCODE_CONTINUE);
break;
}
}
void
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
vec4_visitor::visit(ir_function_signature *)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
void
vec4_visitor::visit(ir_function *ir)
{
/* Ignore function bodies other than main() -- we shouldn't see calls to
* them since they should all be inlined.
*/
if (strcmp(ir->name, "main") == 0) {
const ir_function_signature *sig;
exec_list empty;
glsl: Make it possible to ignore built-ins when matching signatures. Historically, we've implemented the rules for overriding built-in functions by creating multiple ir_functions and relying on the symbol table to hide the one containing built-in functions. That works, but has a few drawbacks, so the next patch will change it. Instead, we'll have a single ir_function for a particular name, which will contain both built-in and user-defined signatures. Passing an extra parameter to matching_signature makes it easy to ignore built-ins when they're supposed to be hidden. I didn't add the parameter to exact_matching_signature since it wasn't necessary. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-24 22:05:40 +01:00
sig = ir->matching_signature(NULL, &empty, false);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
assert(sig);
visit_instructions(&sig->body);
}
}
i965/vs: Use the MAD instruction when possible. This is different from how we do it in the FS - we are using MAD even when some of the args are constants, because with the relatively unrestrained ability to schedule a MOV to prepare a temporary with that data, we can get lower latency for the sequence of instructions. No significant performance difference on GLB2.7 trex (n=33/34), though it doesn't have that many MADs. I noticed MAD opportunities while reading the code for the DOTA2 bug. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-06-06 18:14:41 +01:00
bool
i965/vec4: Remove 'mul_arg' from try_emit_mad(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-28 18:30:50 +01:00
vec4_visitor::try_emit_mad(ir_expression *ir)
i965/vs: Use the MAD instruction when possible. This is different from how we do it in the FS - we are using MAD even when some of the args are constants, because with the relatively unrestrained ability to schedule a MOV to prepare a temporary with that data, we can get lower latency for the sequence of instructions. No significant performance difference on GLB2.7 trex (n=33/34), though it doesn't have that many MADs. I noticed MAD opportunities while reading the code for the DOTA2 bug. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-06-06 18:14:41 +01:00
{
/* 3-src instructions were introduced in gen6. */
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen < 6)
i965/vs: Use the MAD instruction when possible. This is different from how we do it in the FS - we are using MAD even when some of the args are constants, because with the relatively unrestrained ability to schedule a MOV to prepare a temporary with that data, we can get lower latency for the sequence of instructions. No significant performance difference on GLB2.7 trex (n=33/34), though it doesn't have that many MADs. I noticed MAD opportunities while reading the code for the DOTA2 bug. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-06-06 18:14:41 +01:00
return false;
/* MAD can only handle floating-point data. */
if (ir->type->base_type != GLSL_TYPE_FLOAT)
return false;
i965/vec4: Remove 'mul_arg' from try_emit_mad(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-28 18:30:50 +01:00
ir_rvalue *nonmul = ir->operands[1];
ir_expression *mul = ir->operands[0]->as_expression();
i965/vs: Use the MAD instruction when possible. This is different from how we do it in the FS - we are using MAD even when some of the args are constants, because with the relatively unrestrained ability to schedule a MOV to prepare a temporary with that data, we can get lower latency for the sequence of instructions. No significant performance difference on GLB2.7 trex (n=33/34), though it doesn't have that many MADs. I noticed MAD opportunities while reading the code for the DOTA2 bug. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-06-06 18:14:41 +01:00
i965/vec4: Emit MADs from (x + abs(y * z)). Same as commit 3654b6d4 to the fs backend. total instructions in shared programs: 5945788 -> 5945787 (-0.00%) instructions in affected programs: 36 -> 35 (-2.78%) helped: 1 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-01-31 02:24:20 +00:00
bool mul_negate = false, mul_abs = false;
if (mul && mul->operation == ir_unop_abs) {
mul = mul->operands[0]->as_expression();
mul_abs = true;
} else if (mul && mul->operation == ir_unop_neg) {
i965/vec4: Emit MADs from (x + -(y * z)). Same as commit c4fab711 to the fs backend. total instructions in shared programs: 5945998 -> 5945788 (-0.00%) instructions in affected programs: 74665 -> 74455 (-0.28%) helped: 399 HURT: 180 It hurts some programs because we make no attempts in the vec4 backend to avoid MADs if they have constant (or vector uniform) arguments. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-12-20 05:35:56 +00:00
mul = mul->operands[0]->as_expression();
mul_negate = true;
}
i965/vec4: Remove 'mul_arg' from try_emit_mad(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-28 18:30:50 +01:00
if (!mul || mul->operation != ir_binop_mul) {
nonmul = ir->operands[0];
mul = ir->operands[1]->as_expression();
i965/vec4: Emit MADs from (x + abs(y * z)). Same as commit 3654b6d4 to the fs backend. total instructions in shared programs: 5945788 -> 5945787 (-0.00%) instructions in affected programs: 36 -> 35 (-2.78%) helped: 1 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-01-31 02:24:20 +00:00
if (mul && mul->operation == ir_unop_abs) {
mul = mul->operands[0]->as_expression();
mul_abs = true;
} else if (mul && mul->operation == ir_unop_neg) {
i965/vec4: Emit MADs from (x + -(y * z)). Same as commit c4fab711 to the fs backend. total instructions in shared programs: 5945998 -> 5945788 (-0.00%) instructions in affected programs: 74665 -> 74455 (-0.28%) helped: 399 HURT: 180 It hurts some programs because we make no attempts in the vec4 backend to avoid MADs if they have constant (or vector uniform) arguments. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-12-20 05:35:56 +00:00
mul = mul->operands[0]->as_expression();
mul_negate = true;
}
i965/vec4: Remove 'mul_arg' from try_emit_mad(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-28 18:30:50 +01:00
if (!mul || mul->operation != ir_binop_mul)
return false;
}
i965/vs: Use the MAD instruction when possible. This is different from how we do it in the FS - we are using MAD even when some of the args are constants, because with the relatively unrestrained ability to schedule a MOV to prepare a temporary with that data, we can get lower latency for the sequence of instructions. No significant performance difference on GLB2.7 trex (n=33/34), though it doesn't have that many MADs. I noticed MAD opportunities while reading the code for the DOTA2 bug. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-06-06 18:14:41 +01:00
nonmul->accept(this);
src_reg src0 = fix_3src_operand(this->result);
mul->operands[0]->accept(this);
src_reg src1 = fix_3src_operand(this->result);
i965/vec4: Emit MADs from (x + -(y * z)). Same as commit c4fab711 to the fs backend. total instructions in shared programs: 5945998 -> 5945788 (-0.00%) instructions in affected programs: 74665 -> 74455 (-0.28%) helped: 399 HURT: 180 It hurts some programs because we make no attempts in the vec4 backend to avoid MADs if they have constant (or vector uniform) arguments. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-12-20 05:35:56 +00:00
src1.negate ^= mul_negate;
i965/vec4: Emit MADs from (x + abs(y * z)). Same as commit 3654b6d4 to the fs backend. total instructions in shared programs: 5945788 -> 5945787 (-0.00%) instructions in affected programs: 36 -> 35 (-2.78%) helped: 1 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-01-31 02:24:20 +00:00
src1.abs = mul_abs;
if (mul_abs)
src1.negate = false;
i965/vs: Use the MAD instruction when possible. This is different from how we do it in the FS - we are using MAD even when some of the args are constants, because with the relatively unrestrained ability to schedule a MOV to prepare a temporary with that data, we can get lower latency for the sequence of instructions. No significant performance difference on GLB2.7 trex (n=33/34), though it doesn't have that many MADs. I noticed MAD opportunities while reading the code for the DOTA2 bug. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-06-06 18:14:41 +01:00
mul->operands[1]->accept(this);
src_reg src2 = fix_3src_operand(this->result);
i965/vec4: Emit MADs from (x + abs(y * z)). Same as commit 3654b6d4 to the fs backend. total instructions in shared programs: 5945788 -> 5945787 (-0.00%) instructions in affected programs: 36 -> 35 (-2.78%) helped: 1 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-01-31 02:24:20 +00:00
src2.abs = mul_abs;
if (mul_abs)
src2.negate = false;
i965/vs: Use the MAD instruction when possible. This is different from how we do it in the FS - we are using MAD even when some of the args are constants, because with the relatively unrestrained ability to schedule a MOV to prepare a temporary with that data, we can get lower latency for the sequence of instructions. No significant performance difference on GLB2.7 trex (n=33/34), though it doesn't have that many MADs. I noticed MAD opportunities while reading the code for the DOTA2 bug. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-06-06 18:14:41 +01:00
this->result = src_reg(this, ir->type);
emit(BRW_OPCODE_MAD, dst_reg(this->result), src0, src1, src2);
return true;
}
i965/vec4: Emit smarter code for b2f of a comparison Previously we would emit the comparison, emit an AND to mask off extra bits from the comparison result, then convert the result to float. Now, do the comparison, then use a cleverly constructed SEL to pick either 0.0f or 1.0f. No piglit regressions on Ivybridge. total instructions in shared programs: 1642311 -> 1639449 (-0.17%) instructions in affected programs: 136533 -> 133671 (-2.10%) GAINED: 0 LOST: 0 Programs that are affected appear to save between 1 and 5 instuctions (just by skimming the output from shader-db report.py. v2: s/b2i/b2f/ in commit subject (noticed by Chris Forbes). Remove extraneous fix_3src_operand (suggested by Matt). The latter change required swapping the order of the operands and using predicate_inverse. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-11 02:07:50 +01:00
bool
vec4_visitor::try_emit_b2f_of_compare(ir_expression *ir)
{
i965: Disable try_emit_b2f_of_compare on Gen4-6. The optimization relies on CMP setting the destination to 0, which is equivalent to 0.0f. However, early platforms only set the least significant byte, leaving the other bits undefined. So, we must disable the optimization on those platforms. Oddly, Sandybridge wasn't reported as broken. The PRM states that it only sets the LSB, but the internal documentation says that it follows the IVB behavior. Since it wasn't reported as broken, we believe it really does follow the IVB behavior. v2: Allow the optimization on Sandybridge (requested by Matt). +32 piglits on Ironlake. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?=79963 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-16 23:18:21 +01:00
/* This optimization relies on CMP setting the destination to 0 when
* false. Early hardware only sets the least significant bit, and
* leaves the other bits undefined. So we can't use it.
*/
if (brw->gen < 6)
return false;
i965/vec4: Emit smarter code for b2f of a comparison Previously we would emit the comparison, emit an AND to mask off extra bits from the comparison result, then convert the result to float. Now, do the comparison, then use a cleverly constructed SEL to pick either 0.0f or 1.0f. No piglit regressions on Ivybridge. total instructions in shared programs: 1642311 -> 1639449 (-0.17%) instructions in affected programs: 136533 -> 133671 (-2.10%) GAINED: 0 LOST: 0 Programs that are affected appear to save between 1 and 5 instuctions (just by skimming the output from shader-db report.py. v2: s/b2i/b2f/ in commit subject (noticed by Chris Forbes). Remove extraneous fix_3src_operand (suggested by Matt). The latter change required swapping the order of the operands and using predicate_inverse. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-11 02:07:50 +01:00
ir_expression *const cmp = ir->operands[0]->as_expression();
if (cmp == NULL)
return false;
switch (cmp->operation) {
case ir_binop_less:
case ir_binop_greater:
case ir_binop_lequal:
case ir_binop_gequal:
case ir_binop_equal:
case ir_binop_nequal:
break;
default:
return false;
}
cmp->operands[0]->accept(this);
const src_reg cmp_src0 = this->result;
cmp->operands[1]->accept(this);
const src_reg cmp_src1 = this->result;
this->result = src_reg(this, ir->type);
emit(CMP(dst_reg(this->result), cmp_src0, cmp_src1,
brw_conditional_for_comparison(cmp->operation)));
/* If the comparison is false, this->result will just happen to be zero.
*/
vec4_instruction *const inst = emit(BRW_OPCODE_SEL, dst_reg(this->result),
this->result, src_reg(1.0f));
inst->predicate = BRW_PREDICATE_NORMAL;
inst->predicate_inverse = true;
return true;
}
i965/vs: Refactor min/max handling to share code. v2: Properly use "conditionalmod" pre-Gen6, rather than the incorrectly copy-and-pasted "BRW_CONDITIONAL_G". Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-10-08 18:45:08 +01:00
void
i965: Make a brw_conditional_mod enum. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-06-30 01:50:20 +01:00
vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
i965/vs: Refactor min/max handling to share code. v2: Properly use "conditionalmod" pre-Gen6, rather than the incorrectly copy-and-pasted "BRW_CONDITIONAL_G". Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-10-08 18:45:08 +01:00
src_reg src0, src_reg src1)
{
vec4_instruction *inst;
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 6) {
i965/vs: Refactor min/max handling to share code. v2: Properly use "conditionalmod" pre-Gen6, rather than the incorrectly copy-and-pasted "BRW_CONDITIONAL_G". Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-10-08 18:45:08 +01:00
inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
inst->conditional_mod = conditionalmod;
} else {
emit(CMP(dst, src0, src1, conditionalmod));
inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
inst->predicate = BRW_PREDICATE_NORMAL;
}
}
i965/vec4: Handle ir_triop_lrp on Gen4-5 as well. When the vec4 backend encountered an ir_triop_lrp, it always emitted an actual LRP instruction, which only exists on Gen6+. Gen4-5 used lower_instructions() to decompose ir_triop_lrp at the IR level. Since commit 8d37e9915a3b21 ("glsl: Optimize open-coded lrp into lrp."), we've had an bug where lower_instructions translates ir_triop_lrp into arithmetic, but opt_algebraic reassembles it back into a lrp. To avoid this ordering concern, just handle ir_triop_lrp in the backend. The FS backend already does this, so we may as well do likewise. v2: Add a comment reminding us that we could emit better assembly if we implemented the infrastructure necessary to support using MAC. (Assembly code provided by Eric Anholt). Cc: "10.1" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75253 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Acked-by: Eric Anholt <eric@anholt.net>
2014-02-24 00:29:46 +00:00
void
vec4_visitor::emit_lrp(const dst_reg &dst,
const src_reg &x, const src_reg &y, const src_reg &a)
{
if (brw->gen >= 6) {
/* Note that the instruction's argument order is reversed from GLSL
* and the IR.
*/
emit(LRP(dst,
fix_3src_operand(a), fix_3src_operand(y), fix_3src_operand(x)));
} else {
/* Earlier generations don't support three source operations, so we
* need to emit x*(1-a) + y*a.
*/
Revert "i965/vec4: Change vec4_visitor::emit_lrp to use MAC for gen<6" This reverts commit 2dfbbeca50b95ccdd714d9baa4411c779f6a20d9 with the comment about MAC and implicit accumulator removed. Why this code didn't work in all circumstances is unknown and without a working Ironlake simulator (which uses a different AUB format) we'll probably never know, short of a lot of experimentation, and spending a bunch of time to try to optimize a few instructions on Ironlake is not time well spent. Moreover, for mix(vec4, vec4, vec4) using the accumulator introduces a dependence between the otherwise independent per-component calculations. Not using the accumulator, even if it means an extra instruction per component might be preferable. We don't know, we don't have data, and we don't have the necessary register on Ironlake for shader_time to tell us. Cc: "10.2" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77703 Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-22 17:38:24 +01:00
dst_reg y_times_a = dst_reg(this, glsl_type::vec4_type);
dst_reg one_minus_a = dst_reg(this, glsl_type::vec4_type);
dst_reg x_times_one_minus_a = dst_reg(this, glsl_type::vec4_type);
y_times_a.writemask = dst.writemask;
one_minus_a.writemask = dst.writemask;
x_times_one_minus_a.writemask = dst.writemask;
emit(MUL(y_times_a, y, a));
i965/vec4: Handle ir_triop_lrp on Gen4-5 as well. When the vec4 backend encountered an ir_triop_lrp, it always emitted an actual LRP instruction, which only exists on Gen6+. Gen4-5 used lower_instructions() to decompose ir_triop_lrp at the IR level. Since commit 8d37e9915a3b21 ("glsl: Optimize open-coded lrp into lrp."), we've had an bug where lower_instructions translates ir_triop_lrp into arithmetic, but opt_algebraic reassembles it back into a lrp. To avoid this ordering concern, just handle ir_triop_lrp in the backend. The FS backend already does this, so we may as well do likewise. v2: Add a comment reminding us that we could emit better assembly if we implemented the infrastructure necessary to support using MAC. (Assembly code provided by Eric Anholt). Cc: "10.1" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75253 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Acked-by: Eric Anholt <eric@anholt.net>
2014-02-24 00:29:46 +00:00
emit(ADD(one_minus_a, negate(a), src_reg(1.0f)));
Revert "i965/vec4: Change vec4_visitor::emit_lrp to use MAC for gen<6" This reverts commit 2dfbbeca50b95ccdd714d9baa4411c779f6a20d9 with the comment about MAC and implicit accumulator removed. Why this code didn't work in all circumstances is unknown and without a working Ironlake simulator (which uses a different AUB format) we'll probably never know, short of a lot of experimentation, and spending a bunch of time to try to optimize a few instructions on Ironlake is not time well spent. Moreover, for mix(vec4, vec4, vec4) using the accumulator introduces a dependence between the otherwise independent per-component calculations. Not using the accumulator, even if it means an extra instruction per component might be preferable. We don't know, we don't have data, and we don't have the necessary register on Ironlake for shader_time to tell us. Cc: "10.2" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77703 Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-22 17:38:24 +01:00
emit(MUL(x_times_one_minus_a, x, src_reg(one_minus_a)));
emit(ADD(dst, src_reg(x_times_one_minus_a), src_reg(y_times_a)));
i965/vec4: Handle ir_triop_lrp on Gen4-5 as well. When the vec4 backend encountered an ir_triop_lrp, it always emitted an actual LRP instruction, which only exists on Gen6+. Gen4-5 used lower_instructions() to decompose ir_triop_lrp at the IR level. Since commit 8d37e9915a3b21 ("glsl: Optimize open-coded lrp into lrp."), we've had an bug where lower_instructions translates ir_triop_lrp into arithmetic, but opt_algebraic reassembles it back into a lrp. To avoid this ordering concern, just handle ir_triop_lrp in the backend. The FS backend already does this, so we may as well do likewise. v2: Add a comment reminding us that we could emit better assembly if we implemented the infrastructure necessary to support using MAC. (Assembly code provided by Eric Anholt). Cc: "10.1" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75253 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Acked-by: Eric Anholt <eric@anholt.net>
2014-02-24 00:29:46 +00:00
}
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
void
vec4_visitor::visit(ir_expression *ir)
{
unsigned int operand;
src_reg op[Elements(ir->operands)];
vec4_instruction *inst;
i965/vs: Use the MAD instruction when possible. This is different from how we do it in the FS - we are using MAD even when some of the args are constants, because with the relatively unrestrained ability to schedule a MOV to prepare a temporary with that data, we can get lower latency for the sequence of instructions. No significant performance difference on GLB2.7 trex (n=33/34), though it doesn't have that many MADs. I noticed MAD opportunities while reading the code for the DOTA2 bug. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-06-06 18:14:41 +01:00
if (ir->operation == ir_binop_add) {
i965/vec4: Remove 'mul_arg' from try_emit_mad(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-28 18:30:50 +01:00
if (try_emit_mad(ir))
i965/vs: Use the MAD instruction when possible. This is different from how we do it in the FS - we are using MAD even when some of the args are constants, because with the relatively unrestrained ability to schedule a MOV to prepare a temporary with that data, we can get lower latency for the sequence of instructions. No significant performance difference on GLB2.7 trex (n=33/34), though it doesn't have that many MADs. I noticed MAD opportunities while reading the code for the DOTA2 bug. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-06-06 18:14:41 +01:00
return;
}
i965/vec4: Emit smarter code for b2f of a comparison Previously we would emit the comparison, emit an AND to mask off extra bits from the comparison result, then convert the result to float. Now, do the comparison, then use a cleverly constructed SEL to pick either 0.0f or 1.0f. No piglit regressions on Ivybridge. total instructions in shared programs: 1642311 -> 1639449 (-0.17%) instructions in affected programs: 136533 -> 133671 (-2.10%) GAINED: 0 LOST: 0 Programs that are affected appear to save between 1 and 5 instuctions (just by skimming the output from shader-db report.py. v2: s/b2i/b2f/ in commit subject (noticed by Chris Forbes). Remove extraneous fix_3src_operand (suggested by Matt). The latter change required swapping the order of the operands and using predicate_inverse. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-11 02:07:50 +01:00
if (ir->operation == ir_unop_b2f) {
if (try_emit_b2f_of_compare(ir))
return;
}
i965/vec4: Simplify visit(ir_expression *)'s result_src/dst setup. Using dst_reg(this, ir->type) automatically sets the writemask to the proper size for the type; src_reg(dst_reg) preserves that. This should be equivalent, but less code. Note that src_reg(dst_reg) either uses SWIZZLE_XXXX or SWIZZLE_XYZW, so the old code did need the manual writemask adjustment, since it constructed the registers the other way around. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-10-16 03:17:21 +01:00
/* Storage for our result. Ideally for an assignment we'd be using
* the actual storage for the result here, instead.
*/
dst_reg result_dst(this, ir->type);
src_reg result_src(result_dst);
i965/vec4: Generate better code for ir_triop_csel. Previously, we generated an extra CMP instruction: cmp.ge.f0(8) g6<1>D g1<0,4,1>F 0F cmp.nz.f0(8) null g6<4,4,1>D 0D (+f0) sel(8) g5<1>F g1.4<0,4,1>F g2<0,4,1>F The first operand is always a boolean, and we want to predicate the SEL on that. Rather than producing a boolean value and comparing it against zero, we can just produce a condition code in the flag register. Now we generate: cmp.ge.f0(8) null g1<0,4,1>F 0F (+f0) sel(8) g5<1>F g1.4<0,4,1>F g2<0,4,1>F No difference in shader-db. v2: Remember to delete the old code (thanks Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-10-16 02:57:07 +01:00
if (ir->operation == ir_triop_csel) {
ir->operands[1]->accept(this);
op[1] = this->result;
ir->operands[2]->accept(this);
op[2] = this->result;
enum brw_predicate predicate;
emit_bool_to_cond_code(ir->operands[0], &predicate);
inst = emit(BRW_OPCODE_SEL, result_dst, op[1], op[2]);
inst->predicate = predicate;
this->result = result_src;
return;
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
for (operand = 0; operand < ir->get_num_operands(); operand++) {
this->result.file = BAD_FILE;
ir->operands[operand]->accept(this);
if (this->result.file == BAD_FILE) {
i965: Move compiler debugging output to stderr. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-12-23 07:29:31 +00:00
fprintf(stderr, "Failed to get tree for expression operand:\n");
ir->operands[operand]->fprint(stderr);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
exit(1);
}
op[operand] = this->result;
/* Matrix expression operands should have been broken down to vector
* operations already.
*/
assert(!ir->operands[operand]->type->is_matrix());
}
/* If nothing special happens, this is the result. */
this->result = result_src;
switch (ir->operation) {
case ir_unop_logic_not:
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
emit(NOT(result_dst, op[0]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_unop_neg:
op[0].negate = !op[0].negate;
i965: Emit MOVs for neg/abs. Necessary to avoid combining a bitcast and a modifier into a single operation. Otherwise if safe, the MOV should be removed by copy-propagation or register coalescing. With this and the next patch, there are only four changes in shader-db: all a single extra instruction. The code does something like mov a.w, -b.x and copy propagation doesn't work because it only handles no-op swizzles. Seems acceptable, given the known limitation of our copy propagation. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Paul Berry <stereoytpe441@gmail.com>
2013-08-08 21:50:01 +01:00
emit(MOV(result_dst, op[0]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_unop_abs:
op[0].abs = true;
op[0].negate = false;
i965: Emit MOVs for neg/abs. Necessary to avoid combining a bitcast and a modifier into a single operation. Otherwise if safe, the MOV should be removed by copy-propagation or register coalescing. With this and the next patch, there are only four changes in shader-db: all a single extra instruction. The code does something like mov a.w, -b.x and copy propagation doesn't work because it only handles no-op swizzles. Seems acceptable, given the known limitation of our copy propagation. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Paul Berry <stereoytpe441@gmail.com>
2013-08-08 21:50:01 +01:00
emit(MOV(result_dst, op[0]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_unop_sign:
i965: Emit better code for ir_unop_sign. total instructions in shared programs: 1550449 -> 1550048 (-0.03%) instructions in affected programs: 15207 -> 14806 (-2.64%) Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-11-25 06:44:32 +00:00
if (ir->type->is_float()) {
/* AND(val, 0x80000000) gives the sign bit.
*
* Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
* zero.
*/
emit(CMP(dst_null_f(), op[0], src_reg(0.0f), BRW_CONDITIONAL_NZ));
op[0].type = BRW_REGISTER_TYPE_UD;
result_dst.type = BRW_REGISTER_TYPE_UD;
emit(AND(result_dst, op[0], src_reg(0x80000000u)));
inst = emit(OR(result_dst, src_reg(result_dst), src_reg(0x3f800000u)));
inst->predicate = BRW_PREDICATE_NORMAL;
this->result.type = BRW_REGISTER_TYPE_F;
} else {
/* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
* -> non-negative val generates 0x00000000.
* Predicated OR sets 1 if val is positive.
*/
emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_G));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965: Emit better code for ir_unop_sign. total instructions in shared programs: 1550449 -> 1550048 (-0.03%) instructions in affected programs: 15207 -> 14806 (-2.64%) Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-11-25 06:44:32 +00:00
emit(ASR(result_dst, op[0], src_reg(31)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965: Emit better code for ir_unop_sign. total instructions in shared programs: 1550449 -> 1550048 (-0.03%) instructions in affected programs: 15207 -> 14806 (-2.64%) Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-11-25 06:44:32 +00:00
inst = emit(OR(result_dst, src_reg(result_dst), src_reg(1)));
inst->predicate = BRW_PREDICATE_NORMAL;
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_unop_rcp:
emit_math(SHADER_OPCODE_RCP, result_dst, op[0]);
break;
case ir_unop_exp2:
emit_math(SHADER_OPCODE_EXP2, result_dst, op[0]);
break;
case ir_unop_log2:
emit_math(SHADER_OPCODE_LOG2, result_dst, op[0]);
break;
case ir_unop_exp:
case ir_unop_log:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached: should be handled by ir_explog_to_explog2");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_unop_sin:
case ir_unop_sin_reduced:
emit_math(SHADER_OPCODE_SIN, result_dst, op[0]);
break;
case ir_unop_cos:
case ir_unop_cos_reduced:
emit_math(SHADER_OPCODE_COS, result_dst, op[0]);
break;
case ir_unop_dFdx:
i965/vec4: Assert that fine/coarse derivative ops don't appear Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 09:38:33 +01:00
case ir_unop_dFdx_coarse:
case ir_unop_dFdx_fine:
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_unop_dFdy:
i965/vec4: Assert that fine/coarse derivative ops don't appear Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 09:38:33 +01:00
case ir_unop_dFdy_coarse:
case ir_unop_dFdy_fine:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("derivatives not valid in vertex shader");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: Add support for bit instructions. v2: Rebase on LRP addition. Use fix_3src_operand() when emitting BFE and BFI2. Add BFE and BFI2 to is_3src_inst check in brw_vec4_copy_propagation.cpp. Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-04-18 02:57:58 +01:00
case ir_unop_bitfield_reverse:
emit(BFREV(result_dst, op[0]));
break;
case ir_unop_bit_count:
emit(CBIT(result_dst, op[0]));
break;
case ir_unop_find_msb: {
src_reg temp = src_reg(this, glsl_type::uint_type);
inst = emit(FBH(dst_reg(temp), op[0]));
inst->dst.writemask = WRITEMASK_XYZW;
/* FBH counts from the MSB side, while GLSL's findMSB() wants the count
* from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
* subtract the result from 31 to convert the MSB count into an LSB count.
*/
/* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
temp.swizzle = BRW_SWIZZLE_NOOP;
emit(MOV(result_dst, temp));
src_reg src_tmp = src_reg(result_dst);
emit(CMP(dst_null_d(), src_tmp, src_reg(-1), BRW_CONDITIONAL_NZ));
src_tmp.negate = true;
inst = emit(ADD(result_dst, src_tmp, src_reg(31)));
inst->predicate = BRW_PREDICATE_NORMAL;
break;
}
case ir_unop_find_lsb:
emit(FBL(result_dst, op[0]));
break;
yi965/vec4: Add support for ir_unop_saturate Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-06-16 21:56:50 +01:00
case ir_unop_saturate:
inst = emit(MOV(result_dst, op[0]));
inst->saturate = true;
break;
i965/vs: Add support for bit instructions. v2: Rebase on LRP addition. Use fix_3src_operand() when emitting BFE and BFI2. Add BFE and BFI2 to is_3src_inst check in brw_vec4_copy_propagation.cpp. Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-04-18 02:57:58 +01:00
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_unop_noise:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached: should be handled by lower_noise");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_binop_add:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(ADD(result_dst, op[0], op[1]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_sub:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached: should be handled by ir_sub_to_add_neg");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_binop_mul:
i965: Don't use MACH for integer multiplies on Gen8+. The documentation is really hard to follow, but apparently a 32-bit x 32-bit multiply just works without the MACH macro. The macro apparently is only necessary to get the full 64-bit value. Fixes Piglit tests [vf]s-op-mult-int-int.shader_test. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-01-20 16:58:14 +00:00
if (brw->gen < 8 && ir->type->is_integer()) {
i965/vs: Avoid the MUL/MACH/MOV sequence for small integer multiplies. We do a lot of multiplies by 3 or 4 for skinning shaders, and we can avoid the sequence if we just move them into the right argument of the MUL. On pre-IVB, this means reliably putting a constant in a position where it can't be constant folded, but that's still better than MUL/MACH/MOV. Improves GLB 2.7 trex performance by 0.788648% +/- 0.23865% (n=29/30) v2: Fix test for pre-sandybridge. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> (v1)
2013-06-08 02:29:50 +01:00
/* For integer multiplication, the MUL uses the low 16 bits of one of
* the operands (src0 through SNB, src1 on IVB and later). The MACH
* accumulates in the contribution of the upper 16 bits of that
* operand. If we can determine that one of the args is in the low
* 16 bits, though, we can just emit a single MUL.
*/
glsl: Make is_16bit_constant from i965 an ir_constant method. The i965 MUL instruction doesn't natively support 32-bit by 32-bit integer multiplication; additional instructions (MACH/MOV) are required. However, we can avoid those if we know one of the operands can be represented in 16 bits or less. The vector backend's is_16bit_constant static helper function checks for this. We want to be able to use it in the scalar backend as well, which means moving the function to a more generally-usable location. Since it isn't i965 specific, I decided to make it an ir_constant method, in case it ends up being useful to other people as well. v2: Rename from is_16bit_integer_constant to is_uint16_constant, as suggested by Ilia Mirkin. Update comments to clarify that it does apply to both int and uint types, as long as the value is non-negative and fits in 16-bits. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-04-07 02:34:59 +01:00
if (ir->operands[0]->is_uint16_constant()) {
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen < 7)
i965/vs: Avoid the MUL/MACH/MOV sequence for small integer multiplies. We do a lot of multiplies by 3 or 4 for skinning shaders, and we can avoid the sequence if we just move them into the right argument of the MUL. On pre-IVB, this means reliably putting a constant in a position where it can't be constant folded, but that's still better than MUL/MACH/MOV. Improves GLB 2.7 trex performance by 0.788648% +/- 0.23865% (n=29/30) v2: Fix test for pre-sandybridge. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> (v1)
2013-06-08 02:29:50 +01:00
emit(MUL(result_dst, op[0], op[1]));
else
emit(MUL(result_dst, op[1], op[0]));
glsl: Make is_16bit_constant from i965 an ir_constant method. The i965 MUL instruction doesn't natively support 32-bit by 32-bit integer multiplication; additional instructions (MACH/MOV) are required. However, we can avoid those if we know one of the operands can be represented in 16 bits or less. The vector backend's is_16bit_constant static helper function checks for this. We want to be able to use it in the scalar backend as well, which means moving the function to a more generally-usable location. Since it isn't i965 specific, I decided to make it an ir_constant method, in case it ends up being useful to other people as well. v2: Rename from is_16bit_integer_constant to is_uint16_constant, as suggested by Ilia Mirkin. Update comments to clarify that it does apply to both int and uint types, as long as the value is non-negative and fits in 16-bits. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-04-07 02:34:59 +01:00
} else if (ir->operands[1]->is_uint16_constant()) {
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen < 7)
i965/vs: Avoid the MUL/MACH/MOV sequence for small integer multiplies. We do a lot of multiplies by 3 or 4 for skinning shaders, and we can avoid the sequence if we just move them into the right argument of the MUL. On pre-IVB, this means reliably putting a constant in a position where it can't be constant folded, but that's still better than MUL/MACH/MOV. Improves GLB 2.7 trex performance by 0.788648% +/- 0.23865% (n=29/30) v2: Fix test for pre-sandybridge. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> (v1)
2013-06-08 02:29:50 +01:00
emit(MUL(result_dst, op[1], op[0]));
else
emit(MUL(result_dst, op[0], op[1]));
} else {
i965/brw_reg: Make the accumulator register take an explicit width. The big pile of patches I just pushed regresses about 25 piglit tests on SNB. This fixes the regressions. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-09-30 18:15:23 +01:00
struct brw_reg acc = retype(brw_acc_reg(8), result_dst.type);
i965/vs: Avoid the MUL/MACH/MOV sequence for small integer multiplies. We do a lot of multiplies by 3 or 4 for skinning shaders, and we can avoid the sequence if we just move them into the right argument of the MUL. On pre-IVB, this means reliably putting a constant in a position where it can't be constant folded, but that's still better than MUL/MACH/MOV. Improves GLB 2.7 trex performance by 0.788648% +/- 0.23865% (n=29/30) v2: Fix test for pre-sandybridge. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> (v1)
2013-06-08 02:29:50 +01:00
emit(MUL(acc, op[0], op[1]));
emit(MACH(dst_null_d(), op[0], op[1]));
emit(MOV(result_dst, src_reg(acc)));
}
i965/vs: Fix multiplies to actually do 32-bit multiplies. Fixes vs-op-mult-int-int and friends.
2011-08-16 05:02:10 +01:00
} else {
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(MUL(result_dst, op[0], op[1]));
i965/vs: Fix multiplies to actually do 32-bit multiplies. Fixes vs-op-mult-int-int and friends.
2011-08-16 05:02:10 +01:00
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
i965: Generate code for ir_binop_imul_high. v2: Make accumulator's type match the type of the operation. Noticed by Ken. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-18 05:34:45 +01:00
case ir_binop_imul_high: {
i965/brw_reg: Make the accumulator register take an explicit width. The big pile of patches I just pushed regresses about 25 piglit tests on SNB. This fixes the regressions. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-09-30 18:15:23 +01:00
struct brw_reg acc = retype(brw_acc_reg(8), result_dst.type);
i965: Generate code for ir_binop_imul_high. v2: Make accumulator's type match the type of the operation. Noticed by Ken. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-18 05:34:45 +01:00
emit(MUL(acc, op[0], op[1]));
emit(MACH(result_dst, op[0], op[1]));
break;
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_binop_div:
i965/vs: Implement integer quotient and remainder math operations. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-29 01:37:55 +01:00
/* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
assert(ir->type->is_integer());
emit_math(SHADER_OPCODE_INT_QUOTIENT, result_dst, op[0], op[1]);
break;
i965: Generate code for ir_binop_carry and ir_binop_borrow. Using the ADDC and SUBB instructions on Gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-19 21:01:08 +01:00
case ir_binop_carry: {
i965/brw_reg: Make the accumulator register take an explicit width. The big pile of patches I just pushed regresses about 25 piglit tests on SNB. This fixes the regressions. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-09-30 18:15:23 +01:00
struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD);
i965: Generate code for ir_binop_carry and ir_binop_borrow. Using the ADDC and SUBB instructions on Gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-19 21:01:08 +01:00
emit(ADDC(dst_null_ud(), op[0], op[1]));
emit(MOV(result_dst, src_reg(acc)));
break;
}
case ir_binop_borrow: {
i965/brw_reg: Make the accumulator register take an explicit width. The big pile of patches I just pushed regresses about 25 piglit tests on SNB. This fixes the regressions. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-09-30 18:15:23 +01:00
struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD);
i965: Generate code for ir_binop_carry and ir_binop_borrow. Using the ADDC and SUBB instructions on Gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-19 21:01:08 +01:00
emit(SUBB(dst_null_ud(), op[0], op[1]));
emit(MOV(result_dst, src_reg(acc)));
break;
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_binop_mod:
glsl: Improve precision of mod(x,y) Currently, Mesa uses the lowering pass MOD_TO_FRACT to implement mod(x,y) as y * fract(x/y). This implementation has a down side though: it introduces precision errors due to the fract() operation. Even worse, since the result of fract() is multiplied by y, the larger y gets the larger the precision error we produce, so for large enough numbers the precision loss is significant. Some examples on i965: Operation Precision error ----------------------------------------------------- mod(-1.951171875, 1.9980468750) 0.0000000447 mod(121.57, 13.29) 0.0000023842 mod(3769.12, 321.99) 0.0000762939 mod(3769.12, 1321.99) 0.0001220703 mod(-987654.125, 123456.984375) 0.0160663128 mod( 987654.125, 123456.984375) 0.0312500000 This patch replaces the current lowering pass with a different one (MOD_TO_FLOOR) that follows the recommended implementation in the GLSL man pages: mod(x,y) = x - y * floor(x/y) This implementation eliminates the precision errors at the expense of an additional add instruction on some systems. On systems that can do negate with multiply-add in a single operation this new implementation would come at no additional cost. v2 (Ian Romanick) - Do not clone operands because when they are expressions we would be duplicating them and that can lead to suboptimal code. Fixes the following 16 dEQP tests: dEQP-GLES3.functional.shaders.builtin_functions.precision.mod.mediump_* dEQP-GLES3.functional.shaders.builtin_functions.precision.mod.highp_* Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-01-20 16:09:59 +00:00
/* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
i965/vs: Implement integer quotient and remainder math operations. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-29 01:37:55 +01:00
assert(ir->type->is_integer());
emit_math(SHADER_OPCODE_INT_REMAINDER, result_dst, op[0], op[1]);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_less:
case ir_binop_greater:
case ir_binop_lequal:
case ir_binop_gequal:
case ir_binop_equal:
case ir_binop_nequal: {
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
if (brw->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
resolve_bool_comparison(ir->operands[1], &op[1]);
}
i965/vs: Move logic for weird CMP type handling to CMP generators. v2: Don't bother with the no-dst-reg version of CMP() Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:59:43 +01:00
emit(CMP(result_dst, op[0], op[1],
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
brw_conditional_for_comparison(ir->operation)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
}
case ir_binop_all_equal:
/* "==" operator producing a scalar boolean. */
if (ir->operands[0]->type->is_vector() ||
ir->operands[1]->type->is_vector()) {
i965/vs: Move logic for weird CMP type handling to CMP generators. v2: Don't bother with the no-dst-reg version of CMP() Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:59:43 +01:00
emit(CMP(dst_null_d(), op[0], op[1], BRW_CONDITIONAL_Z));
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(MOV(result_dst, src_reg(0)));
i965: Change the type of booleans to D. This is a revert of commit 4656c14e ("i965/fs: Change the type of booleans to UD and emit correct immediates") plus some small additional fixes, like casting ctx->Const.UniformBooleanTrue to int and changing UD to D in the ir_unop_b2f cases. Note that it's safe to leave 0x3f800000 as UD and as a literal it's more recognizable than 1065353216. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:30:27 +00:00
inst = emit(MOV(result_dst, src_reg((int)ctx->Const.UniformBooleanTrue)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
inst->predicate = BRW_PREDICATE_ALIGN16_ALL4H;
} else {
i965/vs: Move logic for weird CMP type handling to CMP generators. v2: Don't bother with the no-dst-reg version of CMP() Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:59:43 +01:00
emit(CMP(result_dst, op[0], op[1], BRW_CONDITIONAL_Z));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
break;
case ir_binop_any_nequal:
/* "!=" operator producing a scalar boolean. */
if (ir->operands[0]->type->is_vector() ||
ir->operands[1]->type->is_vector()) {
i965/vs: Move logic for weird CMP type handling to CMP generators. v2: Don't bother with the no-dst-reg version of CMP() Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:59:43 +01:00
emit(CMP(dst_null_d(), op[0], op[1], BRW_CONDITIONAL_NZ));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(MOV(result_dst, src_reg(0)));
i965: Change the type of booleans to D. This is a revert of commit 4656c14e ("i965/fs: Change the type of booleans to UD and emit correct immediates") plus some small additional fixes, like casting ctx->Const.UniformBooleanTrue to int and changing UD to D in the ir_unop_b2f cases. Note that it's safe to leave 0x3f800000 as UD and as a literal it's more recognizable than 1065353216. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:30:27 +00:00
inst = emit(MOV(result_dst, src_reg((int)ctx->Const.UniformBooleanTrue)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
inst->predicate = BRW_PREDICATE_ALIGN16_ANY4H;
} else {
i965/vs: Move logic for weird CMP type handling to CMP generators. v2: Don't bother with the no-dst-reg version of CMP() Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:59:43 +01:00
emit(CMP(result_dst, op[0], op[1], BRW_CONDITIONAL_NZ));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
break;
case ir_unop_any:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
emit(MOV(result_dst, src_reg(0)));
i965/vs: Fix implementation of ir_unop_any. We were inheriting whatever previous predicate existed.
2011-08-09 18:57:09 +01:00
i965: Change the type of booleans to D. This is a revert of commit 4656c14e ("i965/fs: Change the type of booleans to UD and emit correct immediates") plus some small additional fixes, like casting ctx->Const.UniformBooleanTrue to int and changing UD to D in the ir_unop_b2f cases. Note that it's safe to leave 0x3f800000 as UD and as a literal it's more recognizable than 1065353216. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:30:27 +00:00
inst = emit(MOV(result_dst, src_reg((int)ctx->Const.UniformBooleanTrue)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
inst->predicate = BRW_PREDICATE_ALIGN16_ANY4H;
break;
case ir_binop_logic_xor:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(XOR(result_dst, op[0], op[1]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_logic_or:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(OR(result_dst, op[0], op[1]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_logic_and:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(AND(result_dst, op[0], op[1]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_dot:
assert(ir->operands[0]->type->is_vector());
assert(ir->operands[0]->type == ir->operands[1]->type);
emit_dp(result_dst, op[0], op[1], ir->operands[0]->type->vector_elements);
break;
case ir_unop_sqrt:
emit_math(SHADER_OPCODE_SQRT, result_dst, op[0]);
break;
case ir_unop_rsq:
emit_math(SHADER_OPCODE_RSQ, result_dst, op[0]);
break;
i965: Enable the GL_ARB_shader_bit_encode extension. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-07 08:11:28 +01:00
case ir_unop_bitcast_i2f:
case ir_unop_bitcast_u2f:
this->result = op[0];
this->result.type = BRW_REGISTER_TYPE_F;
break;
case ir_unop_bitcast_f2i:
this->result = op[0];
this->result.type = BRW_REGISTER_TYPE_D;
break;
case ir_unop_bitcast_f2u:
this->result = op[0];
this->result.type = BRW_REGISTER_TYPE_UD;
break;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_unop_i2f:
case ir_unop_i2u:
case ir_unop_u2i:
case ir_unop_u2f:
case ir_unop_f2i:
i965: Add support for ir_unop_f2u to i965 backend. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-13 23:49:25 +01:00
case ir_unop_f2u:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(MOV(result_dst, op[0]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
i965: Use ~0 to represent true on Gen >= 6. total instructions in shared programs: 4292303 -> 4288650 (-0.09%) instructions in affected programs: 299670 -> 296017 (-1.22%) Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-08-09 05:00:31 +01:00
case ir_unop_b2i:
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
emit(AND(result_dst, op[0], src_reg(1)));
i965: Use ~0 to represent true on Gen >= 6. total instructions in shared programs: 4292303 -> 4288650 (-0.09%) instructions in affected programs: 299670 -> 296017 (-1.22%) Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-08-09 05:00:31 +01:00
break;
case ir_unop_b2f:
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
if (brw->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
i965: Use ~0 to represent true on Gen >= 6. total instructions in shared programs: 4292303 -> 4288650 (-0.09%) instructions in affected programs: 299670 -> 296017 (-1.22%) Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-08-09 05:00:31 +01:00
}
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
op[0].type = BRW_REGISTER_TYPE_D;
result_dst.type = BRW_REGISTER_TYPE_D;
emit(AND(result_dst, op[0], src_reg(0x3f800000u)));
result_dst.type = BRW_REGISTER_TYPE_F;
i965: Use ~0 to represent true on Gen >= 6. total instructions in shared programs: 4292303 -> 4288650 (-0.09%) instructions in affected programs: 299670 -> 296017 (-1.22%) Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-08-09 05:00:31 +01:00
break;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_unop_f2b:
i965/vs: Move logic for weird CMP type handling to CMP generators. v2: Don't bother with the no-dst-reg version of CMP() Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:59:43 +01:00
emit(CMP(result_dst, op[0], src_reg(0.0f), BRW_CONDITIONAL_NZ));
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
break;
case ir_unop_i2b:
emit(AND(result_dst, op[0], src_reg(1)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_unop_trunc:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(RNDZ(result_dst, op[0]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
i965: Fix bitcast operations with negate (ceil) Commit 0ae9ca12a8 put source modifiers out of the bitcast operations by adding a MOV operation that would handle them separately. It missed the case of ceil though: the implementation negates both its source and destination operands. The source operand will be used for RNDD, which we can handle normally, but we need to fix the modifier for the negated result. v2: - RNDD can handle the source modifier so no need to put that one in a separate MOV. Fixes the following 42 dEQP tests: dEQP-GLES3.functional.shaders.builtin_functions.common.ceil.*_vertex dEQP-GLES3.functional.shaders.builtin_functions.common.ceil.*_fragment dEQP-GLES3.functional.shaders.builtin_functions.precision.ceil._*vertex.* dEQP-GLES3.functional.shaders.builtin_functions.precision.ceil._*fragment.* Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-17 13:19:01 +00:00
case ir_unop_ceil: {
src_reg tmp = src_reg(this, ir->type);
op[0].negate = !op[0].negate;
emit(RNDD(dst_reg(tmp), op[0]));
tmp.negate = true;
emit(MOV(result_dst, tmp));
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_unop_floor:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
inst = emit(RNDD(result_dst, op[0]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_unop_fract:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
inst = emit(FRC(result_dst, op[0]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_unop_round_even:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(RNDE(result_dst, op[0]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_min:
i965/vs: Refactor min/max handling to share code. v2: Properly use "conditionalmod" pre-Gen6, rather than the incorrectly copy-and-pasted "BRW_CONDITIONAL_G". Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-10-08 18:45:08 +01:00
emit_minmax(BRW_CONDITIONAL_L, result_dst, op[0], op[1]);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_max:
i965/vs: Refactor min/max handling to share code. v2: Properly use "conditionalmod" pre-Gen6, rather than the incorrectly copy-and-pasted "BRW_CONDITIONAL_G". Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-10-08 18:45:08 +01:00
emit_minmax(BRW_CONDITIONAL_G, result_dst, op[0], op[1]);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_pow:
emit_math(SHADER_OPCODE_POW, result_dst, op[0], op[1]);
break;
case ir_unop_bit_not:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
inst = emit(NOT(result_dst, op[0]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_bit_and:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
inst = emit(AND(result_dst, op[0], op[1]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_bit_xor:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
inst = emit(XOR(result_dst, op[0], op[1]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_bit_or:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
inst = emit(OR(result_dst, op[0], op[1]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case ir_binop_lshift:
i965/vs: add support for emitting SHL, SHR, ASR Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-22 03:23:23 +00:00
inst = emit(SHL(result_dst, op[0], op[1]));
i965/vs: Add support for bit-shift operations. Reviewed-by: Chad Versace <chad@chad-versace.us> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-09-27 22:48:56 +01:00
break;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_binop_rshift:
i965/vs: Add support for bit-shift operations. Reviewed-by: Chad Versace <chad@chad-versace.us> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-09-27 22:48:56 +01:00
if (ir->type->base_type == GLSL_TYPE_INT)
i965/vs: add support for emitting SHL, SHR, ASR Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-22 03:23:23 +00:00
inst = emit(ASR(result_dst, op[0], op[1]));
i965/vs: Add support for bit-shift operations. Reviewed-by: Chad Versace <chad@chad-versace.us> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-09-27 22:48:56 +01:00
else
i965/vs: add support for emitting SHL, SHR, ASR Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-22 03:23:23 +00:00
inst = emit(SHR(result_dst, op[0], op[1]));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
i965/vs: Add support for bit instructions. v2: Rebase on LRP addition. Use fix_3src_operand() when emitting BFE and BFI2. Add BFE and BFI2 to is_3src_inst check in brw_vec4_copy_propagation.cpp. Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-04-18 02:57:58 +01:00
case ir_binop_bfm:
emit(BFI1(result_dst, op[0], op[1]));
break;
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
case ir_binop_ubo_load: {
i965/vec4: Add visitor support for nonconst ubo block indexing Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-06-29 01:30:04 +01:00
ir_constant *const_uniform_block = ir->operands[0]->as_constant();
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
ir_constant *const_offset_ir = ir->operands[1]->as_constant();
unsigned const_offset = const_offset_ir ? const_offset_ir->value.u[0] : 0;
i965/vec4: Don't overwrite op[1] when doing a UBO load. Prior to the GLSL CSE pass, all of our testing happened to have a freshly computed temporary in op[1], from the multiply by 16 to get a byte offset. As of CSE you'll get var_refs of a reused value when you've got multiple loads from the same offset. Make a proper temporary for computing our temporary value, to avoid shifting the value farther and farther down. Avoids a regression in gs-float-array-variable-index Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-31 00:09:53 +00:00
src_reg offset;
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
/* Now, load the vector from that offset. */
assert(ir->type->is_vector() || ir->type->is_scalar());
src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
packed_consts.type = result.type;
i965/vec4: Add visitor support for nonconst ubo block indexing Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-06-29 01:30:04 +01:00
src_reg surf_index;
if (const_uniform_block) {
/* The block index is a constant, so just emit the binding table entry
* as an immediate.
*/
surf_index = src_reg(prog_data->base.binding_table.ubo_start +
const_uniform_block->value.u[0]);
} else {
/* The block index is not a constant. Evaluate the index expression
* per-channel and add the base UBO index; the generator will select
* a value from any live channel.
*/
surf_index = src_reg(this, glsl_type::uint_type);
emit(ADD(dst_reg(surf_index), op[0],
src_reg(prog_data->base.binding_table.ubo_start)));
/* Assume this may touch any UBO. It would be nice to provide
* a tighter bound, but the array information is already lowered away.
*/
brw_mark_surface_used(&prog_data->base,
prog_data->base.binding_table.ubo_start +
shader_prog->NumUniformBlocks - 1);
}
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
if (const_offset_ir) {
i965/vs: Always store pull constant offsets in GRFs on Gen8. We need to SEND from a GRF, and we can only obtain those prior to register allocation. This allows us to do pull constant loads without the MRF hack. v2: Reword comments (suggested by Paul). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-12-16 08:02:43 +00:00
if (brw->gen >= 8) {
/* Store the offset in a GRF so we can send-from-GRF. */
offset = src_reg(this, glsl_type::int_type);
emit(MOV(dst_reg(offset), src_reg(const_offset / 16)));
} else {
/* Immediates are fine on older generations since they'll be moved
* to a (potentially fake) MRF at the generator level.
*/
offset = src_reg(const_offset / 16);
}
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
} else {
i965/vec4: Don't overwrite op[1] when doing a UBO load. Prior to the GLSL CSE pass, all of our testing happened to have a freshly computed temporary in op[1], from the multiply by 16 to get a byte offset. As of CSE you'll get var_refs of a reused value when you've got multiple loads from the same offset. Make a proper temporary for computing our temporary value, to avoid shifting the value farther and farther down. Avoids a regression in gs-float-array-variable-index Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-31 00:09:53 +00:00
offset = src_reg(this, glsl_type::uint_type);
emit(SHR(dst_reg(offset), op[1], src_reg(4)));
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
}
i965/vs: Use samplers for UBOs in the VS like we do for non-UBO pulls. Improves performance of a dolphin emulator trace I had laying around by 3.60131% +/- 0.995887% (n=128). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-02-15 00:06:31 +00:00
if (brw->gen >= 7) {
dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
grf_offset.type = offset.type;
emit(MOV(grf_offset, offset));
i965/vec4: Init mlen for several send from GRF instructions. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-03 20:52:37 +00:00
vec4_instruction *pull =
emit(new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
dst_reg(packed_consts),
surf_index,
src_reg(grf_offset)));
pull->mlen = 1;
i965/vs: Use samplers for UBOs in the VS like we do for non-UBO pulls. Improves performance of a dolphin emulator trace I had laying around by 3.60131% +/- 0.995887% (n=128). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-02-15 00:06:31 +00:00
} else {
vec4_instruction *pull =
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
emit(new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD,
i965/vs: Use samplers for UBOs in the VS like we do for non-UBO pulls. Improves performance of a dolphin emulator trace I had laying around by 3.60131% +/- 0.995887% (n=128). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-02-15 00:06:31 +00:00
dst_reg(packed_consts),
surf_index,
offset));
pull->base_mrf = 14;
pull->mlen = 1;
}
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
packed_consts.swizzle = swizzle_for_size(ir->type->vector_elements);
packed_consts.swizzle += BRW_SWIZZLE4(const_offset % 16 / 4,
const_offset % 16 / 4,
const_offset % 16 / 4,
const_offset % 16 / 4);
i965: Use ~0 to represent true on Gen >= 6. total instructions in shared programs: 4292303 -> 4288650 (-0.09%) instructions in affected programs: 299670 -> 296017 (-1.22%) Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-08-09 05:00:31 +01:00
/* UBO bools are any nonzero int. We need to convert them to use the
* value of true stored in ctx->Const.UniformBooleanTrue.
*/
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
if (ir->type->base_type == GLSL_TYPE_BOOL) {
emit(CMP(result_dst, packed_consts, src_reg(0u),
BRW_CONDITIONAL_NZ));
} else {
emit(MOV(result_dst, packed_consts));
}
glsl: Add a "ubo_load" expression type for fetches from UBOs. Drivers will probably want to be able to take UBO references in a shader like: uniform ubo1 { float a; float b; float c; float d; } void main() { gl_FragColor = vec4(a, b, c, d); } and generate a single aligned vec4 load out of the UBO. For intel, this involves recognizing the shared offset of the aligned loads and CSEing them out. Obviously that involves breaking things down to loads from an offset from a particular UBO first. Thus, the driver doesn't want to see variable_ref(ir_variable("a")), and even more so does it not want to see array_ref(record_ref(variable_ref(ir_variable("a")), "field1"), variable_ref(ir_variable("i"))). where a.field1[i] is a row_major matrix. Instead, we're going to make a lowering pass to break UBO references down to expressions that are obvious to codegen, and amenable to merging through CSE. v2: Fix some partial thoughts in the ir_binop comment (review by Kenneth) Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-09 23:52:53 +01:00
break;
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-25 22:55:01 +01:00
}
glsl: Add a "ubo_load" expression type for fetches from UBOs. Drivers will probably want to be able to take UBO references in a shader like: uniform ubo1 { float a; float b; float c; float d; } void main() { gl_FragColor = vec4(a, b, c, d); } and generate a single aligned vec4 load out of the UBO. For intel, this involves recognizing the shared offset of the aligned loads and CSEing them out. Obviously that involves breaking things down to loads from an offset from a particular UBO first. Thus, the driver doesn't want to see variable_ref(ir_variable("a")), and even more so does it not want to see array_ref(record_ref(variable_ref(ir_variable("a")), "field1"), variable_ref(ir_variable("i"))). where a.field1[i] is a row_major matrix. Instead, we're going to make a lowering pass to break UBO references down to expressions that are obvious to codegen, and amenable to merging through CSE. v2: Fix some partial thoughts in the ir_binop comment (review by Kenneth) Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-09 23:52:53 +01:00
i965: Add cases for ir_binop_vector_extract that assert. do_vec_index_to_swizzle() should remove any vector extract operations with a constant index. It's unconditionally called from do_common_optimization(). do_vec_index_to_cond_assign() should remove the rest, and it is unconditionally called from brw_link_shader(). This means that we should never see ir_binop_vector_extract in the backend. Silences compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-05-17 18:33:40 +01:00
case ir_binop_vector_extract:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("should have been lowered by vec_index_to_cond_assign");
i965/vs: Add support for translating ir_triop_fma into MAD. Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-08-02 18:28:16 +01:00
case ir_triop_fma:
op[0] = fix_3src_operand(op[0]);
op[1] = fix_3src_operand(op[1]);
op[2] = fix_3src_operand(op[2]);
/* Note that the instruction's argument order is reversed from GLSL
* and the IR.
*/
emit(MAD(result_dst, op[2], op[1], op[0]));
break;
i965: Add cases for ir_binop_vector_extract that assert. do_vec_index_to_swizzle() should remove any vector extract operations with a constant index. It's unconditionally called from do_common_optimization(). do_vec_index_to_cond_assign() should remove the rest, and it is unconditionally called from brw_link_shader(). This means that we should never see ir_binop_vector_extract in the backend. Silences compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-05-17 18:33:40 +01:00
i965/vs: Assert that ir_triop_lrp was lowered. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-19 23:57:28 +00:00
case ir_triop_lrp:
i965/vec4: Handle ir_triop_lrp on Gen4-5 as well. When the vec4 backend encountered an ir_triop_lrp, it always emitted an actual LRP instruction, which only exists on Gen6+. Gen4-5 used lower_instructions() to decompose ir_triop_lrp at the IR level. Since commit 8d37e9915a3b21 ("glsl: Optimize open-coded lrp into lrp."), we've had an bug where lower_instructions translates ir_triop_lrp into arithmetic, but opt_algebraic reassembles it back into a lrp. To avoid this ordering concern, just handle ir_triop_lrp in the backend. The FS backend already does this, so we may as well do likewise. v2: Add a comment reminding us that we could emit better assembly if we implemented the infrastructure necessary to support using MAC. (Assembly code provided by Eric Anholt). Cc: "10.1" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75253 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Acked-by: Eric Anholt <eric@anholt.net>
2014-02-24 00:29:46 +00:00
emit_lrp(result_dst, op[0], op[1], op[2]);
i965/vs: Assert that ir_triop_lrp was lowered. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-19 23:57:28 +00:00
break;
i965: Add support for ir_triop_csel. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-08-19 18:44:41 +01:00
case ir_triop_csel:
i965/vec4: Generate better code for ir_triop_csel. Previously, we generated an extra CMP instruction: cmp.ge.f0(8) g6<1>D g1<0,4,1>F 0F cmp.nz.f0(8) null g6<4,4,1>D 0D (+f0) sel(8) g5<1>F g1.4<0,4,1>F g2<0,4,1>F The first operand is always a boolean, and we want to predicate the SEL on that. Rather than producing a boolean value and comparing it against zero, we can just produce a condition code in the flag register. Now we generate: cmp.ge.f0(8) null g1<0,4,1>F 0F (+f0) sel(8) g5<1>F g1.4<0,4,1>F g2<0,4,1>F No difference in shader-db. v2: Remember to delete the old code (thanks Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-10-16 02:57:07 +01:00
unreachable("already handled above");
i965: Add support for ir_triop_csel. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-08-19 18:44:41 +01:00
break;
i965/vs: Add support for bit instructions. v2: Rebase on LRP addition. Use fix_3src_operand() when emitting BFE and BFI2. Add BFE and BFI2 to is_3src_inst check in brw_vec4_copy_propagation.cpp. Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-04-18 02:57:58 +01:00
case ir_triop_bfi:
op[0] = fix_3src_operand(op[0]);
op[1] = fix_3src_operand(op[1]);
op[2] = fix_3src_operand(op[2]);
emit(BFI2(result_dst, op[0], op[1], op[2]));
break;
case ir_triop_bitfield_extract:
op[0] = fix_3src_operand(op[0]);
op[1] = fix_3src_operand(op[1]);
op[2] = fix_3src_operand(op[2]);
/* Note that the instruction's argument order is reversed from GLSL
* and the IR.
*/
emit(BFE(result_dst, op[2], op[1], op[0]));
break;
i965: Add cases for ir_triop_vector_insert that assert. brw_link_shader() unconditionally calls lower_vector_insert() with true as the second parameter. This means that both constant and variable indexed expressions will get lowered, so we should never see this in the backend. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-05-17 18:41:27 +01:00
case ir_triop_vector_insert:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("should have been lowered by lower_vector_insert");
i965: Add cases for ir_triop_vector_insert that assert. brw_link_shader() unconditionally calls lower_vector_insert() with true as the second parameter. This means that both constant and variable indexed expressions will get lowered, so we should never see this in the backend. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-05-17 18:41:27 +01:00
i965/vs: Add support for bit instructions. v2: Rebase on LRP addition. Use fix_3src_operand() when emitting BFE and BFI2. Add BFE and BFI2 to is_3src_inst check in brw_vec4_copy_propagation.cpp. Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-04-18 02:57:58 +01:00
case ir_quadop_bitfield_insert:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached: should be handled by "
i965/vs: Add support for bit instructions. v2: Rebase on LRP addition. Use fix_3src_operand() when emitting BFE and BFI2. Add BFE and BFI2 to is_3src_inst check in brw_vec4_copy_propagation.cpp. Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-04-18 02:57:58 +01:00
"bitfield_insert_to_bfm_bfi\n");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
case ir_quadop_vector:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached: should be handled by lower_quadop_vector");
i965/vs/gen7: Emit code for GLSL ES 3.00 pack/unpack operations (v3) FIXME: This patch emits VS code that violates documented hardware restrictions and then relies on undocumented behavior that results from that violation. This patch passes all tests, but should be fixed ASAP to conform to the hardware documentation. v2: Explain undocumented hardware behavior. Improve comments. v3: Use ALU1 helper methods F32TO16() and F16TO32(). [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:44:31 +00:00
case ir_unop_pack_half_2x16:
emit_pack_half_2x16(result_dst, op[0]);
break;
case ir_unop_unpack_half_2x16:
emit_unpack_half_2x16(result_dst, op[0]);
break;
i965/vec4: Optimize unpackUnorm4x8(). Reduces the number of instructions needed to implement unpackUnorm4x8() from 11 -> 4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-03-09 01:29:33 +00:00
case ir_unop_unpack_unorm_4x8:
emit_unpack_unorm_4x8(result_dst, op[0]);
break;
i965/vec4: Optimize unpackSnorm4x8(). Reduces the number of instructions needed to implement unpackSnorm4x8() from 16 -> 6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-03-10 03:22:23 +00:00
case ir_unop_unpack_snorm_4x8:
emit_unpack_snorm_4x8(result_dst, op[0]);
break;
i965/vec4: Optimize packUnorm4x8(). Reduces the number of instructions needed to implement packUnorm4x8() from 11 -> 6.
2014-03-10 20:27:46 +00:00
case ir_unop_pack_unorm_4x8:
emit_pack_unorm_4x8(result_dst, op[0]);
break;
i965: Assert that the 4x8 pack/unpack operations have been lowered Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-01-22 01:50:41 +00:00
case ir_unop_pack_snorm_4x8:
i965/vec4: Optimize packSnorm4x8(). Reduces the number of instructions needed to implement packSnorm4x8() from 13 -> 7.
2014-03-10 21:11:05 +00:00
emit_pack_snorm_4x8(result_dst, op[0]);
break;
case ir_unop_pack_snorm_2x16:
i965/vs/gen7: Emit code for GLSL ES 3.00 pack/unpack operations (v3) FIXME: This patch emits VS code that violates documented hardware restrictions and then relies on undocumented behavior that results from that violation. This patch passes all tests, but should be fixed ASAP to conform to the hardware documentation. v2: Explain undocumented hardware behavior. Improve comments. v3: Use ALU1 helper methods F32TO16() and F16TO32(). [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:44:31 +00:00
case ir_unop_pack_unorm_2x16:
case ir_unop_unpack_snorm_2x16:
case ir_unop_unpack_unorm_2x16:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached: should be handled by lower_packing_builtins");
i965/vs/gen7: Emit code for GLSL ES 3.00 pack/unpack operations (v3) FIXME: This patch emits VS code that violates documented hardware restrictions and then relies on undocumented behavior that results from that violation. This patch passes all tests, but should be fixed ASAP to conform to the hardware documentation. v2: Explain undocumented hardware behavior. Improve comments. v3: Use ALU1 helper methods F32TO16() and F16TO32(). [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:44:31 +00:00
case ir_unop_unpack_half_2x16_split_x:
case ir_unop_unpack_half_2x16_split_y:
case ir_binop_pack_half_2x16_split:
i965/vec4: Silence warnings about unhandled interpolation ops Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-07-13 00:13:18 +01:00
case ir_unop_interpolate_at_centroid:
case ir_binop_interpolate_at_sample:
case ir_binop_interpolate_at_offset:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached: should not occur in vertex shader");
glsl: Add support for ldexp. v2: Drop frexp. Rebase on builtins rewrite. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-22 21:31:18 +01:00
case ir_binop_ldexp:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached: should be handled by ldexp_to_arith()");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
}
void
vec4_visitor::visit(ir_swizzle *ir)
{
src_reg src;
int i = 0;
int swizzle[4];
/* Note that this is only swizzles in expressions, not those on the left
* hand side of an assignment, which do write masking. See ir_assignment
* for that.
*/
ir->val->accept(this);
src = this->result;
assert(src.file != BAD_FILE);
i965/vs: Fix ir_swizzle handling. I decided to refactor it a bit in adapting ir_to_mesa.cpp code, and mangled it. Fixes glsl-vs-cross-2.
2011-08-06 00:37:18 +01:00
for (i = 0; i < ir->type->vector_elements; i++) {
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
switch (i) {
case 0:
swizzle[i] = BRW_GET_SWZ(src.swizzle, ir->mask.x);
break;
case 1:
swizzle[i] = BRW_GET_SWZ(src.swizzle, ir->mask.y);
break;
case 2:
swizzle[i] = BRW_GET_SWZ(src.swizzle, ir->mask.z);
break;
case 3:
swizzle[i] = BRW_GET_SWZ(src.swizzle, ir->mask.w);
break;
}
}
for (; i < 4; i++) {
/* Replicate the last channel out. */
swizzle[i] = swizzle[ir->type->vector_elements - 1];
}
src.swizzle = BRW_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
this->result = src;
}
void
vec4_visitor::visit(ir_dereference_variable *ir)
{
i965/vs: Use an appropriate swizzle on src regs from variables. Fixes glsl-vs-if-bool.
2011-08-06 03:29:41 +01:00
const struct glsl_type *type = ir->type;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
dst_reg *reg = variable_storage(ir->var);
if (!reg) {
fail("Failed to find variable storage for %s\n", ir->var->name);
this->result = src_reg(brw_null_reg());
return;
}
this->result = src_reg(*reg);
i965/vs: Use an appropriate swizzle on src regs from variables. Fixes glsl-vs-if-bool.
2011-08-06 03:29:41 +01:00
i965: Fix swizzles for system values such as gl_InstanceID. visit(ir_variable *) sets dst_reg::writemask to the appropriate channel for system values. Unfortunately, visit(ir_dereference_variable *) then calls swizzle_for_size, which for a float, sets the swizzle to .x. This works for gl_VertexID, since we store it in the .x component (see brw_draw_upload.c:732 - VID), but fails for gl_InstanceID (IID) since we store it in the .y channel. To fix this, avoid calling swizzle_for_size on ir_var_system_values. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-02-09 00:59:39 +00:00
/* System values get their swizzle from the dst_reg writemask */
glsl: move variables in to ir_variable::data, part I This patch moves following bitfields in to the data structure: used, assigned, how_declared, mode, interpolation, origin_upper_left, pixel_center_integer Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-12 11:51:01 +00:00
if (ir->var->data.mode == ir_var_system_value)
i965: Fix swizzles for system values such as gl_InstanceID. visit(ir_variable *) sets dst_reg::writemask to the appropriate channel for system values. Unfortunately, visit(ir_dereference_variable *) then calls swizzle_for_size, which for a float, sets the swizzle to .x. This works for gl_VertexID, since we store it in the .x component (see brw_draw_upload.c:732 - VID), but fails for gl_InstanceID (IID) since we store it in the .y channel. To fix this, avoid calling swizzle_for_size on ir_var_system_values. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-02-09 00:59:39 +00:00
return;
i965/vs: Use an appropriate swizzle on src regs from variables. Fixes glsl-vs-if-bool.
2011-08-06 03:29:41 +01:00
if (type->is_scalar() || type->is_vector() || type->is_matrix())
this->result.swizzle = swizzle_for_size(type->vector_elements);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Generalize computation of array strides in preparation for GS. Geometry shader inputs are arrays, but they use an unusual array layout: instead of all array elements for a given geometry shader input being stored consecutively, all geometry shader inputs are interleaved into one giant array. As a result, the array stride we use to access geometry shader inputs must be equal to the size of the input VUE, rather than the size of the array element. This patch introduces a new virtual function, vec4_visitor::compute_array_stride(), which will allow geometry shader compilation to specialize the computation of array stride to account for the unusual layout of geometry shader input arrays. It also renames the local variable that the ir_dereference_array visitor uses to store the stride, to avoid confusion. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-22 18:26:34 +00:00
int
vec4_visitor::compute_array_stride(ir_dereference_array *ir)
{
/* Under normal circumstances array elements are stored consecutively, so
* the stride is equal to the size of the array element.
*/
return type_size(ir->type);
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
void
vec4_visitor::visit(ir_dereference_array *ir)
{
ir_constant *constant_index;
src_reg src;
i965/vs: Generalize computation of array strides in preparation for GS. Geometry shader inputs are arrays, but they use an unusual array layout: instead of all array elements for a given geometry shader input being stored consecutively, all geometry shader inputs are interleaved into one giant array. As a result, the array stride we use to access geometry shader inputs must be equal to the size of the input VUE, rather than the size of the array element. This patch introduces a new virtual function, vec4_visitor::compute_array_stride(), which will allow geometry shader compilation to specialize the computation of array stride to account for the unusual layout of geometry shader input arrays. It also renames the local variable that the ir_dereference_array visitor uses to store the stride, to avoid confusion. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-22 18:26:34 +00:00
int array_stride = compute_array_stride(ir);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
constant_index = ir->array_index->constant_expression_value();
ir->array->accept(this);
src = this->result;
if (constant_index) {
i965/vs: Generalize computation of array strides in preparation for GS. Geometry shader inputs are arrays, but they use an unusual array layout: instead of all array elements for a given geometry shader input being stored consecutively, all geometry shader inputs are interleaved into one giant array. As a result, the array stride we use to access geometry shader inputs must be equal to the size of the input VUE, rather than the size of the array element. This patch introduces a new virtual function, vec4_visitor::compute_array_stride(), which will allow geometry shader compilation to specialize the computation of array stride to account for the unusual layout of geometry shader input arrays. It also renames the local variable that the ir_dereference_array visitor uses to store the stride, to avoid confusion. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-22 18:26:34 +00:00
src.reg_offset += constant_index->value.i[0] * array_stride;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
} else {
/* Variable index array dereference. It eats the "vec4" of the
* base of the array and an index that offsets the Mesa register
* index.
*/
ir->array_index->accept(this);
src_reg index_reg;
i965/vs: Generalize computation of array strides in preparation for GS. Geometry shader inputs are arrays, but they use an unusual array layout: instead of all array elements for a given geometry shader input being stored consecutively, all geometry shader inputs are interleaved into one giant array. As a result, the array stride we use to access geometry shader inputs must be equal to the size of the input VUE, rather than the size of the array element. This patch introduces a new virtual function, vec4_visitor::compute_array_stride(), which will allow geometry shader compilation to specialize the computation of array stride to account for the unusual layout of geometry shader input arrays. It also renames the local variable that the ir_dereference_array visitor uses to store the stride, to avoid confusion. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-22 18:26:34 +00:00
if (array_stride == 1) {
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
index_reg = this->result;
} else {
i965/vs: Track the variable index of array accesses. This isn't used currently, as we lower all array accesses.
2011-08-07 18:59:39 +01:00
index_reg = src_reg(this, glsl_type::int_type);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: Generalize computation of array strides in preparation for GS. Geometry shader inputs are arrays, but they use an unusual array layout: instead of all array elements for a given geometry shader input being stored consecutively, all geometry shader inputs are interleaved into one giant array. As a result, the array stride we use to access geometry shader inputs must be equal to the size of the input VUE, rather than the size of the array element. This patch introduces a new virtual function, vec4_visitor::compute_array_stride(), which will allow geometry shader compilation to specialize the computation of array stride to account for the unusual layout of geometry shader input arrays. It also renames the local variable that the ir_dereference_array visitor uses to store the stride, to avoid confusion. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-22 18:26:34 +00:00
emit(MUL(dst_reg(index_reg), this->result, src_reg(array_stride)));
i965/vs: Track the variable index of array accesses. This isn't used currently, as we lower all array accesses.
2011-08-07 18:59:39 +01:00
}
if (src.reladdr) {
src_reg temp = src_reg(this, glsl_type::int_type);
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(ADD(dst_reg(temp), *src.reladdr, index_reg));
i965/vs: Track the variable index of array accesses. This isn't used currently, as we lower all array accesses.
2011-08-07 18:59:39 +01:00
index_reg = temp;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
src.reladdr = ralloc(mem_ctx, src_reg);
memcpy(src.reladdr, &index_reg, sizeof(index_reg));
}
/* If the type is smaller than a vec4, replicate the last channel out. */
i965/vs: Fix up swizzle for dereference_array of matrices. Fixes assertion failure in piglit: vs-mat2-struct-assignment.shader_test vs-mat2-array-assignment.shader_test Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-10 23:38:11 +01:00
if (ir->type->is_scalar() || ir->type->is_vector() || ir->type->is_matrix())
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
src.swizzle = swizzle_for_size(ir->type->vector_elements);
else
src.swizzle = BRW_SWIZZLE_NOOP;
i965/vs: Fix the types of array/struct dereferences. Fixes glsl-vs-arrays-3.
2011-08-06 03:38:44 +01:00
src.type = brw_type_for_base_type(ir->type);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
this->result = src;
}
void
vec4_visitor::visit(ir_dereference_record *ir)
{
unsigned int i;
const glsl_type *struct_type = ir->record->type;
int offset = 0;
ir->record->accept(this);
for (i = 0; i < struct_type->length; i++) {
if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
break;
offset += type_size(struct_type->fields.structure[i].type);
}
/* If the type is smaller than a vec4, replicate the last channel out. */
i965/vs: Fix up swizzle for dereference_array of matrices. Fixes assertion failure in piglit: vs-mat2-struct-assignment.shader_test vs-mat2-array-assignment.shader_test Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-10 23:38:11 +01:00
if (ir->type->is_scalar() || ir->type->is_vector() || ir->type->is_matrix())
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
else
this->result.swizzle = BRW_SWIZZLE_NOOP;
i965/vs: Fix the types of array/struct dereferences. Fixes glsl-vs-arrays-3.
2011-08-06 03:38:44 +01:00
this->result.type = brw_type_for_base_type(ir->type);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
this->result.reg_offset += offset;
}
/**
* We want to be careful in assignment setup to hit the actual storage
* instead of potentially using a temporary like we might with the
* ir_dereference handler.
*/
static dst_reg
get_assignment_lhs(ir_dereference *ir, vec4_visitor *v)
{
/* The LHS must be a dereference. If the LHS is a variable indexed array
* access of a vector, it must be separated into a series conditional moves
* before reaching this point (see ir_vec_index_to_cond_assign).
*/
assert(ir->as_dereference());
ir_dereference_array *deref_array = ir->as_dereference_array();
if (deref_array) {
assert(!deref_array->array->type->is_vector());
}
/* Use the rvalue deref handler for the most part. We'll ignore
* swizzles in it and write swizzles using writemask, though.
*/
ir->accept(v);
return dst_reg(v->result);
}
void
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
vec4_visitor::emit_block_move(dst_reg *dst, src_reg *src,
i965: Make a brw_predicate enum. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-06-30 01:58:59 +01:00
const struct glsl_type *type,
enum brw_predicate predicate)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
if (type->base_type == GLSL_TYPE_STRUCT) {
for (unsigned int i = 0; i < type->length; i++) {
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
emit_block_move(dst, src, type->fields.structure[i].type, predicate);
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
}
return;
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
if (type->is_array()) {
for (unsigned int i = 0; i < type->length; i++) {
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
emit_block_move(dst, src, type->fields.array, predicate);
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
}
return;
i965/vs: Don't forget to set up assignment condition code for arrays/structs. Fixes vs-uniform-array-mat2-index-col-rd.
2011-08-06 04:26:48 +01:00
}
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
if (type->is_matrix()) {
const struct glsl_type *vec_type;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
vec_type = glsl_type::get_instance(GLSL_TYPE_FLOAT,
type->vector_elements, 1);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
for (int i = 0; i < type->matrix_columns; i++) {
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
emit_block_move(dst, src, vec_type, predicate);
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
}
return;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
assert(type->is_scalar() || type->is_vector());
dst->type = brw_type_for_base_type(type);
src->type = dst->type;
dst->writemask = (1 << type->vector_elements) - 1;
src->swizzle = swizzle_for_size(type->vector_elements);
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
vec4_instruction *inst = emit(MOV(*dst, *src));
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
inst->predicate = predicate;
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
dst->reg_offset++;
src->reg_offset++;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Avoid generating a MOV for most ir_assignment handling. Removes an average of 11.5% of instructions in 54% of vertex shaders in shader-db.
2011-08-11 16:09:10 +01:00
/* If the RHS processing resulted in an instruction generating a
* temporary value, and it would be easy to rewrite the instruction to
* generate its result right into the LHS instead, do so. This ends
* up reliably removing instructions where it can be tricky to do so
* later without real UD chain information.
*/
bool
vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
dst_reg dst,
src_reg src,
vec4_instruction *pre_rhs_inst,
vec4_instruction *last_rhs_inst)
{
/* This could be supported, but it would take more smarts. */
if (ir->condition)
return false;
if (pre_rhs_inst == last_rhs_inst)
return false; /* No instructions generated to work with. */
/* Make sure the last instruction generated our source reg. */
if (src.file != GRF ||
src.file != last_rhs_inst->dst.file ||
src.reg != last_rhs_inst->dst.reg ||
src.reg_offset != last_rhs_inst->dst.reg_offset ||
src.reladdr ||
src.abs ||
src.negate ||
last_rhs_inst->predicate != BRW_PREDICATE_NONE)
return false;
/* Check that that last instruction fully initialized the channels
* we want to use, in the order we want to use them. We could
* potentially reswizzle the operands of many instructions so that
* we could handle out of order channels, but don't yet.
*/
i965: silence signed/unsigned comparison warning Reviewed-by: Paul Berry <stereotype441@gmail.com>
2011-10-15 23:36:11 +01:00
for (unsigned i = 0; i < 4; i++) {
i965/vs: Avoid generating a MOV for most ir_assignment handling. Removes an average of 11.5% of instructions in 54% of vertex shaders in shader-db.
2011-08-11 16:09:10 +01:00
if (dst.writemask & (1 << i)) {
if (!(last_rhs_inst->dst.writemask & (1 << i)))
return false;
if (BRW_GET_SWZ(src.swizzle, i) != i)
return false;
}
}
/* Success! Rewrite the instruction. */
last_rhs_inst->dst.file = dst.file;
last_rhs_inst->dst.reg = dst.reg;
last_rhs_inst->dst.reg_offset = dst.reg_offset;
last_rhs_inst->dst.reladdr = dst.reladdr;
last_rhs_inst->dst.writemask &= dst.writemask;
return true;
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
void
vec4_visitor::visit(ir_assignment *ir)
{
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
dst_reg dst = get_assignment_lhs(ir->lhs, this);
i965: Make a brw_predicate enum. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-06-30 01:58:59 +01:00
enum brw_predicate predicate = BRW_PREDICATE_NONE;
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
if (!ir->lhs->type->is_scalar() &&
!ir->lhs->type->is_vector()) {
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
ir->rhs->accept(this);
src_reg src = this->result;
if (ir->condition) {
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
emit_bool_to_cond_code(ir->condition, &predicate);
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
2011-08-06 04:46:03 +01:00
}
i965/vs: Fix bogus assertion in emit_block_move() i965 processes assignments of whole structures using vec4_visitor::emit_block_move, a recursive function which visits each element of a structure or array (to arbitrary nesting depth) and copies it from the source to the destination. Then it increments the source and destination register numbers so that further recursive invocations will copy the rest of the structure. In addition, it sets the swizzle field for the source register to an appropriate value of swizzle_for_size(...) for the size of each element being copied, so that later optimization passes won't be fooled into thinking that unused vector elements are live. This all works fine. However, emit_block_move also contains an assertion to verify, before setting the swizzle field for the source register, that the source register doesn't already contain a nontrivial swizzle. The intention is to make sure that the caller of emit_block_move hasn't already done some swizzling of the data before the call, which emit_block_move would then counteract when it overwrites the swizzle field. But the assertion is at the lowest level of nesting of emit_block_move, which means that after the first element is copied, instead of checking the swizzle field set by the caller, it checks the swizzle field used when moving the previous element. That means that if the structure contains elements of different vector sizes (which therefore require different swizzles), the assertion will erroneously fire. This patch moves the assertion from emit_block_move to the calling function, vec4_visitor::visit(ir_assignment *). Since the caller is non-recursive, the assertion will only happen once, and won't be fooled by emit_block_move's modification of the swizzle field. This patch also reverts commit fe006a7 (i965/vs: Fix swizzle related assertion), which attempted to fix the bug by making the assertion more lenient, but only worked properly for structures, arrays, and matrices in which each constituent vector is the same size. This fixes the problem described in comment 9 of https://bugs.freedesktop.org/show_bug.cgi?id=40865. Unfortunately, it doesn't fix the whole bug, since the test in question is also failing due to lack of register spilling support in the VS. Fixes piglit test vs-assign-varied-struct. No piglit regressions on Sandy Bridge. This is a candidate for the 8.0 release branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40865#c9 Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-01-19 23:49:43 +00:00
/* emit_block_move doesn't account for swizzles in the source register.
* This should be ok, since the source register is a structure or an
* array, and those can't be swizzled. But double-check to be sure.
*/
assert(src.swizzle ==
(ir->rhs->type->is_matrix()
? swizzle_for_size(ir->rhs->type->vector_elements)
: BRW_SWIZZLE_NOOP));
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
emit_block_move(&dst, &src, ir->rhs->type, predicate);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
return;
}
/* Now we're down to just a scalar/vector with writemasks. */
int i;
i965/vs: Avoid generating a MOV for most ir_assignment handling. Removes an average of 11.5% of instructions in 54% of vertex shaders in shader-db.
2011-08-11 16:09:10 +01:00
vec4_instruction *pre_rhs_inst, *last_rhs_inst;
pre_rhs_inst = (vec4_instruction *)this->instructions.get_tail();
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
ir->rhs->accept(this);
i965/vs: Avoid generating a MOV for most ir_assignment handling. Removes an average of 11.5% of instructions in 54% of vertex shaders in shader-db.
2011-08-11 16:09:10 +01:00
last_rhs_inst = (vec4_instruction *)this->instructions.get_tail();
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
src_reg src = this->result;
int swizzles[4];
int first_enabled_chan = 0;
int src_chan = 0;
i965/vs: Allow scalar values in assignments, too. Fixes glsl-vs-all-02 and many other tests.
2011-08-06 00:31:30 +01:00
assert(ir->lhs->type->is_vector() ||
ir->lhs->type->is_scalar());
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
dst.writemask = ir->write_mask;
for (int i = 0; i < 4; i++) {
if (dst.writemask & (1 << i)) {
first_enabled_chan = BRW_GET_SWZ(src.swizzle, i);
break;
}
}
/* Swizzle a small RHS vector into the channels being written.
*
* glsl ir treats write_mask as dictating how many channels are
* present on the RHS while in our instructions we need to make
* those channels appear in the slots of the vec4 they're written to.
*/
for (int i = 0; i < 4; i++) {
if (dst.writemask & (1 << i))
swizzles[i] = BRW_GET_SWZ(src.swizzle, src_chan++);
else
swizzles[i] = first_enabled_chan;
}
src.swizzle = BRW_SWIZZLE4(swizzles[0], swizzles[1],
swizzles[2], swizzles[3]);
i965/vs: Avoid generating a MOV for most ir_assignment handling. Removes an average of 11.5% of instructions in 54% of vertex shaders in shader-db.
2011-08-11 16:09:10 +01:00
if (try_rewrite_rhs_to_dst(ir, dst, src, pre_rhs_inst, last_rhs_inst)) {
return;
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
if (ir->condition) {
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
emit_bool_to_cond_code(ir->condition, &predicate);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
for (i = 0; i < type_size(ir->lhs->type); i++) {
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
vec4_instruction *inst = emit(MOV(dst, src));
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
inst->predicate = predicate;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
dst.reg_offset++;
src.reg_offset++;
}
}
void
i965/vs: Avoid generating extra moves when setting up large ir_constants. We were also screwing up the types in the process, and just not emitting moves was easier.
2011-08-06 05:22:36 +01:00
vec4_visitor::emit_constant_values(dst_reg *dst, ir_constant *ir)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
if (ir->type->base_type == GLSL_TYPE_STRUCT) {
i965: Use typed foreach_in_list instead of foreach_list. Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-24 23:53:19 +01:00
foreach_in_list(ir_constant, field_value, &ir->components) {
i965/vs: Avoid generating extra moves when setting up large ir_constants. We were also screwing up the types in the process, and just not emitting moves was easier.
2011-08-06 05:22:36 +01:00
emit_constant_values(dst, field_value);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
return;
}
if (ir->type->is_array()) {
for (unsigned int i = 0; i < ir->type->length; i++) {
i965/vs: Avoid generating extra moves when setting up large ir_constants. We were also screwing up the types in the process, and just not emitting moves was easier.
2011-08-06 05:22:36 +01:00
emit_constant_values(dst, ir->array_elements[i]);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
return;
}
if (ir->type->is_matrix()) {
for (int i = 0; i < ir->type->matrix_columns; i++) {
i965/vs: Try to emit more components of constant vectors at once. We were naively emitting each component at a time, even if we were emitting the same value to multiple channels. Improves on a codegen regression from the old VS to the new VS on some unigine shaders (because we emit constant vecs/matrices as immediates instead of loading them as push constants, so we had over 4x the instructions for using them). shader-db results: Total instructions: 58594 -> 58540 11/870 programs affected (1.3%) 765 -> 711 instructions in affected programs (7.1% reduction)
2012-01-06 18:20:09 +00:00
float *vec = &ir->value.f[i * ir->type->vector_elements];
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
for (int j = 0; j < ir->type->vector_elements; j++) {
i965/vs: Avoid generating extra moves when setting up large ir_constants. We were also screwing up the types in the process, and just not emitting moves was easier.
2011-08-06 05:22:36 +01:00
dst->writemask = 1 << j;
dst->type = BRW_REGISTER_TYPE_F;
i965/vs: Try to emit more components of constant vectors at once. We were naively emitting each component at a time, even if we were emitting the same value to multiple channels. Improves on a codegen regression from the old VS to the new VS on some unigine shaders (because we emit constant vecs/matrices as immediates instead of loading them as push constants, so we had over 4x the instructions for using them). shader-db results: Total instructions: 58594 -> 58540 11/870 programs affected (1.3%) 765 -> 711 instructions in affected programs (7.1% reduction)
2012-01-06 18:20:09 +00:00
emit(MOV(*dst, src_reg(vec[j])));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Avoid generating extra moves when setting up large ir_constants. We were also screwing up the types in the process, and just not emitting moves was easier.
2011-08-06 05:22:36 +01:00
dst->reg_offset++;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
return;
}
i965/vs: Try to emit more components of constant vectors at once. We were naively emitting each component at a time, even if we were emitting the same value to multiple channels. Improves on a codegen regression from the old VS to the new VS on some unigine shaders (because we emit constant vecs/matrices as immediates instead of loading them as push constants, so we had over 4x the instructions for using them). shader-db results: Total instructions: 58594 -> 58540 11/870 programs affected (1.3%) 765 -> 711 instructions in affected programs (7.1% reduction)
2012-01-06 18:20:09 +00:00
int remaining_writemask = (1 << ir->type->vector_elements) - 1;
i965/vs: Fix constant vector construction. Fixes some issues noticed in glsl-vs-all-01.
2011-08-06 00:18:00 +01:00
for (int i = 0; i < ir->type->vector_elements; i++) {
i965/vs: Try to emit more components of constant vectors at once. We were naively emitting each component at a time, even if we were emitting the same value to multiple channels. Improves on a codegen regression from the old VS to the new VS on some unigine shaders (because we emit constant vecs/matrices as immediates instead of loading them as push constants, so we had over 4x the instructions for using them). shader-db results: Total instructions: 58594 -> 58540 11/870 programs affected (1.3%) 765 -> 711 instructions in affected programs (7.1% reduction)
2012-01-06 18:20:09 +00:00
if (!(remaining_writemask & (1 << i)))
continue;
i965/vs: Avoid generating extra moves when setting up large ir_constants. We were also screwing up the types in the process, and just not emitting moves was easier.
2011-08-06 05:22:36 +01:00
dst->writemask = 1 << i;
dst->type = brw_type_for_base_type(ir->type);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: Try to emit more components of constant vectors at once. We were naively emitting each component at a time, even if we were emitting the same value to multiple channels. Improves on a codegen regression from the old VS to the new VS on some unigine shaders (because we emit constant vecs/matrices as immediates instead of loading them as push constants, so we had over 4x the instructions for using them). shader-db results: Total instructions: 58594 -> 58540 11/870 programs affected (1.3%) 765 -> 711 instructions in affected programs (7.1% reduction)
2012-01-06 18:20:09 +00:00
/* Find other components that match the one we're about to
* write. Emits fewer instructions for things like vec4(0.5,
* 1.5, 1.5, 1.5).
*/
for (int j = i + 1; j < ir->type->vector_elements; j++) {
if (ir->type->base_type == GLSL_TYPE_BOOL) {
if (ir->value.b[i] == ir->value.b[j])
dst->writemask |= (1 << j);
} else {
/* u, i, and f storage all line up, so no need for a
* switch case for comparing each type.
*/
if (ir->value.u[i] == ir->value.u[j])
dst->writemask |= (1 << j);
}
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
switch (ir->type->base_type) {
case GLSL_TYPE_FLOAT:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(MOV(*dst, src_reg(ir->value.f[i])));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case GLSL_TYPE_INT:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(MOV(*dst, src_reg(ir->value.i[i])));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case GLSL_TYPE_UINT:
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(MOV(*dst, src_reg(ir->value.u[i])));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
case GLSL_TYPE_BOOL:
i965: Use UniformBooleanTrue value for boolean literal true. Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-08-09 03:44:22 +01:00
emit(MOV(*dst,
i965: Change the type of booleans to D. This is a revert of commit 4656c14e ("i965/fs: Change the type of booleans to UD and emit correct immediates") plus some small additional fixes, like casting ctx->Const.UniformBooleanTrue to int and changing UD to D in the ir_unop_b2f cases. Note that it's safe to leave 0x3f800000 as UD and as a literal it's more recognizable than 1065353216. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:30:27 +00:00
src_reg(ir->value.b[i] != 0 ? (int)ctx->Const.UniformBooleanTrue
: 0)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
break;
default:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("Non-float/uint/int/bool constant");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Try to emit more components of constant vectors at once. We were naively emitting each component at a time, even if we were emitting the same value to multiple channels. Improves on a codegen regression from the old VS to the new VS on some unigine shaders (because we emit constant vecs/matrices as immediates instead of loading them as push constants, so we had over 4x the instructions for using them). shader-db results: Total instructions: 58594 -> 58540 11/870 programs affected (1.3%) 765 -> 711 instructions in affected programs (7.1% reduction)
2012-01-06 18:20:09 +00:00
remaining_writemask &= ~dst->writemask;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Avoid generating extra moves when setting up large ir_constants. We were also screwing up the types in the process, and just not emitting moves was easier.
2011-08-06 05:22:36 +01:00
dst->reg_offset++;
}
void
vec4_visitor::visit(ir_constant *ir)
{
dst_reg dst = dst_reg(this, ir->type);
this->result = src_reg(dst);
emit_constant_values(&dst, ir);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/gen7: Handle atomic instructions from the VEC4 back-end. This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. v2: Represent atomics as GLSL intrinsics. Add support for variably indexed atomic counter arrays. v3: Add comment on why we don't need to assign uniform storage for atomic counters. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-26 00:31:35 +01:00
void
vec4_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
{
ir_dereference *deref = static_cast<ir_dereference *>(
ir->actual_parameters.get_head());
ir_variable *location = deref->variable_referenced();
unsigned surf_index = (prog_data->base.binding_table.abo_start +
glsl: Eliminate ir_variable::data.atomic.buffer_index Just use ir_variable::data.binding... because that's the where the binding is stored for everything else that can use layout(binding=). Valgrind massif results for a trimmed apitrace of dota2: n time(i) total(B) useful-heap(B) extra-heap(B) stacks(B) Before (32-bit): 50 40,564,927,443 69,185,408 63,683,871 5,501,537 0 After (32-bit): 74 40,580,119,657 69,186,544 63,506,327 5,680,217 0 Before (64-bit): 59 36,822,048,449 96,526,888 89,113,000 7,413,888 0 After (64-bit): 89 36,822,971,897 96,526,616 88,735,296 7,791,320 0 A real savings of 173KiB on 32-bit and 368KiB on 64-bit. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-14 23:48:36 +01:00
location->data.binding);
i965/gen7: Handle atomic instructions from the VEC4 back-end. This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. v2: Represent atomics as GLSL intrinsics. Add support for variably indexed atomic counter arrays. v3: Add comment on why we don't need to assign uniform storage for atomic counters. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-26 00:31:35 +01:00
/* Calculate the surface offset */
src_reg offset(this, glsl_type::uint_type);
ir_dereference_array *deref_array = deref->as_dereference_array();
if (deref_array) {
deref_array->array_index->accept(this);
src_reg tmp(this, glsl_type::uint_type);
emit(MUL(dst_reg(tmp), this->result, ATOMIC_COUNTER_SIZE));
glsl: move variables in to ir_variable::data, part II This patch moves following bitfields and variables to the data structure: explicit_location, explicit_index, explicit_binding, has_initializer, is_unmatched_generic_inout, location_frac, from_named_ifc_block_nonarray, from_named_ifc_block_array, depth_layout, location, index, binding, max_array_access, atomic Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-12 13:08:59 +00:00
emit(ADD(dst_reg(offset), tmp, location->data.atomic.offset));
i965/gen7: Handle atomic instructions from the VEC4 back-end. This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. v2: Represent atomics as GLSL intrinsics. Add support for variably indexed atomic counter arrays. v3: Add comment on why we don't need to assign uniform storage for atomic counters. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-26 00:31:35 +01:00
} else {
glsl: move variables in to ir_variable::data, part II This patch moves following bitfields and variables to the data structure: explicit_location, explicit_index, explicit_binding, has_initializer, is_unmatched_generic_inout, location_frac, from_named_ifc_block_nonarray, from_named_ifc_block_array, depth_layout, location, index, binding, max_array_access, atomic Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-12 13:08:59 +00:00
offset = location->data.atomic.offset;
i965/gen7: Handle atomic instructions from the VEC4 back-end. This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. v2: Represent atomics as GLSL intrinsics. Add support for variably indexed atomic counter arrays. v3: Add comment on why we don't need to assign uniform storage for atomic counters. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-26 00:31:35 +01:00
}
/* Emit the appropriate machine instruction */
const char *callee = ir->callee->function_name();
dst_reg dst = get_assignment_lhs(ir->return_deref, this);
if (!strcmp("__intrinsic_atomic_read", callee)) {
emit_untyped_surface_read(surf_index, dst, offset);
} else if (!strcmp("__intrinsic_atomic_increment", callee)) {
emit_untyped_atomic(BRW_AOP_INC, surf_index, dst, offset,
src_reg(), src_reg());
} else if (!strcmp("__intrinsic_atomic_predecrement", callee)) {
emit_untyped_atomic(BRW_AOP_PREDEC, surf_index, dst, offset,
src_reg(), src_reg());
}
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
void
vec4_visitor::visit(ir_call *ir)
{
i965/gen7: Handle atomic instructions from the VEC4 back-end. This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. v2: Represent atomics as GLSL intrinsics. Add support for variably indexed atomic counter arrays. v3: Add comment on why we don't need to assign uniform storage for atomic counters. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-26 00:31:35 +01:00
const char *callee = ir->callee->function_name();
if (!strcmp("__intrinsic_atomic_read", callee) ||
!strcmp("__intrinsic_atomic_increment", callee) ||
!strcmp("__intrinsic_atomic_predecrement", callee)) {
visit_atomic_counter_intrinsic(ir);
} else {
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("Unsupported intrinsic.");
i965/gen7: Handle atomic instructions from the VEC4 back-end. This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. v2: Represent atomics as GLSL intrinsics. Add support for variably indexed atomic counter arrays. v3: Add comment on why we don't need to assign uniform storage for atomic counters. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-26 00:31:35 +01:00
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Sample from MCS surface when required Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-30 00:49:50 +00:00
src_reg
i965/vec4: Add support for nonconst sampler indexing in VS visitor V2: Set force_writemask_all on ADD; this *is* necessary in the VS case too. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-09 11:08:11 +01:00
vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler)
i965/vs: Sample from MCS surface when required Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-30 00:49:50 +00:00
{
i965/vec4: Pass dst register to the vec4_instruction constructor. So regs_written gets initialized with a sensible value. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-03 20:53:17 +00:00
vec4_instruction *inst =
new(mem_ctx) vec4_instruction(SHADER_OPCODE_TXF_MCS,
dst_reg(this, glsl_type::uvec4_type));
i965/vs: Sample from MCS surface when required Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-30 00:49:50 +00:00
inst->base_mrf = 2;
inst->mlen = 1;
i965/vec4: Add support for nonconst sampler indexing in VS visitor V2: Set force_writemask_all on ADD; this *is* necessary in the VS case too. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-09 11:08:11 +01:00
inst->src[1] = sampler;
i965/vec4: Pass sampler index in src1 for texture ops Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-04 08:37:58 +01:00
i965/vs: Sample from MCS surface when required Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-30 00:49:50 +00:00
/* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
int param_base = inst->base_mrf;
int coord_mask = (1 << ir->coordinate->type->vector_elements) - 1;
int zero_mask = 0xf & ~coord_mask;
emit(MOV(dst_reg(MRF, param_base, ir->coordinate->type, coord_mask),
coordinate));
emit(MOV(dst_reg(MRF, param_base, ir->coordinate->type, zero_mask),
src_reg(0)));
emit(inst);
return src_reg(inst->dst);
}
i965/vec4: Add support for nonconst sampler indexing in VS visitor V2: Set force_writemask_all on ADD; this *is* necessary in the VS case too. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-09 11:08:11 +01:00
static bool
is_high_sampler(struct brw_context *brw, src_reg sampler)
{
if (brw->gen < 8 && !brw->is_haswell)
return false;
return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
void
vec4_visitor::visit(ir_texture *ir)
{
i965/vec4: Pass sampler index in src1 for texture ops Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-04 08:37:58 +01:00
uint32_t sampler =
i965/vs: Make type of vec4_visitor::vp more generic. The vec4_visitor functions don't use any VS specific data from vec4_visitor::vp. So rename it to "prog" and change its type from struct gl_vertex_program * to struct gl_program *. This will allow the code to be re-used for geometry shaders. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> v2: Use the name "prog" rather than "p". Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-16 04:19:23 +00:00
_mesa_get_sampler_uniform_value(ir->sampler, shader_prog, prog);
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
i965/vec4: Add support for nonconst sampler indexing in VS visitor V2: Set force_writemask_all on ADD; this *is* necessary in the VS case too. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-09 11:08:11 +01:00
ir_rvalue *nonconst_sampler_index =
_mesa_get_sampler_array_nonconst_index(ir->sampler);
/* Handle non-constant sampler array indexing */
src_reg sampler_reg;
if (nonconst_sampler_index) {
/* The highest sampler which may be used by this operation is
* the last element of the array. Mark it here, because the generator
* doesn't have enough information to determine the bound.
*/
uint32_t array_size = ir->sampler->as_dereference_array()
->array->type->array_size();
uint32_t max_used = sampler + array_size - 1;
if (ir->op == ir_tg4 && brw->gen < 8) {
max_used += prog_data->base.binding_table.gather_texture_start;
} else {
max_used += prog_data->base.binding_table.texture_start;
}
brw_mark_surface_used(&prog_data->base, max_used);
/* Emit code to evaluate the actual indexing expression */
nonconst_sampler_index->accept(this);
dst_reg temp(this, glsl_type::uint_type);
emit(ADD(temp, this->result, src_reg(sampler)))
->force_writemask_all = true;
sampler_reg = src_reg(temp);
} else {
/* Single sampler, or constant array index; the indexing expression
* is just an immediate.
*/
sampler_reg = src_reg(sampler);
}
i965/vs: Add support for ir_tg4 Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:39:37 +01:00
/* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
* emitting anything other than setting up the constant result.
*/
if (ir->op == ir_tg4) {
i965/vs: Add support for textureGather(.., comp) - For HSW: Select the channel based on the component selected (swizzle is done in HW) - For IVB: Select the channel based on the swizzle state for the component selected. Only apply the RG32F w/a if we actually want green -- we're about to flag it regardless of swizzle state. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-05 11:10:04 +01:00
ir_constant *chan = ir->lod_info.component->as_constant();
int swiz = GET_SWZ(key->tex.swizzles[sampler], chan->value.i[0]);
i965/vs: Add support for ir_tg4 Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:39:37 +01:00
if (swiz == SWIZZLE_ZERO || swiz == SWIZZLE_ONE) {
dst_reg result(this, ir->type);
this->result = src_reg(result);
emit(MOV(result, src_reg(swiz == SWIZZLE_ONE ? 1.0f : 0.0f)));
return;
}
}
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
/* Should be lowered by do_lower_texture_projection */
assert(!ir->projector);
i965: Add asserts to ensure that ir_tg4 offset arrays are lowered We don't have a message that does 4 independent offsets; a lowering pass needs to lower it to 4 normal gather4s before reaching this point. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-10 09:40:46 +01:00
/* Should be lowered */
assert(!ir->offset || !ir->offset->type->is_array());
i965/vs: Don't clobber sampler message MRFs with subexpressions. See the preceding commit for a description of the problem. NOTE: This is a candidate for stable release branches. v2: Use a separate dPdx variable rather than reusing the lod src_reg. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52129 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 05:28:23 +01:00
/* Generate code to compute all the subexpression trees. This has to be
* done before loading any values into MRFs for the sampler message since
* generating these values may involve SEND messages that need the MRFs.
*/
src_reg coordinate;
if (ir->coordinate) {
ir->coordinate->accept(this);
coordinate = this->result;
}
src_reg shadow_comparitor;
if (ir->shadow_comparitor) {
ir->shadow_comparitor->accept(this);
shadow_comparitor = this->result;
}
i965/vs: add support for gather4 with nonconstant offsets Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2013-10-08 10:19:58 +01:00
bool has_nonconstant_offset = ir->offset && !ir->offset->as_constant();
src_reg offset_value;
if (has_nonconstant_offset) {
ir->offset->accept(this);
offset_value = src_reg(this->result);
}
i965: Fix compiler warnings since the introduction of texture multisample. Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-04-05 21:43:52 +01:00
const glsl_type *lod_type = NULL, *sample_index_type = NULL;
i965/vs: Sample from MCS surface when required Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-30 00:49:50 +00:00
src_reg lod, dPdx, dPdy, sample_index, mcs;
i965/vs: Don't clobber sampler message MRFs with subexpressions. See the preceding commit for a description of the problem. NOTE: This is a candidate for stable release branches. v2: Use a separate dPdx variable rather than reusing the lod src_reg. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52129 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 05:28:23 +01:00
switch (ir->op) {
i965/vs: Set LOD to 0 for ordinary texture() calls. Previously it was left undefined, causing us to select a random LOD. NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org>
2013-01-17 03:09:52 +00:00
case ir_tex:
lod = src_reg(0.0f);
lod_type = glsl_type::float_type;
break;
i965/vs: Don't clobber sampler message MRFs with subexpressions. See the preceding commit for a description of the problem. NOTE: This is a candidate for stable release branches. v2: Use a separate dPdx variable rather than reusing the lod src_reg. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52129 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 05:28:23 +01:00
case ir_txf:
case ir_txl:
case ir_txs:
ir->lod_info.lod->accept(this);
lod = this->result;
i965/vs: Create a 'lod_type' temporary for ir->lod_info.lod->type. This is purely a refactor. However, in a moment, we'll want to set lod_type to float for ir_tex, where ir->lod_info.lod is NULL. NOTE: This is a candidate for stable branches (for the next patch). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org>
2013-01-17 03:08:12 +00:00
lod_type = ir->lod_info.lod->type;
i965/vs: Don't clobber sampler message MRFs with subexpressions. See the preceding commit for a description of the problem. NOTE: This is a candidate for stable release branches. v2: Use a separate dPdx variable rather than reusing the lod src_reg. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52129 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 05:28:23 +01:00
break;
i965/vs: implement ir_query_levels Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-09-26 18:52:20 +01:00
case ir_query_levels:
lod = src_reg(0);
lod_type = glsl_type::int_type;
break;
i965/vs: add support for ir_txf_ms on Gen6+ On Gen6, lower this to `ld` with lod=0 and an extra sample_index parameter. On Gen7, use `ld2dms`. This takes an additional MCS parameter to support compressed multisample surfaces, but we're not enabling them for multisample textures for now, so it's always ignored and can be safely omitted. V2: Reworked completely, added support for Gen7. V3: - Use new sample_index, sample_index_type rather than reusing lod - Clarify commit message. V4: - Fix comment style Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-12-29 07:12:26 +00:00
case ir_txf_ms:
ir->lod_info.sample_index->accept(this);
sample_index = this->result;
sample_index_type = ir->lod_info.sample_index->type;
i965/vs: Sample from MCS surface when required Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-30 00:49:50 +00:00
if (brw->gen >= 7 && key->tex.compressed_multisample_layout_mask & (1<<sampler))
i965/vec4: Add support for nonconst sampler indexing in VS visitor V2: Set force_writemask_all on ADD; this *is* necessary in the VS case too. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-09 11:08:11 +01:00
mcs = emit_mcs_fetch(ir, coordinate, sampler_reg);
i965/vs: Sample from MCS surface when required Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-30 00:49:50 +00:00
else
mcs = src_reg(0u);
i965/vs: add support for ir_txf_ms on Gen6+ On Gen6, lower this to `ld` with lod=0 and an extra sample_index parameter. On Gen7, use `ld2dms`. This takes an additional MCS parameter to support compressed multisample surfaces, but we're not enabling them for multisample textures for now, so it's always ignored and can be safely omitted. V2: Reworked completely, added support for Gen7. V3: - Use new sample_index, sample_index_type rather than reusing lod - Clarify commit message. V4: - Fix comment style Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-12-29 07:12:26 +00:00
break;
i965/vs: Don't clobber sampler message MRFs with subexpressions. See the preceding commit for a description of the problem. NOTE: This is a candidate for stable release branches. v2: Use a separate dPdx variable rather than reusing the lod src_reg. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52129 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 05:28:23 +01:00
case ir_txd:
ir->lod_info.grad.dPdx->accept(this);
dPdx = this->result;
ir->lod_info.grad.dPdy->accept(this);
dPdy = this->result;
i965/vs: Create a 'lod_type' temporary for ir->lod_info.lod->type. This is purely a refactor. However, in a moment, we'll want to set lod_type to float for ir_tex, where ir->lod_info.lod is NULL. NOTE: This is a candidate for stable branches (for the next patch). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org>
2013-01-17 03:08:12 +00:00
lod_type = ir->lod_info.grad.dPdx->type;
i965/vs: Don't clobber sampler message MRFs with subexpressions. See the preceding commit for a description of the problem. NOTE: This is a candidate for stable release branches. v2: Use a separate dPdx variable rather than reusing the lod src_reg. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52129 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 05:28:23 +01:00
break;
case ir_txb:
i965/fs: Generate LOD sampler message from ir_lod. v2: Support Ironlake as well. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:01 +00:00
case ir_lod:
i965/vs: Add support for ir_tg4 Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:39:37 +01:00
case ir_tg4:
i965/vs: Don't clobber sampler message MRFs with subexpressions. See the preceding commit for a description of the problem. NOTE: This is a candidate for stable release branches. v2: Use a separate dPdx variable rather than reusing the lod src_reg. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52129 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 05:28:23 +01:00
break;
}
i965/vec4: Collect all emits of texture ops into one place Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-03 11:01:11 +01:00
enum opcode opcode;
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
switch (ir->op) {
i965/vec4: Collect all emits of texture ops into one place Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-03 11:01:11 +01:00
case ir_tex: opcode = SHADER_OPCODE_TXL; break;
case ir_txl: opcode = SHADER_OPCODE_TXL; break;
case ir_txd: opcode = SHADER_OPCODE_TXD; break;
case ir_txf: opcode = SHADER_OPCODE_TXF; break;
case ir_txf_ms: opcode = SHADER_OPCODE_TXF_CMS; break;
case ir_txs: opcode = SHADER_OPCODE_TXS; break;
case ir_tg4: opcode = has_nonconstant_offset
? SHADER_OPCODE_TG4_OFFSET : SHADER_OPCODE_TG4; break;
case ir_query_levels: opcode = SHADER_OPCODE_TXS; break;
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
case ir_txb:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("TXB is not valid for vertex shaders.");
i965/fs: Generate LOD sampler message from ir_lod. v2: Support Ironlake as well. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:01 +00:00
case ir_lod:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("LOD is not valid for vertex shaders.");
i965/vs: Add support for ir_tg4 Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:39:37 +01:00
default:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("Unrecognized tex op");
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
}
i965/vec4: Pass dst register to the vec4_instruction constructor. So regs_written gets initialized with a sensible value. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-03 20:53:17 +00:00
vec4_instruction *inst = new(mem_ctx) vec4_instruction(
opcode, dst_reg(this, ir->type));
i965/vec4: Collect all emits of texture ops into one place Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-03 11:01:11 +01:00
i965: Make brw_texture_offset() not use ir_texture. Our new IR won't have ir_texture objects. Signed-off-by: Connor Abbott <connor.abbott@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-04 23:20:38 +01:00
if (ir->offset != NULL && !has_nonconstant_offset) {
i965: Combine offset/texture_offset fields. texture_offset was only used by some texturing operations, and offset was only used by spill/unspill and some URB operations. These fields are never used at the same time. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-12 19:28:02 +00:00
inst->offset =
i965: Make brw_texture_offset() not use ir_texture. Our new IR won't have ir_texture objects. Signed-off-by: Connor Abbott <connor.abbott@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-04 23:20:38 +01:00
brw_texture_offset(ctx, ir->offset->as_constant()->value.i,
ir->offset->type->vector_elements);
}
i965/vec4: Don't set header_present if texel offsets are all 0. In theory, a shader might use textureOffset() but set all the texel offsets to zero. In that case, we don't actually need to set up the message header - zero is the implicit default. By moving the texture_offset setup before the header_present setup, we can easily only set header_present when there are non-zero texel offset values. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 22:34:07 +00:00
/* Stuff the channel select bits in the top of the texture offset */
if (ir->op == ir_tg4)
i965: Combine offset/texture_offset fields. texture_offset was only used by some texturing operations, and offset was only used by spill/unspill and some URB operations. These fields are never used at the same time. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-12 19:28:02 +00:00
inst->offset |= gather_channel(ir, sampler) << 16;
i965/vs: Do headerless texturing for texelFetchOffset(). For texelFetchOffset(), we just add the texel offsets to the coordinate rather than using the message header's offset fields. So we don't actually need a header on Gen5+. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-01-22 05:24:34 +00:00
i965/vec4: Support arbitrarily large sampler state indices on Haswell+. Like the scalar backend, we add an offset to the "Sampler State Pointer" field to select a group of 16 samplers, then use the "Sampler Index" field to select within that group. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 22:32:49 +00:00
/* The message header is necessary for:
* - Gen4 (always)
i965/skl: Always use a header for SIMD4x2 sampler messages SKL+ overloads the SIMD4x2 SIMD mode to mean either SIMD8D or SIMD4x2 depending on bit 22 in the message header. If the bit is 0 or there is no header we get SIMD8D. We always wand SIMD4x2 in vec4 and for fs pull constants, so use a message header in those cases and set bit 22 there. Based on an initial patch from Ken. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2014-12-10 22:59:26 +00:00
* - Gen9+ for selecting SIMD4x2
i965/vec4: Support arbitrarily large sampler state indices on Haswell+. Like the scalar backend, we add an offset to the "Sampler State Pointer" field to select a group of 16 samplers, then use the "Sampler Index" field to select within that group. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 22:32:49 +00:00
* - Texel offsets
* - Gather channel selection
* - Sampler indices too large to fit in a 4-bit value.
*/
i965/vec4: Don't set header_present if texel offsets are all 0. In theory, a shader might use textureOffset() but set all the texel offsets to zero. In that case, we don't actually need to set up the message header - zero is the implicit default. By moving the texture_offset setup before the header_present setup, we can easily only set header_present when there are non-zero texel offset values. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 22:34:07 +00:00
inst->header_present =
i965/skl: Always use a header for SIMD4x2 sampler messages SKL+ overloads the SIMD4x2 SIMD mode to mean either SIMD8D or SIMD4x2 depending on bit 22 in the message header. If the bit is 0 or there is no header we get SIMD8D. We always wand SIMD4x2 in vec4 and for fs pull constants, so use a message header in those cases and set bit 22 there. Based on an initial patch from Ken. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2014-12-10 22:59:26 +00:00
brw->gen < 5 || brw->gen >= 9 ||
inst->offset != 0 || ir->op == ir_tg4 ||
i965/vec4: Add support for nonconst sampler indexing in VS visitor V2: Set force_writemask_all on ADD; this *is* necessary in the VS case too. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-09 11:08:11 +01:00
is_high_sampler(brw, sampler_reg);
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
inst->base_mrf = 2;
inst->mlen = inst->header_present + 1; /* always at least one */
i965/vec4: Override destination register writemask in sampler message send. This line was removed by accident in commit 16b911257440afbd77a6eb762e28df62e3c19bc7 causing a regression in the ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_vert Khronos conformance test. It's necessary because the swizzle_result() code below expects all four components of the vector to be valid. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89094 Tested-by: Lu Hua <huax.lu@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-12 08:20:49 +00:00
inst->dst.writemask = WRITEMASK_XYZW;
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
inst->shadow_compare = ir->shadow_comparitor != NULL;
i965/vec4: Add support for nonconst sampler indexing in VS visitor V2: Set force_writemask_all on ADD; this *is* necessary in the VS case too. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-09 11:08:11 +01:00
inst->src[1] = sampler_reg;
i965/vec4: Pass sampler index in src1 for texture ops Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-04 08:37:58 +01:00
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
/* MRF for the first parameter */
int param_base = inst->base_mrf + inst->header_present;
i965/vs: implement ir_query_levels Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-09-26 18:52:20 +01:00
if (ir->op == ir_txs || ir->op == ir_query_levels) {
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
int writemask = brw->gen == 4 ? WRITEMASK_W : WRITEMASK_X;
i965/vs: Create a 'lod_type' temporary for ir->lod_info.lod->type. This is purely a refactor. However, in a moment, we'll want to set lod_type to float for ir_tex, where ir->lod_info.lod is NULL. NOTE: This is a candidate for stable branches (for the next patch). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org>
2013-01-17 03:08:12 +00:00
emit(MOV(dst_reg(MRF, param_base, lod_type, writemask), lod));
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
} else {
/* Load the coordinate */
/* FINISHME: gl_clamp_mask and saturate */
i965/vec4: Simplify the computation of coord_mask and zero_mask. We can easily compute these without loops, resulting in simpler and shorter code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Suggested-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-09 23:36:59 +01:00
int coord_mask = (1 << ir->coordinate->type->vector_elements) - 1;
int zero_mask = 0xf & ~coord_mask;
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
i965: Remove ir_txf coord+offset special case in visitors Just let it be handled by the lowering pass. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-12 12:02:04 +01:00
emit(MOV(dst_reg(MRF, param_base, ir->coordinate->type, coord_mask),
coordinate));
i965/vec4: Only zero out unused message components when there are any. Otherwise, coordinates with four components would result in a MOV with a destination writemask that has no channels enabled: mov(8) g115<1>.F 0D { align16 WE_normal NoDDChk 1Q }; At best, this is stupid: we emit code that shouldn't do anything. Worse, it apparently causes GPU hangs (observable with Chris's textureGather test on CubeArrays.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <idr@freedesktop.org> Cc: mesa-stable@lists.freedesktop.org
2013-09-09 19:11:03 +01:00
if (zero_mask != 0) {
emit(MOV(dst_reg(MRF, param_base, ir->coordinate->type, zero_mask),
src_reg(0)));
}
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
/* Load the shadow comparitor */
i965/vs: Add support for shadow comparitors with gather4 gather4_c's argument layout is straightforward -- refz just goes on the end. gather4_po_c's layout however -- the array index is replaced with refz. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-10 07:42:47 +01:00
if (ir->shadow_comparitor && ir->op != ir_txd && (ir->op != ir_tg4 || !has_nonconstant_offset)) {
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
emit(MOV(dst_reg(MRF, param_base + 1, ir->shadow_comparitor->type,
WRITEMASK_X),
i965/vs: Don't clobber sampler message MRFs with subexpressions. See the preceding commit for a description of the problem. NOTE: This is a candidate for stable release branches. v2: Use a separate dPdx variable rather than reusing the lod src_reg. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52129 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 05:28:23 +01:00
shadow_comparitor));
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
inst->mlen++;
}
/* Load the LOD info */
i965/vs: Set LOD to 0 for ordinary texture() calls. Previously it was left undefined, causing us to select a random LOD. NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org>
2013-01-17 03:09:52 +00:00
if (ir->op == ir_tex || ir->op == ir_txl) {
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
int mrf, writemask;
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 5) {
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
mrf = param_base + 1;
if (ir->shadow_comparitor) {
writemask = WRITEMASK_Y;
/* mlen already incremented */
} else {
writemask = WRITEMASK_X;
inst->mlen++;
}
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
} else /* brw->gen == 4 */ {
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
mrf = param_base;
i965/vs: Put lod parameter in the correct place for Gen4 This was never visible before due to the bogus sampler state pointer. Fixes remaining vertex texturing breakage on Gen4. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org
2013-07-30 05:03:58 +01:00
writemask = WRITEMASK_W;
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
}
i965/vs: Create a 'lod_type' temporary for ir->lod_info.lod->type. This is purely a refactor. However, in a moment, we'll want to set lod_type to float for ir_tex, where ir->lod_info.lod is NULL. NOTE: This is a candidate for stable branches (for the next patch). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org>
2013-01-17 03:08:12 +00:00
emit(MOV(dst_reg(MRF, mrf, lod_type, writemask), lod));
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
} else if (ir->op == ir_txf) {
i965/vs: add support for ir_txf_ms on Gen6+ On Gen6, lower this to `ld` with lod=0 and an extra sample_index parameter. On Gen7, use `ld2dms`. This takes an additional MCS parameter to support compressed multisample surfaces, but we're not enabling them for multisample textures for now, so it's always ignored and can be safely omitted. V2: Reworked completely, added support for Gen7. V3: - Use new sample_index, sample_index_type rather than reusing lod - Clarify commit message. V4: - Fix comment style Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-12-29 07:12:26 +00:00
emit(MOV(dst_reg(MRF, param_base, lod_type, WRITEMASK_W), lod));
} else if (ir->op == ir_txf_ms) {
emit(MOV(dst_reg(MRF, param_base + 1, sample_index_type, WRITEMASK_X),
sample_index));
i965: add missing parens in vec4 visitor coverity reported this, Matt said it look like missing parens, not bad identing, so lets try that. Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-02 01:13:02 +01:00
if (brw->gen >= 7) {
i965/vs: Sample from MCS surface when required Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-30 00:49:50 +00:00
/* MCS data is in the first channel of `mcs`, but we need to get it into
* the .y channel of the second vec4 of params, so replicate .x across
* the whole vec4 and then mask off everything except .y
*/
mcs.swizzle = BRW_SWIZZLE_XXXX;
emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::uint_type, WRITEMASK_Y),
mcs));
i965: add missing parens in vec4 visitor coverity reported this, Matt said it look like missing parens, not bad identing, so lets try that. Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-02 01:13:02 +01:00
}
i965/vs: add support for ir_txf_ms on Gen6+ On Gen6, lower this to `ld` with lod=0 and an extra sample_index parameter. On Gen7, use `ld2dms`. This takes an additional MCS parameter to support compressed multisample surfaces, but we're not enabling them for multisample textures for now, so it's always ignored and can be safely omitted. V2: Reworked completely, added support for Gen7. V3: - Use new sample_index, sample_index_type rather than reusing lod - Clarify commit message. V4: - Fix comment style Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-12-29 07:12:26 +00:00
inst->mlen++;
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
} else if (ir->op == ir_txd) {
i965/vs: Create a 'lod_type' temporary for ir->lod_info.lod->type. This is purely a refactor. However, in a moment, we'll want to set lod_type to float for ir_tex, where ir->lod_info.lod is NULL. NOTE: This is a candidate for stable branches (for the next patch). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org>
2013-01-17 03:08:12 +00:00
const glsl_type *type = lod_type;
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 5) {
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
dPdx.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
dPdy.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XZ), dPdx));
emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_YW), dPdy));
inst->mlen++;
i965/vs: Fix textureGrad() with shadow samplers on Haswell. The shadow comparitor needs to be loaded into the Z component of the last DWord. Fixes es3conform's shadow_execution_vert and oglconform's shadow-grad advanced.textureGrad.1D tests on Haswell. NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-13 05:51:17 +00:00
if (ir->type->vector_elements == 3 || ir->shadow_comparitor) {
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
dPdx.swizzle = BRW_SWIZZLE_ZZZZ;
dPdy.swizzle = BRW_SWIZZLE_ZZZZ;
emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_X), dPdx));
emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_Y), dPdy));
inst->mlen++;
i965/vs: Fix textureGrad() with shadow samplers on Haswell. The shadow comparitor needs to be loaded into the Z component of the last DWord. Fixes es3conform's shadow_execution_vert and oglconform's shadow-grad advanced.textureGrad.1D tests on Haswell. NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-13 05:51:17 +00:00
if (ir->shadow_comparitor) {
emit(MOV(dst_reg(MRF, param_base + 2,
ir->shadow_comparitor->type, WRITEMASK_Z),
shadow_comparitor));
}
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
}
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
} else /* brw->gen == 4 */ {
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XYZ), dPdx));
emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_XYZ), dPdy));
inst->mlen += 2;
}
i965/vs: add support for gather4 with nonconstant offsets Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2013-10-08 10:19:58 +01:00
} else if (ir->op == ir_tg4 && has_nonconstant_offset) {
i965/vs: Add support for shadow comparitors with gather4 gather4_c's argument layout is straightforward -- refz just goes on the end. gather4_po_c's layout however -- the array index is replaced with refz. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-10 07:42:47 +01:00
if (ir->shadow_comparitor) {
emit(MOV(dst_reg(MRF, param_base, ir->shadow_comparitor->type, WRITEMASK_W),
shadow_comparitor));
}
i965/vs: add support for gather4 with nonconstant offsets Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2013-10-08 10:19:58 +01:00
emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::ivec2_type, WRITEMASK_XY),
offset_value));
inst->mlen++;
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-26 22:00:52 +01:00
}
}
emit(inst);
i965: vs: Add fixup for textureSize with cube array samplers V3: Fixed weird whitespace V4: Use sampler's type rather than variable's type; otherwise broken with arrays of samplers. (Thanks Eric) v5: Fix a couple more style nits (by anholt) Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-22 08:32:08 +00:00
/* fixup num layers (z) for cube arrays: hardware returns faces * layers;
* spec requires layers.
*/
if (ir->op == ir_txs) {
glsl_type const *type = ir->sampler->type;
if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
type->sampler_array) {
emit_math(SHADER_OPCODE_INT_QUOTIENT,
i965/vec4: Trivial improvements to the with_writemask() function. Add assertion that the register is not in the HW_REG or IMM file, calculate the conjunction of the old and new mask instead of replacing the old [consistent with the behavior of brw_writemask(), causes no functional changes right now], make it static inline to let the compiler do a slightly better job at optimizing things, and shorten its name. v2: Assert that the new writemask is not zero to avoid undefined hardware behaviour. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-28 23:07:06 +00:00
writemask(inst->dst, WRITEMASK_Z),
i965: vs: Add fixup for textureSize with cube array samplers V3: Fixed weird whitespace V4: Use sampler's type rather than variable's type; otherwise broken with arrays of samplers. (Thanks Eric) v5: Fix a couple more style nits (by anholt) Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-22 08:32:08 +00:00
src_reg(inst->dst), src_reg(6));
}
}
i965/vec4: Emit shader w/a for Gen6 gather Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-02-03 09:15:41 +00:00
if (brw->gen == 6 && ir->op == ir_tg4) {
emit_gen6_gather_wa(key->tex.gen6_gather_wa[sampler], inst->dst);
}
i965: Index sampler program key data by linker-assigned index. Now that most things are based on the linker-assigned index, it makes sense to convert the arrays in the VS/WM program key as well. It seems silly to leave them indexed by texture unit. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-26 08:28:38 +01:00
swizzle_result(ir, src_reg(inst->dst), sampler);
i965/vs: Implement EXT_texture_swizzle support for VS texturing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-12-07 11:20:53 +00:00
}
i965/vec4: Emit shader w/a for Gen6 gather Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-02-03 09:15:41 +00:00
/**
* Apply workarounds for Gen6 gather with UINT/SINT
*/
void
vec4_visitor::emit_gen6_gather_wa(uint8_t wa, dst_reg dst)
{
if (!wa)
return;
int width = (wa & WA_8BIT) ? 8 : 16;
dst_reg dst_f = dst;
dst_f.type = BRW_REGISTER_TYPE_F;
/* Convert from UNORM to UINT */
emit(MUL(dst_f, src_reg(dst_f), src_reg((float)((1 << width) - 1))));
emit(MOV(dst, src_reg(dst_f)));
if (wa & WA_SIGN) {
/* Reinterpret the UINT value as a signed INT value by
* shifting the sign bit into place, then shifting back
* preserving sign.
*/
emit(SHL(dst, src_reg(dst), src_reg(32 - width)));
emit(ASR(dst, src_reg(dst), src_reg(32 - width)));
}
}
i965/vs: Add support for ir_tg4 Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:39:37 +01:00
/**
* Set up the gather channel based on the swizzle, for gather4.
*/
uint32_t
i965/vec4: Pass sampler index in src1 for texture ops Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-04 08:37:58 +01:00
vec4_visitor::gather_channel(ir_texture *ir, uint32_t sampler)
i965/vs: Add support for ir_tg4 Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:39:37 +01:00
{
i965/vs: Add support for textureGather(.., comp) - For HSW: Select the channel based on the component selected (swizzle is done in HW) - For IVB: Select the channel based on the swizzle state for the component selected. Only apply the RG32F w/a if we actually want green -- we're about to flag it regardless of swizzle state. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-05 11:10:04 +01:00
ir_constant *chan = ir->lod_info.component->as_constant();
int swiz = GET_SWZ(key->tex.swizzles[sampler], chan->value.i[0]);
i965/vs: Add support for ir_tg4 Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:39:37 +01:00
switch (swiz) {
case SWIZZLE_X: return 0;
i965/vs: Add support for textureGather(.., comp) - For HSW: Select the channel based on the component selected (swizzle is done in HW) - For IVB: Select the channel based on the swizzle state for the component selected. Only apply the RG32F w/a if we actually want green -- we're about to flag it regardless of swizzle state. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-05 11:10:04 +01:00
case SWIZZLE_Y:
/* gather4 sampler is broken for green channel on RG32F --
* we must ask for blue instead.
*/
if (key->tex.gather_channel_quirk_mask & (1<<sampler))
return 2;
return 1;
i965/vs: Add support for ir_tg4 Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:39:37 +01:00
case SWIZZLE_Z: return 2;
case SWIZZLE_W: return 3;
default:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("Not reached"); /* zero, one swizzles handled already */
i965/vs: Add support for ir_tg4 Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:39:37 +01:00
}
}
i965/vs: Implement EXT_texture_swizzle support for VS texturing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-12-07 11:20:53 +00:00
void
i965/vec4: Pass sampler index in src1 for texture ops Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-04 08:37:58 +01:00
vec4_visitor::swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler)
i965/vs: Implement EXT_texture_swizzle support for VS texturing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-12-07 11:20:53 +00:00
{
i965/vs: move VS-specific data members to vs_vec4_visitor. This patch moves the following data structures from vec4_visitor to vec4_vs_visitor, since they contain VS-specific data: - struct brw_vs_compile *c (renamed to vs_compile) - struct brw_vs_prog_data *prog_data (renamed to vs_prog_data) - src_reg *vp_temp_regs - src_reg vp_addr_reg Since brw_vs_compile and brw_vs_prog_data also contain vec4-generic data, the following pointers are added to the base class, to allow it to access the vec4-generic portions of these data structures: - struct brw_vec4_compile *c - struct brw_vec4_prog_key *key - struct brw_vec4_prog_data *prog_data Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> v2: Use shorter names in the base class and longer names in the derived class. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-17 17:09:45 +00:00
int s = key->tex.swizzles[sampler];
i965/vs: Implement EXT_texture_swizzle support for VS texturing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-12-07 11:20:53 +00:00
i965/vs: Store texturing results into a vec4 temporary. The sampler appears to ignore writemasks (even when correcting the WRITEMASK_XYZW in brw_vec4_emit.cpp to the proper writemask) and just always writes all four values. To cope with this, just texture into a temporary, then MOV out into a register that has the proper number of components. NOTE: This is a candidate for stable branches. Fixes es3conform's shadow_execution_vert.test. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org>
2013-01-17 04:24:13 +00:00
this->result = src_reg(this, ir->type);
dst_reg swizzled_result(this->result);
i965/vs: implement ir_query_levels Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-09-26 18:52:20 +01:00
if (ir->op == ir_query_levels) {
/* # levels is in .w */
orig_val.swizzle = BRW_SWIZZLE4(SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W);
emit(MOV(swizzled_result, orig_val));
return;
}
i965/vs: Implement EXT_texture_swizzle support for VS texturing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-12-07 11:20:53 +00:00
if (ir->op == ir_txs || ir->type == glsl_type::float_type
i965/vs: Add support for ir_tg4 Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:39:37 +01:00
|| s == SWIZZLE_NOOP || ir->op == ir_tg4) {
i965/vs: Store texturing results into a vec4 temporary. The sampler appears to ignore writemasks (even when correcting the WRITEMASK_XYZW in brw_vec4_emit.cpp to the proper writemask) and just always writes all four values. To cope with this, just texture into a temporary, then MOV out into a register that has the proper number of components. NOTE: This is a candidate for stable branches. Fixes es3conform's shadow_execution_vert.test. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org>
2013-01-17 04:24:13 +00:00
emit(MOV(swizzled_result, orig_val));
i965/vs: Implement EXT_texture_swizzle support for VS texturing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-12-07 11:20:53 +00:00
return;
i965/vs: Store texturing results into a vec4 temporary. The sampler appears to ignore writemasks (even when correcting the WRITEMASK_XYZW in brw_vec4_emit.cpp to the proper writemask) and just always writes all four values. To cope with this, just texture into a temporary, then MOV out into a register that has the proper number of components. NOTE: This is a candidate for stable branches. Fixes es3conform's shadow_execution_vert.test. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org>
2013-01-17 04:24:13 +00:00
}
i965/vs: Implement EXT_texture_swizzle support for VS texturing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-12-07 11:20:53 +00:00
i965/vs: Add support for ir_tg4 Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:39:37 +01:00
i965/vs: Implement EXT_texture_swizzle support for VS texturing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-12-07 11:20:53 +00:00
int zero_mask = 0, one_mask = 0, copy_mask = 0;
i965/vs: Fix flaky texture swizzling If any component used the ZERO or ONE swizzle, its corresponding member in the `swizzle` array would never be initialized. We *mostly* got away with this, except when that memory happened to contain a value that clobbered another channel when combined using BRW_SWIZZLE4(). NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-07-23 20:21:22 +01:00
int swizzle[4] = {0};
i965/vs: Implement EXT_texture_swizzle support for VS texturing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-12-07 11:20:53 +00:00
for (int i = 0; i < 4; i++) {
switch (GET_SWZ(s, i)) {
case SWIZZLE_ZERO:
zero_mask |= (1 << i);
break;
case SWIZZLE_ONE:
one_mask |= (1 << i);
break;
default:
copy_mask |= (1 << i);
swizzle[i] = GET_SWZ(s, i);
break;
}
}
if (copy_mask) {
orig_val.swizzle = BRW_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
swizzled_result.writemask = copy_mask;
emit(MOV(swizzled_result, orig_val));
}
if (zero_mask) {
swizzled_result.writemask = zero_mask;
emit(MOV(swizzled_result, src_reg(0.0f)));
}
if (one_mask) {
swizzled_result.writemask = one_mask;
emit(MOV(swizzled_result, src_reg(1.0f)));
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
void
i965/vec4: Silence a couple unused parameter warnings brw_vec4_visitor.cpp:2717:1: warning: unused parameter 'ir' [-Wunused-parameter] brw_vec4_visitor.cpp:2723:1: warning: unused parameter 'ir' [-Wunused-parameter] Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-11 01:50:04 +01:00
vec4_visitor::visit(ir_return *)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
void
i965/vec4: Silence a couple unused parameter warnings brw_vec4_visitor.cpp:2717:1: warning: unused parameter 'ir' [-Wunused-parameter] brw_vec4_visitor.cpp:2723:1: warning: unused parameter 'ir' [-Wunused-parameter] Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-11 01:50:04 +01:00
vec4_visitor::visit(ir_discard *)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached");
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
void
vec4_visitor::visit(ir_if *ir)
{
i965/vs: Fix support for "IF" instructions by copying brw_fs_visitor.cpp. Fixes glsl-vs-if-greater.
2011-08-06 03:12:16 +01:00
/* Don't point the annotation at the if statement, because then it plus
* the then and else blocks get printed.
*/
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
this->base_ir = ir->condition;
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen == 6) {
i965/vs: Fix support for "IF" instructions by copying brw_fs_visitor.cpp. Fixes glsl-vs-if-greater.
2011-08-06 03:12:16 +01:00
emit_if_gen6(ir);
} else {
i965: Make a brw_predicate enum. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-06-30 01:58:59 +01:00
enum brw_predicate predicate;
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-31 00:23:44 +01:00
emit_bool_to_cond_code(ir->condition, &predicate);
emit(IF(predicate));
i965/vs: Fix support for "IF" instructions by copying brw_fs_visitor.cpp. Fixes glsl-vs-if-greater.
2011-08-06 03:12:16 +01:00
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
visit_instructions(&ir->then_instructions);
if (!ir->else_instructions.is_empty()) {
this->base_ir = ir->condition;
emit(BRW_OPCODE_ELSE);
visit_instructions(&ir->else_instructions);
}
this->base_ir = ir->condition;
emit(BRW_OPCODE_ENDIF);
}
glsl: add ir_emit_vertex and ir_end_primitive instruction types These correspond to the EmitVertex and EndPrimitive functions in GLSL. v2 (Paul Berry <stereotype441@gmail.com>): Add stub implementations of new pure visitor functions to i965's vec4_visitor and fs_visitor classes. v3 (Paul Berry <stereotype441@gmail.com>): Rename classes to be more consistent with the names used in the GL spec. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-15 15:26:35 +00:00
void
vec4_visitor::visit(ir_emit_vertex *)
{
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached");
glsl: add ir_emit_vertex and ir_end_primitive instruction types These correspond to the EmitVertex and EndPrimitive functions in GLSL. v2 (Paul Berry <stereotype441@gmail.com>): Add stub implementations of new pure visitor functions to i965's vec4_visitor and fs_visitor classes. v3 (Paul Berry <stereotype441@gmail.com>): Rename classes to be more consistent with the names used in the GL spec. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-15 15:26:35 +00:00
}
void
vec4_visitor::visit(ir_end_primitive *)
{
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached");
glsl: add ir_emit_vertex and ir_end_primitive instruction types These correspond to the EmitVertex and EndPrimitive functions in GLSL. v2 (Paul Berry <stereotype441@gmail.com>): Add stub implementations of new pure visitor functions to i965's vec4_visitor and fs_visitor classes. v3 (Paul Berry <stereotype441@gmail.com>): Rename classes to be more consistent with the names used in the GL spec. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-15 15:26:35 +00:00
}
i965/gen7: Handle atomic instructions from the VEC4 back-end. This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. v2: Represent atomics as GLSL intrinsics. Add support for variably indexed atomic counter arrays. v3: Add comment on why we don't need to assign uniform storage for atomic counters. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-26 00:31:35 +01:00
void
vec4_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
dst_reg dst, src_reg offset,
src_reg src0, src_reg src1)
{
unsigned mlen = 0;
/* Set the atomic operation offset. */
emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen, 0), WRITEMASK_X), offset));
mlen++;
/* Set the atomic operation arguments. */
if (src0.file != BAD_FILE) {
emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen, 0), WRITEMASK_X), src0));
mlen++;
}
if (src1.file != BAD_FILE) {
emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen, 0), WRITEMASK_X), src1));
mlen++;
}
/* Emit the instruction. Note that this maps to the normal SIMD8
* untyped atomic message on Ivy Bridge, but that's OK because
* unused channels will be masked out.
*/
vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst,
src_reg(atomic_op), src_reg(surf_index));
inst->base_mrf = 0;
inst->mlen = mlen;
}
void
vec4_visitor::emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
src_reg offset)
{
/* Set the surface read offset. */
emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X), offset));
/* Emit the instruction. Note that this maps to the normal SIMD8
* untyped surface read message, but that's OK because unused
* channels will be masked out.
*/
vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ,
dst, src_reg(surf_index));
inst->base_mrf = 0;
inst->mlen = 1;
}
i965: new VS: move NDC computation (GEN4-5) to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:26:15 +01:00
void
vec4_visitor::emit_ndc_computation()
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
/* Get the position */
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
src_reg pos = src_reg(output_reg[VARYING_SLOT_POS]);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
/* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
dst_reg ndc = dst_reg(this, glsl_type::vec4_type);
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
output_reg[BRW_VARYING_SLOT_NDC] = ndc;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
current_annotation = "NDC";
dst_reg ndc_w = ndc;
ndc_w.writemask = WRITEMASK_W;
src_reg pos_w = pos;
pos_w.swizzle = BRW_SWIZZLE4(SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W);
emit_math(SHADER_OPCODE_RCP, ndc_w, pos_w);
dst_reg ndc_xyz = ndc;
ndc_xyz.writemask = WRITEMASK_XYZ;
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(MUL(ndc_xyz, pos, src_reg(ndc_w)));
i965: new VS: move NDC computation (GEN4-5) to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:26:15 +01:00
}
i965: new VS: Move PSIZ/flags computation to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:29:48 +01:00
void
i965: Generalize emit_urb_slot() to emit to any dst_reg. In gen7+ we emit vertices as they come, however in gen6 geometry shaders we have to buffer vertex data for all vertices and then emit it all in one go at the end. To achieve this we need to generalize emit_urb_slot() to store vertex data in general purpose registers and not only MRF registers. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-17 15:59:10 +01:00
vec4_visitor::emit_psiz_and_flags(dst_reg reg)
i965: new VS: move NDC computation (GEN4-5) to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:26:15 +01:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen < 6 &&
i965/vs: move VS-specific data members to vs_vec4_visitor. This patch moves the following data structures from vec4_visitor to vec4_vs_visitor, since they contain VS-specific data: - struct brw_vs_compile *c (renamed to vs_compile) - struct brw_vs_prog_data *prog_data (renamed to vs_prog_data) - src_reg *vp_temp_regs - src_reg vp_addr_reg Since brw_vs_compile and brw_vs_prog_data also contain vec4-generic data, the following pointers are added to the base class, to allow it to access the vec4-generic portions of these data structures: - struct brw_vec4_compile *c - struct brw_vec4_prog_key *key - struct brw_vec4_prog_data *prog_data Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> v2: Use shorter names in the base class and longer names in the derived class. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-17 17:09:45 +00:00
((prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) ||
key->userclip_active || brw->has_negative_rhw_bug)) {
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
dst_reg header1 = dst_reg(this, glsl_type::uvec4_type);
i965 new VS: Fix bugs in pre-GEN6 psiz/flags computation This patch corrects two errors in the computation of the psiz/flags VUE slot on pre-GEN5 when using the new VS backend: - The clip flags (which should be stored in the w component of the first VUE slot) were being accidentally duplicated in all other components of that VUE slot, causing partially clipped triangles to sometimes disappear completely. - The OR instruction wasn't being stored in "inst", causing the BRW_PREDICATE_NORMAL flag to be applied to the wrong instruction. This patch fixes regressions in clipping behavior when using shaders on GEN4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-09-24 05:36:17 +01:00
dst_reg header1_w = header1;
header1_w.writemask = WRITEMASK_W;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 18:52:16 +01:00
emit(MOV(header1, 0u));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: move VS-specific data members to vs_vec4_visitor. This patch moves the following data structures from vec4_visitor to vec4_vs_visitor, since they contain VS-specific data: - struct brw_vs_compile *c (renamed to vs_compile) - struct brw_vs_prog_data *prog_data (renamed to vs_prog_data) - src_reg *vp_temp_regs - src_reg vp_addr_reg Since brw_vs_compile and brw_vs_prog_data also contain vec4-generic data, the following pointers are added to the base class, to allow it to access the vec4-generic portions of these data structures: - struct brw_vec4_compile *c - struct brw_vec4_prog_key *key - struct brw_vec4_prog_data *prog_data Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> v2: Use shorter names in the base class and longer names in the derived class. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-17 17:09:45 +00:00
if (prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) {
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
src_reg psiz = src_reg(output_reg[VARYING_SLOT_PSIZ]);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: Fix point size handling on gen4. Fixes glsl-vs-point-size. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-30 23:34:43 +01:00
current_annotation = "Point size";
i965 new VS: Fix bugs in pre-GEN6 psiz/flags computation This patch corrects two errors in the computation of the psiz/flags VUE slot on pre-GEN5 when using the new VS backend: - The clip flags (which should be stored in the w component of the first VUE slot) were being accidentally duplicated in all other components of that VUE slot, causing partially clipped triangles to sometimes disappear completely. - The OR instruction wasn't being stored in "inst", causing the BRW_PREDICATE_NORMAL flag to be applied to the wrong instruction. This patch fixes regressions in clipping behavior when using shaders on GEN4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-09-24 05:36:17 +01:00
emit(MUL(header1_w, psiz, src_reg((float)(1 << 11))));
emit(AND(header1_w, src_reg(header1_w), 0x7ff << 8));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/Gen4-5: Set clip flags from clip distances V2: - Use the new VS_OPCODE_UNPACK_FLAGS_SIMD4X2 to correctly split the flags for the two vertices being processed together. - Don't apply bogus masking of clip flags. The set of plane enables aren't included in the shader key, and we wouldn't want the recompiles anyway. V3: - Tidy up spurious instructions, name temps properly. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> [V2] Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-03 16:32:34 +01:00
if (key->userclip_active) {
current_annotation = "Clipping flags";
dst_reg flags0 = dst_reg(this, glsl_type::uint_type);
dst_reg flags1 = dst_reg(this, glsl_type::uint_type);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/Gen4-5: Set clip flags from clip distances V2: - Use the new VS_OPCODE_UNPACK_FLAGS_SIMD4X2 to correctly split the flags for the two vertices being processed together. - Don't apply bogus masking of clip flags. The set of plane enables aren't included in the shader key, and we wouldn't want the recompiles anyway. V3: - Tidy up spurious instructions, name temps properly. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> [V2] Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-03 16:32:34 +01:00
emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST0]), src_reg(0.0f), BRW_CONDITIONAL_L));
emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags0, src_reg(0));
emit(OR(header1_w, src_reg(header1_w), src_reg(flags0)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/Gen4-5: Set clip flags from clip distances V2: - Use the new VS_OPCODE_UNPACK_FLAGS_SIMD4X2 to correctly split the flags for the two vertices being processed together. - Don't apply bogus masking of clip flags. The set of plane enables aren't included in the shader key, and we wouldn't want the recompiles anyway. V3: - Tidy up spurious instructions, name temps properly. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> [V2] Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-03 16:32:34 +01:00
emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST1]), src_reg(0.0f), BRW_CONDITIONAL_L));
emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags1, src_reg(0));
emit(SHL(flags1, src_reg(flags1), src_reg(4)));
emit(OR(header1_w, src_reg(header1_w), src_reg(flags1)));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
/* i965 clipping workaround:
* 1) Test for -ve rhw
* 2) If set,
* set ndc = (0,0,0,0)
* set ucp[6] = 1
*
* Later, clipping will detect ucp[6] and ensure the primitive is
* clipped against all fixed planes.
*/
if (brw->has_negative_rhw_bug) {
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
src_reg ndc_w = src_reg(output_reg[BRW_VARYING_SLOT_NDC]);
i965: Re-enable the -RHW workaround for original gen4 chips. Fixes broken clipping in supertuxkart and presumably many other applications. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51471 NOTE: Candidate for the stable branches. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-06 23:22:45 +00:00
ndc_w.swizzle = BRW_SWIZZLE_WWWW;
emit(CMP(dst_null_f(), ndc_w, src_reg(0.0f), BRW_CONDITIONAL_L));
vec4_instruction *inst;
inst = emit(OR(header1_w, src_reg(header1_w), src_reg(1u << 6)));
inst->predicate = BRW_PREDICATE_NORMAL;
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
inst = emit(MOV(output_reg[BRW_VARYING_SLOT_NDC], src_reg(0.0f)));
i965: Re-enable the -RHW workaround for original gen4 chips. Fixes broken clipping in supertuxkart and presumably many other applications. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51471 NOTE: Candidate for the stable branches. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-06 23:22:45 +00:00
inst->predicate = BRW_PREDICATE_NORMAL;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Fix point size handling on gen4. Fixes glsl-vs-point-size. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-30 23:34:43 +01:00
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), src_reg(header1)));
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
} else if (brw->gen < 6) {
i965: new VS: Move PSIZ/flags computation to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:29:48 +01:00
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), 0u));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
} else {
i965: new VS: Move PSIZ/flags computation to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:29:48 +01:00
emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), src_reg(0)));
i965/vs: move VS-specific data members to vs_vec4_visitor. This patch moves the following data structures from vec4_visitor to vec4_vs_visitor, since they contain VS-specific data: - struct brw_vs_compile *c (renamed to vs_compile) - struct brw_vs_prog_data *prog_data (renamed to vs_prog_data) - src_reg *vp_temp_regs - src_reg vp_addr_reg Since brw_vs_compile and brw_vs_prog_data also contain vec4-generic data, the following pointers are added to the base class, to allow it to access the vec4-generic portions of these data structures: - struct brw_vec4_compile *c - struct brw_vec4_prog_key *key - struct brw_vec4_prog_data *prog_data Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> v2: Use shorter names in the base class and longer names in the derived class. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-17 17:09:45 +00:00
if (prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) {
i965: Generalize emit_urb_slot() to emit to any dst_reg. In gen7+ we emit vertices as they come, however in gen6 geometry shaders we have to buffer vertex data for all vertices and then emit it all in one go at the end. To achieve this we need to generalize emit_urb_slot() to store vertex data in general purpose registers and not only MRF registers. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-17 15:59:10 +01:00
dst_reg reg_w = reg;
reg_w.writemask = WRITEMASK_W;
emit(MOV(reg_w, src_reg(output_reg[VARYING_SLOT_PSIZ])));
i965: new VS: Move PSIZ/flags computation to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:29:48 +01:00
}
i965: write layer if gl_Layer is used in VS This is enabled by the AMD_vertex_shader_layer extension. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-04-18 00:17:50 +01:00
if (prog_data->vue_map.slots_valid & VARYING_BIT_LAYER) {
i965: Generalize emit_urb_slot() to emit to any dst_reg. In gen7+ we emit vertices as they come, however in gen6 geometry shaders we have to buffer vertex data for all vertices and then emit it all in one go at the end. To achieve this we need to generalize emit_urb_slot() to store vertex data in general purpose registers and not only MRF registers. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-17 15:59:10 +01:00
dst_reg reg_y = reg;
reg_y.writemask = WRITEMASK_Y;
reg_y.type = BRW_REGISTER_TYPE_D;
emit(MOV(reg_y, src_reg(output_reg[VARYING_SLOT_LAYER])));
i965: write layer if gl_Layer is used in VS This is enabled by the AMD_vertex_shader_layer extension. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-04-18 00:17:50 +01:00
}
i965: Emit writes to viewport index This variable is handled in a fashion identical to gl_Layer. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-05 20:19:23 +00:00
if (prog_data->vue_map.slots_valid & VARYING_BIT_VIEWPORT) {
i965: Generalize emit_urb_slot() to emit to any dst_reg. In gen7+ we emit vertices as they come, however in gen6 geometry shaders we have to buffer vertex data for all vertices and then emit it all in one go at the end. To achieve this we need to generalize emit_urb_slot() to store vertex data in general purpose registers and not only MRF registers. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-17 15:59:10 +01:00
dst_reg reg_z = reg;
reg_z.writemask = WRITEMASK_Z;
reg_z.type = BRW_REGISTER_TYPE_D;
emit(MOV(reg_z, src_reg(output_reg[VARYING_SLOT_VIEWPORT])));
i965: Emit writes to viewport index This variable is handled in a fashion identical to gl_Layer. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-05 20:19:23 +00:00
}
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965: new VS: Move PSIZ/flags computation to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:29:48 +01:00
}
i965: new VS: move clip distance computation (GEN5+) to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:41:31 +01:00
void
i965/vs: Do legacy clip lowering earlier We need to produce clip flags for the vertex header on Gen4/5, so clip plane lowering has to be done before we try to emit the flags/psiz attribute. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-07-07 17:21:08 +01:00
vec4_visitor::emit_clip_distances(dst_reg reg, int offset)
i965: new VS: move clip distance computation (GEN5+) to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:41:31 +01:00
{
i965 Gen6: Implement gl_ClipVertex. This patch implements proper support for gl_ClipVertex by causing the new VS backend to populate the clip distance VUE slots using VERT_RESULT_CLIP_VERTEX when appropriate, and by using the untransformed clip planes in ctx->Transform.EyeUserPlane rather than the transformed clip planes in ctx->Transform._ClipUserPlane when a GLSL-based vertex shader is in use. When not using a GLSL-based vertex shader, we use ctx->Transform._ClipUserPlane (which is what we used prior to this patch). This ensures that clipping is still performed correctly for fixed function and ARB vertex programs. A new function, brw_select_clip_planes() is used to determine whether to use _ClipUserPlane or EyeUserPlane, so that the logic for making this decision is shared between the new and old vertex shaders. Fixes the following Piglit tests on i965 Gen6: - vs-clip-vertex-const-accept - vs-clip-vertex-const-reject - vs-clip-vertex-different-from-position - vs-clip-vertex-equal-to-position - vs-clip-vertex-homogeneity - vs-clip-based-on-position - vs-clip-based-on-position-homogeneity - clip-plane-transformation clipvert_pos - clip-plane-transformation pos_clipvert - clip-plane-transformation pos Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chad Versace <chad@chad-versace.us>
2011-09-26 21:43:04 +01:00
/* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
*
* "If a linked set of shaders forming the vertex stage contains no
* static write to gl_ClipVertex or gl_ClipDistance, but the
* application has requested clipping against user clip planes through
* the API, then the coordinate written to gl_Position is used for
* comparison against the user clip planes."
*
* This function is only called if the shader didn't write to
* gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
* if the user wrote to it; otherwise we use gl_Position.
*/
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
gl_varying_slot clip_vertex = VARYING_SLOT_CLIP_VERTEX;
i965/vs: move VS-specific data members to vs_vec4_visitor. This patch moves the following data structures from vec4_visitor to vec4_vs_visitor, since they contain VS-specific data: - struct brw_vs_compile *c (renamed to vs_compile) - struct brw_vs_prog_data *prog_data (renamed to vs_prog_data) - src_reg *vp_temp_regs - src_reg vp_addr_reg Since brw_vs_compile and brw_vs_prog_data also contain vec4-generic data, the following pointers are added to the base class, to allow it to access the vec4-generic portions of these data structures: - struct brw_vec4_compile *c - struct brw_vec4_prog_key *key - struct brw_vec4_prog_data *prog_data Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> v2: Use shorter names in the base class and longer names in the derived class. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-17 17:09:45 +00:00
if (!(prog_data->vue_map.slots_valid & VARYING_BIT_CLIP_VERTEX)) {
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
clip_vertex = VARYING_SLOT_POS;
i965 Gen6: Implement gl_ClipVertex. This patch implements proper support for gl_ClipVertex by causing the new VS backend to populate the clip distance VUE slots using VERT_RESULT_CLIP_VERTEX when appropriate, and by using the untransformed clip planes in ctx->Transform.EyeUserPlane rather than the transformed clip planes in ctx->Transform._ClipUserPlane when a GLSL-based vertex shader is in use. When not using a GLSL-based vertex shader, we use ctx->Transform._ClipUserPlane (which is what we used prior to this patch). This ensures that clipping is still performed correctly for fixed function and ARB vertex programs. A new function, brw_select_clip_planes() is used to determine whether to use _ClipUserPlane or EyeUserPlane, so that the logic for making this decision is shared between the new and old vertex shaders. Fixes the following Piglit tests on i965 Gen6: - vs-clip-vertex-const-accept - vs-clip-vertex-const-reject - vs-clip-vertex-different-from-position - vs-clip-vertex-equal-to-position - vs-clip-vertex-homogeneity - vs-clip-based-on-position - vs-clip-based-on-position-homogeneity - clip-plane-transformation clipvert_pos - clip-plane-transformation pos_clipvert - clip-plane-transformation pos Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chad Versace <chad@chad-versace.us>
2011-09-26 21:43:04 +01:00
}
i965/vs: move VS-specific data members to vs_vec4_visitor. This patch moves the following data structures from vec4_visitor to vec4_vs_visitor, since they contain VS-specific data: - struct brw_vs_compile *c (renamed to vs_compile) - struct brw_vs_prog_data *prog_data (renamed to vs_prog_data) - src_reg *vp_temp_regs - src_reg vp_addr_reg Since brw_vs_compile and brw_vs_prog_data also contain vec4-generic data, the following pointers are added to the base class, to allow it to access the vec4-generic portions of these data structures: - struct brw_vec4_compile *c - struct brw_vec4_prog_key *key - struct brw_vec4_prog_data *prog_data Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> v2: Use shorter names in the base class and longer names in the derived class. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-17 17:09:45 +00:00
for (int i = 0; i + offset < key->nr_userclip_plane_consts && i < 4;
i965 Gen6+: De-compact clip planes. Previously, if the user enabled a non-consecutive set of clip planes (e.g. 0, 1, and 3), the driver would compact them down to a consecutive set starting at 0. This optimization was of dubious value, and complicated the implementation of gl_ClipDistance. This patch changes the driver so that with Gen6 and later chipsets, we no longer compact the clip planes. However, we still discard any clip planes beyond the highest number that is in use, so performance should not be affected for applications that use clip planes consecutively from 0. With chipsets previous to Gen6, we still compact the clip planes, since the pre-Gen6 clipper thread relies on this behavior. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-27 20:57:08 +01:00
++i) {
i965/vs: Do legacy clip lowering earlier We need to produce clip flags for the vertex header on Gen4/5, so clip plane lowering has to be done before we try to emit the flags/psiz attribute. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-07-07 17:21:08 +01:00
reg.writemask = 1 << i;
emit(DP4(reg,
i965 Gen6: Implement gl_ClipVertex. This patch implements proper support for gl_ClipVertex by causing the new VS backend to populate the clip distance VUE slots using VERT_RESULT_CLIP_VERTEX when appropriate, and by using the untransformed clip planes in ctx->Transform.EyeUserPlane rather than the transformed clip planes in ctx->Transform._ClipUserPlane when a GLSL-based vertex shader is in use. When not using a GLSL-based vertex shader, we use ctx->Transform._ClipUserPlane (which is what we used prior to this patch). This ensures that clipping is still performed correctly for fixed function and ARB vertex programs. A new function, brw_select_clip_planes() is used to determine whether to use _ClipUserPlane or EyeUserPlane, so that the logic for making this decision is shared between the new and old vertex shaders. Fixes the following Piglit tests on i965 Gen6: - vs-clip-vertex-const-accept - vs-clip-vertex-const-reject - vs-clip-vertex-different-from-position - vs-clip-vertex-equal-to-position - vs-clip-vertex-homogeneity - vs-clip-based-on-position - vs-clip-based-on-position-homogeneity - clip-plane-transformation clipvert_pos - clip-plane-transformation pos_clipvert - clip-plane-transformation pos Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chad Versace <chad@chad-versace.us>
2011-09-26 21:43:04 +01:00
src_reg(output_reg[clip_vertex]),
i965 new VS: don't share clip plane constants in pre-GEN6 In pre-GEN6, when using clip planes, both the vertex shader and the clipper need access to the client-supplied clip planes, since the vertex shader needs them to set the clip flags, and the clipper needs them to determine where to insert new vertices. With the old VS backend, we used a clever optimization to avoid placing duplicate copies of these planes in the CURBE: we used the same block of memory for both the clipper and vertex shader constants, with the clip planes at the front of it, and then we instructed the clipper to read just the initial part of this block containing the clip planes. This optimization was tricky, of dubious value, and not completely working in the new VS backend, so I've removed it. Now, when using the new VS backend, separate parts of the CURBE are used for the clipper and the vertex shader. Note that this doesn't affect the number of push constants available to the vertex shader, it simply causes the CURBE to occupy a few more bytes of URB memory. The old VS backend is unaffected. GEN6+, which does clipping entirely in hardware, is also unaffected. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-09-24 05:33:50 +01:00
src_reg(this->userplane[i + offset])));
i965: new VS: move clip distance computation (GEN5+) to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:41:31 +01:00
}
}
i965/vs: Handle vertex color clamping in emit_urb_slot(). Vertex color clamping only applies to a few specific built-ins: COL0/1 and BFC0/1 (aka gl_[Secondary]{Front,Back}Color). It seems weird to handle special cases in a function called emit_generic_urb_slot(). emit_urb_slot() is all about handling special cases, so it makes more sense to handle this there. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-12-01 08:53:02 +00:00
vec4_instruction *
i965: Clarify nomenclature: vert_result -> varying This patch removes the terminology "vert_result" from the i965 driver, replacing it with "varying". The old terminology, "vert_result", was confusing because (a) it referred to the enum gl_vert_result, which no longer exists (it was replaced with gl_varying_slot), and (b) it implied a vertex output, but with the advent of geometry shaders, it could be either a vertex or a geometry output, depending what shaders are in use. The generic term "varying" is less confusing. No functional change. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> v2: Whitespace fixes.
2013-03-22 16:39:11 +00:00
vec4_visitor::emit_generic_urb_slot(dst_reg reg, int varying)
i965: Set up clip distance VUE slots appropriately for gl_ClipDistance. When gl_ClipDistance is in use, the contents of the gl_ClipDistance array just need to be copied directly into the clip distance VUE slots, so we re-use the code that copies all other generic VUE slots (this has been extracted to its own method). When gl_ClipDistance is not in use, the vertex shader needs to calculate the clip distances based on user-specified clipping planes. This patch also removes the i965-specific enum values BRW_VERT_RESULT_CLIP[01], since we now have generic Mesa enums that serve the same purpose (VERT_RESULT_CLIP_DIST[01]). Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-02 20:36:09 +01:00
{
i965: Clarify nomenclature: vert_result -> varying This patch removes the terminology "vert_result" from the i965 driver, replacing it with "varying". The old terminology, "vert_result", was confusing because (a) it referred to the enum gl_vert_result, which no longer exists (it was replaced with gl_varying_slot), and (b) it implied a vertex output, but with the advent of geometry shaders, it could be either a vertex or a geometry output, depending what shaders are in use. The generic term "varying" is less confusing. No functional change. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> v2: Whitespace fixes.
2013-03-22 16:39:11 +00:00
assert (varying < VARYING_SLOT_MAX);
reg.type = output_reg[varying].type;
current_annotation = output_reg_annotation[varying];
i965: Set up clip distance VUE slots appropriately for gl_ClipDistance. When gl_ClipDistance is in use, the contents of the gl_ClipDistance array just need to be copied directly into the clip distance VUE slots, so we re-use the code that copies all other generic VUE slots (this has been extracted to its own method). When gl_ClipDistance is not in use, the vertex shader needs to calculate the clip distances based on user-specified clipping planes. This patch also removes the i965-specific enum values BRW_VERT_RESULT_CLIP[01], since we now have generic Mesa enums that serve the same purpose (VERT_RESULT_CLIP_DIST[01]). Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-02 20:36:09 +01:00
/* Copy the register, saturating if necessary */
i965/vs: Handle vertex color clamping in emit_urb_slot(). Vertex color clamping only applies to a few specific built-ins: COL0/1 and BFC0/1 (aka gl_[Secondary]{Front,Back}Color). It seems weird to handle special cases in a function called emit_generic_urb_slot(). emit_urb_slot() is all about handling special cases, so it makes more sense to handle this there. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-12-01 08:53:02 +00:00
return emit(MOV(reg, src_reg(output_reg[varying])));
i965: Set up clip distance VUE slots appropriately for gl_ClipDistance. When gl_ClipDistance is in use, the contents of the gl_ClipDistance array just need to be copied directly into the clip distance VUE slots, so we re-use the code that copies all other generic VUE slots (this has been extracted to its own method). When gl_ClipDistance is not in use, the vertex shader needs to calculate the clip distances based on user-specified clipping planes. This patch also removes the i965-specific enum values BRW_VERT_RESULT_CLIP[01], since we now have generic Mesa enums that serve the same purpose (VERT_RESULT_CLIP_DIST[01]). Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-02 20:36:09 +01:00
}
i965: new VS: use the VUE map to write out vertex attributes. Previously, the new VS backend used two functions, emit_vue_header_gen6() and emit_vue_header_gen4() to emit the fixed parts of the VUE, and then a pair of carefully-constructed loops to emit the rest of the VUE, leaving out the parts that were already emitted as part of the header. This patch changes the new VS backend to use the VUE map to emit the entire VUE. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 19:07:56 +01:00
void
i965: Generalize emit_urb_slot() to emit to any dst_reg. In gen7+ we emit vertices as they come, however in gen6 geometry shaders we have to buffer vertex data for all vertices and then emit it all in one go at the end. To achieve this we need to generalize emit_urb_slot() to store vertex data in general purpose registers and not only MRF registers. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-17 15:59:10 +01:00
vec4_visitor::emit_urb_slot(dst_reg reg, int varying)
i965: new VS: Move PSIZ/flags computation to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 18:29:48 +01:00
{
i965/vs: Do VUE writes using the MRF file instead of hardware register. We'll only do compute-to-MRF on accesses to this file.
2011-09-06 20:32:33 +01:00
reg.type = BRW_REGISTER_TYPE_F;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965: Clarify nomenclature: vert_result -> varying This patch removes the terminology "vert_result" from the i965 driver, replacing it with "varying". The old terminology, "vert_result", was confusing because (a) it referred to the enum gl_vert_result, which no longer exists (it was replaced with gl_varying_slot), and (b) it implied a vertex output, but with the advent of geometry shaders, it could be either a vertex or a geometry output, depending what shaders are in use. The generic term "varying" is less confusing. No functional change. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> v2: Whitespace fixes.
2013-03-22 16:39:11 +00:00
switch (varying) {
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
case VARYING_SLOT_PSIZ:
i965: Generalize emit_urb_slot() to emit to any dst_reg. In gen7+ we emit vertices as they come, however in gen6 geometry shaders we have to buffer vertex data for all vertices and then emit it all in one go at the end. To achieve this we need to generalize emit_urb_slot() to store vertex data in general purpose registers and not only MRF registers. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-17 15:59:10 +01:00
{
i965: new VS: use the VUE map to write out vertex attributes. Previously, the new VS backend used two functions, emit_vue_header_gen6() and emit_vue_header_gen4() to emit the fixed parts of the VUE, and then a pair of carefully-constructed loops to emit the rest of the VUE, leaving out the parts that were already emitted as part of the header. This patch changes the new VS backend to use the VUE map to emit the entire VUE. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 19:07:56 +01:00
/* PSIZ is always in slot 0, and is coupled with other flags. */
current_annotation = "indices, point width, clip flags";
i965: Generalize emit_urb_slot() to emit to any dst_reg. In gen7+ we emit vertices as they come, however in gen6 geometry shaders we have to buffer vertex data for all vertices and then emit it all in one go at the end. To achieve this we need to generalize emit_urb_slot() to store vertex data in general purpose registers and not only MRF registers. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-17 15:59:10 +01:00
emit_psiz_and_flags(reg);
i965: new VS: use the VUE map to write out vertex attributes. Previously, the new VS backend used two functions, emit_vue_header_gen6() and emit_vue_header_gen4() to emit the fixed parts of the VUE, and then a pair of carefully-constructed loops to emit the rest of the VUE, leaving out the parts that were already emitted as part of the header. This patch changes the new VS backend to use the VUE map to emit the entire VUE. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 19:07:56 +01:00
break;
i965: Generalize emit_urb_slot() to emit to any dst_reg. In gen7+ we emit vertices as they come, however in gen6 geometry shaders we have to buffer vertex data for all vertices and then emit it all in one go at the end. To achieve this we need to generalize emit_urb_slot() to store vertex data in general purpose registers and not only MRF registers. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-17 15:59:10 +01:00
}
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
case BRW_VARYING_SLOT_NDC:
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
current_annotation = "NDC";
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
emit(MOV(reg, src_reg(output_reg[BRW_VARYING_SLOT_NDC])));
i965: new VS: use the VUE map to write out vertex attributes. Previously, the new VS backend used two functions, emit_vue_header_gen6() and emit_vue_header_gen4() to emit the fixed parts of the VUE, and then a pair of carefully-constructed loops to emit the rest of the VUE, leaving out the parts that were already emitted as part of the header. This patch changes the new VS backend to use the VUE map to emit the entire VUE. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 19:07:56 +01:00
break;
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
case VARYING_SLOT_POS:
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
current_annotation = "gl_Position";
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
emit(MOV(reg, src_reg(output_reg[VARYING_SLOT_POS])));
i965: new VS: use the VUE map to write out vertex attributes. Previously, the new VS backend used two functions, emit_vue_header_gen6() and emit_vue_header_gen4() to emit the fixed parts of the VUE, and then a pair of carefully-constructed loops to emit the rest of the VUE, leaving out the parts that were already emitted as part of the header. This patch changes the new VS backend to use the VUE map to emit the entire VUE. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 19:07:56 +01:00
break;
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
case VARYING_SLOT_EDGE:
i965/vs: Add support for copying user edge flags. Fixes the glsl skinning demo regression since changing to the new GLSL compiler, and is part of fixing piglit gl-2.0-edgeflag. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50079 NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-27 20:57:56 +01:00
/* This is present when doing unfilled polygons. We're supposed to copy
* the edge flag from the user-provided vertex array
* (glEdgeFlagPointer), or otherwise we'll copy from the current value
* of that attribute (starts as 1.0f). This is then used in clipping to
* determine which edges should be drawn as wireframe.
*/
current_annotation = "edge flag";
emit(MOV(reg, src_reg(dst_reg(ATTR, VERT_ATTRIB_EDGEFLAG,
glsl_type::float_type, WRITEMASK_XYZW))));
break;
Replace gl_vert_result enum with gl_varying_slot. This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
2013-02-23 15:22:01 +00:00
case BRW_VARYING_SLOT_PAD:
i965: new VS: use the VUE map to write out vertex attributes. Previously, the new VS backend used two functions, emit_vue_header_gen6() and emit_vue_header_gen4() to emit the fixed parts of the VUE, and then a pair of carefully-constructed loops to emit the rest of the VUE, leaving out the parts that were already emitted as part of the header. This patch changes the new VS backend to use the VUE map to emit the entire VUE. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 19:07:56 +01:00
/* No need to write to this slot */
break;
i965/vs: Handle vertex color clamping in emit_urb_slot(). Vertex color clamping only applies to a few specific built-ins: COL0/1 and BFC0/1 (aka gl_[Secondary]{Front,Back}Color). It seems weird to handle special cases in a function called emit_generic_urb_slot(). emit_urb_slot() is all about handling special cases, so it makes more sense to handle this there. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-12-01 08:53:02 +00:00
case VARYING_SLOT_COL0:
case VARYING_SLOT_COL1:
case VARYING_SLOT_BFC0:
case VARYING_SLOT_BFC1: {
i965: Make vertex color clamp handling code VS specific. Vertex color clamping only applies to gl_[Secondary]{Front,Back}Color, which are compatibility-only built-in varyings. We only support GS in core profile, so they can't exist in geometry shaders. We can drop several dirty bits from the GS program key - they're unnecessary for a core profile implementation. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-12-01 09:01:02 +00:00
/* These built-in varyings are only supported in compatibility mode,
* and we only support GS in core profile. So, this must be a vertex
* shader.
*/
assert(stage == MESA_SHADER_VERTEX);
i965/vs: Handle vertex color clamping in emit_urb_slot(). Vertex color clamping only applies to a few specific built-ins: COL0/1 and BFC0/1 (aka gl_[Secondary]{Front,Back}Color). It seems weird to handle special cases in a function called emit_generic_urb_slot(). emit_urb_slot() is all about handling special cases, so it makes more sense to handle this there. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-12-01 08:53:02 +00:00
vec4_instruction *inst = emit_generic_urb_slot(reg, varying);
i965: Make vertex color clamp handling code VS specific. Vertex color clamping only applies to gl_[Secondary]{Front,Back}Color, which are compatibility-only built-in varyings. We only support GS in core profile, so they can't exist in geometry shaders. We can drop several dirty bits from the GS program key - they're unnecessary for a core profile implementation. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-12-01 09:01:02 +00:00
if (((struct brw_vs_prog_key *) key)->clamp_vertex_color)
i965/vs: Handle vertex color clamping in emit_urb_slot(). Vertex color clamping only applies to a few specific built-ins: COL0/1 and BFC0/1 (aka gl_[Secondary]{Front,Back}Color). It seems weird to handle special cases in a function called emit_generic_urb_slot(). emit_urb_slot() is all about handling special cases, so it makes more sense to handle this there. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-12-01 08:53:02 +00:00
inst->saturate = true;
break;
}
i965: Set up clip distance VUE slots appropriately for gl_ClipDistance. When gl_ClipDistance is in use, the contents of the gl_ClipDistance array just need to be copied directly into the clip distance VUE slots, so we re-use the code that copies all other generic VUE slots (this has been extracted to its own method). When gl_ClipDistance is not in use, the vertex shader needs to calculate the clip distances based on user-specified clipping planes. This patch also removes the i965-specific enum values BRW_VERT_RESULT_CLIP[01], since we now have generic Mesa enums that serve the same purpose (VERT_RESULT_CLIP_DIST[01]). Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-02 20:36:09 +01:00
default:
i965: Clarify nomenclature: vert_result -> varying This patch removes the terminology "vert_result" from the i965 driver, replacing it with "varying". The old terminology, "vert_result", was confusing because (a) it referred to the enum gl_vert_result, which no longer exists (it was replaced with gl_varying_slot), and (b) it implied a vertex output, but with the advent of geometry shaders, it could be either a vertex or a geometry output, depending what shaders are in use. The generic term "varying" is less confusing. No functional change. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> v2: Whitespace fixes.
2013-03-22 16:39:11 +00:00
emit_generic_urb_slot(reg, varying);
i965: new VS: use the VUE map to write out vertex attributes. Previously, the new VS backend used two functions, emit_vue_header_gen6() and emit_vue_header_gen4() to emit the fixed parts of the VUE, and then a pair of carefully-constructed loops to emit the rest of the VUE, leaving out the parts that were already emitted as part of the header. This patch changes the new VS backend to use the VUE map to emit the entire VUE. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 19:07:56 +01:00
break;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
}
static int
align_interleaved_urb_mlen(struct brw_context *brw, int mlen)
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 6) {
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
/* URB data written (does not include the message header reg) must
* be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
* section 5.4.3.2.2: URB_INTERLEAVED.
*
* URB entries are allocated on a multiple of 1024 bits, so an
* extra 128 bits written here to make the end align to 256 is
* no problem.
*/
if ((mlen % 2) != 1)
mlen++;
}
return mlen;
}
i965/vs: Generalize vertex emission code in preparation for GS. This patch introduces a new function, vec4_visitor::emit_vertex(), which contains the code for emitting vertices that will need to be common between the vertex and geometry shaders. Geometry shaders will need to use a different message header, and a different opcode, for their URB writes, so we introduce virtual functions emit_urb_write_header() and emit_urb_write_opcode() to take care of the GS-specific behaviours. Also, since vertex emission happens at the end of the VS, but in the middle of the GS, we need to be sure to only call emit_shader_time_end() during VS vertex emission. We accomplish this by moving the call to emit_shader_time_end() into the VS implementation of emit_urb_write_opcode(). Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-22 13:59:52 +00:00
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
/**
i965/vs: Generalize vertex emission code in preparation for GS. This patch introduces a new function, vec4_visitor::emit_vertex(), which contains the code for emitting vertices that will need to be common between the vertex and geometry shaders. Geometry shaders will need to use a different message header, and a different opcode, for their URB writes, so we introduce virtual functions emit_urb_write_header() and emit_urb_write_opcode() to take care of the GS-specific behaviours. Also, since vertex emission happens at the end of the VS, but in the middle of the GS, we need to be sure to only call emit_shader_time_end() during VS vertex emission. We accomplish this by moving the call to emit_shader_time_end() into the VS implementation of emit_urb_write_opcode(). Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-22 13:59:52 +00:00
* Generates the VUE payload plus the necessary URB write instructions to
* output it.
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
*
* The VUE layout is documented in Volume 2a.
*/
void
i965/vs: Generalize vertex emission code in preparation for GS. This patch introduces a new function, vec4_visitor::emit_vertex(), which contains the code for emitting vertices that will need to be common between the vertex and geometry shaders. Geometry shaders will need to use a different message header, and a different opcode, for their URB writes, so we introduce virtual functions emit_urb_write_header() and emit_urb_write_opcode() to take care of the GS-specific behaviours. Also, since vertex emission happens at the end of the VS, but in the middle of the GS, we need to be sure to only call emit_shader_time_end() during VS vertex emission. We accomplish this by moving the call to emit_shader_time_end() into the VS implementation of emit_urb_write_opcode(). Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-22 13:59:52 +00:00
vec4_visitor::emit_vertex()
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
i965/vs: Reserve MRF 14/15 for array loads/register unspilling.
2011-08-07 23:21:25 +01:00
/* MRF 0 is reserved for the debugger, so start with message header
* in MRF 1.
*/
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
int base_mrf = 1;
int mrf = base_mrf;
i965/vs: Reserve MRF 14/15 for array loads/register unspilling.
2011-08-07 23:21:25 +01:00
/* In the process of generating our URB write message contents, we
* may need to unspill a register or load from an array. Those
* reads would use MRFs 14-15.
*/
int max_usable_mrf = 13;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965: new VS: Clarify comments about max_usable_mrf and add an assertion. max_usable_mrf has been carefully set such that (max_usable_mrf - base_mrf) is a multiple of 2, so that an even number of VUE slots are emitted with each URB write (which Gen6 requires). This patch adds an assertion to confirm that this is the case, and moves the comment to this effect to be near the assertion. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 19:41:41 +01:00
/* The following assertion verifies that max_usable_mrf causes an
* even-numbered amount of URB write data, which will meet gen6's
* requirements for length alignment.
*/
assert ((max_usable_mrf - base_mrf) % 2 == 0);
i965/vs: Generalize vertex emission code in preparation for GS. This patch introduces a new function, vec4_visitor::emit_vertex(), which contains the code for emitting vertices that will need to be common between the vertex and geometry shaders. Geometry shaders will need to use a different message header, and a different opcode, for their URB writes, so we introduce virtual functions emit_urb_write_header() and emit_urb_write_opcode() to take care of the GS-specific behaviours. Also, since vertex emission happens at the end of the VS, but in the middle of the GS, we need to be sure to only call emit_shader_time_end() during VS vertex emission. We accomplish this by moving the call to emit_shader_time_end() into the VS implementation of emit_urb_write_opcode(). Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-22 13:59:52 +00:00
/* First mrf is the g0-based message header containing URB handles and
* such.
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
*/
i965/vs: Generalize vertex emission code in preparation for GS. This patch introduces a new function, vec4_visitor::emit_vertex(), which contains the code for emitting vertices that will need to be common between the vertex and geometry shaders. Geometry shaders will need to use a different message header, and a different opcode, for their URB writes, so we introduce virtual functions emit_urb_write_header() and emit_urb_write_opcode() to take care of the GS-specific behaviours. Also, since vertex emission happens at the end of the VS, but in the middle of the GS, we need to be sure to only call emit_shader_time_end() during VS vertex emission. We accomplish this by moving the call to emit_shader_time_end() into the VS implementation of emit_urb_write_opcode(). Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-22 13:59:52 +00:00
emit_urb_write_header(mrf++);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen < 6) {
i965: new VS: use the VUE map to write out vertex attributes. Previously, the new VS backend used two functions, emit_vue_header_gen6() and emit_vue_header_gen4() to emit the fixed parts of the VUE, and then a pair of carefully-constructed loops to emit the rest of the VUE, leaving out the parts that were already emitted as part of the header. This patch changes the new VS backend to use the VUE map to emit the entire VUE. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-23 19:07:56 +01:00
emit_ndc_computation();
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Do legacy clip lowering earlier We need to produce clip flags for the vertex header on Gen4/5, so clip plane lowering has to be done before we try to emit the flags/psiz attribute. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-07-07 17:21:08 +01:00
/* Lower legacy ff and ClipVertex clipping to clip distances */
i965/vec4: Remove uses_clip_distance from program key. This should never have been in the program key in the first place, since it's determined by the shader source, not by GL state. Change the code to just refer to gl_program::UsesClipDistanceOut directly. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-10-23 19:10:14 +01:00
if (key->userclip_active && !prog->UsesClipDistanceOut) {
i965/vs: Do legacy clip lowering earlier We need to produce clip flags for the vertex header on Gen4/5, so clip plane lowering has to be done before we try to emit the flags/psiz attribute. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-07-07 17:21:08 +01:00
current_annotation = "user clip distances";
output_reg[VARYING_SLOT_CLIP_DIST0] = dst_reg(this, glsl_type::vec4_type);
output_reg[VARYING_SLOT_CLIP_DIST1] = dst_reg(this, glsl_type::vec4_type);
emit_clip_distances(output_reg[VARYING_SLOT_CLIP_DIST0], 0);
emit_clip_distances(output_reg[VARYING_SLOT_CLIP_DIST1], 4);
}
i965/vec4: Generate URB writes using a loop. Previously we only ever did 1 or 2 URB writes, since the maximum number of varyings we support is small enough to fit in 2 URB writes. But GL 3.2 requires the geometry shader to support 128 output varying components, and this could require up to 3 URB writes. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-03 20:30:06 +01:00
/* We may need to split this up into several URB writes, so do them in a
* loop.
*/
int slot = 0;
bool complete = false;
do {
/* URB offset is in URB row increments, and each of our MRFs is half of
* one of those, since we're doing interleaved writes.
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
*/
i965/vec4: Generate URB writes using a loop. Previously we only ever did 1 or 2 URB writes, since the maximum number of varyings we support is small enough to fit in 2 URB writes. But GL 3.2 requires the geometry shader to support 128 output varying components, and this could require up to 3 URB writes. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-03 20:30:06 +01:00
int offset = slot / 2;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
i965/vs: Add support for VUEs larger than a single URB write. Fixes glsl-max-varyings.
2011-08-06 05:53:00 +01:00
mrf = base_mrf + 1;
i965/vs: move VS-specific data members to vs_vec4_visitor. This patch moves the following data structures from vec4_visitor to vec4_vs_visitor, since they contain VS-specific data: - struct brw_vs_compile *c (renamed to vs_compile) - struct brw_vs_prog_data *prog_data (renamed to vs_prog_data) - src_reg *vp_temp_regs - src_reg vp_addr_reg Since brw_vs_compile and brw_vs_prog_data also contain vec4-generic data, the following pointers are added to the base class, to allow it to access the vec4-generic portions of these data structures: - struct brw_vec4_compile *c - struct brw_vec4_prog_key *key - struct brw_vec4_prog_data *prog_data Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> v2: Use shorter names in the base class and longer names in the derived class. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-17 17:09:45 +00:00
for (; slot < prog_data->vue_map.num_slots; ++slot) {
i965: Generalize emit_urb_slot() to emit to any dst_reg. In gen7+ we emit vertices as they come, however in gen6 geometry shaders we have to buffer vertex data for all vertices and then emit it all in one go at the end. To achieve this we need to generalize emit_urb_slot() to store vertex data in general purpose registers and not only MRF registers. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-17 15:59:10 +01:00
emit_urb_slot(dst_reg(MRF, mrf++),
prog_data->vue_map.slot_to_varying[slot]);
i965/vec4: Generate URB writes using a loop. Previously we only ever did 1 or 2 URB writes, since the maximum number of varyings we support is small enough to fit in 2 URB writes. But GL 3.2 requires the geometry shader to support 128 output varying components, and this could require up to 3 URB writes. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-03 20:30:06 +01:00
/* If this was max_usable_mrf, we can't fit anything more into this
* URB WRITE.
*/
if (mrf > max_usable_mrf) {
slot++;
break;
}
i965/vs: Add support for VUEs larger than a single URB write. Fixes glsl-max-varyings.
2011-08-06 05:53:00 +01:00
}
i965/vec4: Generate URB writes using a loop. Previously we only ever did 1 or 2 URB writes, since the maximum number of varyings we support is small enough to fit in 2 URB writes. But GL 3.2 requires the geometry shader to support 128 output varying components, and this could require up to 3 URB writes. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-03 20:30:06 +01:00
complete = slot >= prog_data->vue_map.num_slots;
i965/vs: Add annotation to more of the URB write. While we had nice debug output for most of the instruction stream, it was terminated by a series of anonymous MOVs and a send. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-09-06 21:29:21 +01:00
current_annotation = "URB write";
i965/vec4: Generate URB writes using a loop. Previously we only ever did 1 or 2 URB writes, since the maximum number of varyings we support is small enough to fit in 2 URB writes. But GL 3.2 requires the geometry shader to support 128 output varying components, and this could require up to 3 URB writes. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-03 20:30:06 +01:00
vec4_instruction *inst = emit_urb_write_opcode(complete);
i965/vs: Add support for VUEs larger than a single URB write. Fixes glsl-max-varyings.
2011-08-06 05:53:00 +01:00
inst->base_mrf = base_mrf;
inst->mlen = align_interleaved_urb_mlen(brw, mrf - base_mrf);
i965/vec4: Generate URB writes using a loop. Previously we only ever did 1 or 2 URB writes, since the maximum number of varyings we support is small enough to fit in 2 URB writes. But GL 3.2 requires the geometry shader to support 128 output varying components, and this could require up to 3 URB writes. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-03 20:30:06 +01:00
inst->offset += offset;
} while(!complete);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
i965/vs: Generalize vertex emission code in preparation for GS. This patch introduces a new function, vec4_visitor::emit_vertex(), which contains the code for emitting vertices that will need to be common between the vertex and geometry shaders. Geometry shaders will need to use a different message header, and a different opcode, for their URB writes, so we introduce virtual functions emit_urb_write_header() and emit_urb_write_opcode() to take care of the GS-specific behaviours. Also, since vertex emission happens at the end of the VS, but in the middle of the GS, we need to be sure to only call emit_shader_time_end() during VS vertex emission. We accomplish this by moving the call to emit_shader_time_end() into the VS implementation of emit_urb_write_opcode(). Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-22 13:59:52 +00:00
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
src_reg
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
vec4_visitor::get_scratch_offset(bblock_t *block, vec4_instruction *inst,
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
src_reg *reladdr, int reg_offset)
{
/* Because we store the values to scratch interleaved like our
* vertex data, we need to scale the vec4 index by 2.
*/
int message_header_scale = 2;
/* Pre-gen6, the message header uses byte offsets instead of vec4
* (16-byte) offset units.
*/
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen < 6)
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
message_header_scale *= 16;
if (reladdr) {
src_reg index = src_reg(this, glsl_type::int_type);
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
emit_before(block, inst, ADD(dst_reg(index), *reladdr,
src_reg(reg_offset)));
emit_before(block, inst, MUL(dst_reg(index), index,
src_reg(message_header_scale)));
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
return index;
} else {
return src_reg(reg_offset * message_header_scale);
}
}
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
src_reg
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
vec4_visitor::get_pull_constant_offset(bblock_t * block, vec4_instruction *inst,
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
src_reg *reladdr, int reg_offset)
{
if (reladdr) {
src_reg index = src_reg(this, glsl_type::int_type);
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
emit_before(block, inst, ADD(dst_reg(index), *reladdr,
src_reg(reg_offset)));
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
/* Pre-gen6, the message header uses byte offsets instead of vec4
* (16-byte) offset units.
*/
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen < 6) {
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
emit_before(block, inst, MUL(dst_reg(index), index, src_reg(16)));
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
}
return index;
i965/vs: Always store pull constant offsets in GRFs on Gen8. We need to SEND from a GRF, and we can only obtain those prior to register allocation. This allows us to do pull constant loads without the MRF hack. v2: Reword comments (suggested by Paul). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-12-16 08:02:43 +00:00
} else if (brw->gen >= 8) {
/* Store the offset in a GRF so we can send-from-GRF. */
src_reg offset = src_reg(this, glsl_type::int_type);
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
emit_before(block, inst, MOV(dst_reg(offset), src_reg(reg_offset)));
i965/vs: Always store pull constant offsets in GRFs on Gen8. We need to SEND from a GRF, and we can only obtain those prior to register allocation. This allows us to do pull constant loads without the MRF hack. v2: Reword comments (suggested by Paul). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-12-16 08:02:43 +00:00
return offset;
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
} else {
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
int message_header_scale = brw->gen < 6 ? 16 : 1;
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
return src_reg(reg_offset * message_header_scale);
}
}
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
/**
* Emits an instruction before @inst to load the value named by @orig_src
* from scratch space at @base_offset to @temp.
i965/vs: Fix unit mismatch in scratch base_offset parameter. move_grf_array_access_to_scratch() calculates scratch buffer offsets in bytes. However, emit_scratch_read/write() expects the base_offset parameter to be measured in OWords. As a result, a shader using a scratch read/write offset greater than zero (in practice, a shader containing more than one variable in scratch) would use too large an offset, frequently exceeding the available scratch space. This patch corrects the mismatch by removing spurious conversion from OWords to bytes in move_grf_array_access_to_scratch(). This is based on a patch by Paul Berry. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-10-01 23:28:55 +01:00
*
* @base_offset is measured in 32-byte units (the size of a register).
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
*/
void
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
vec4_visitor::emit_scratch_read(bblock_t *block, vec4_instruction *inst,
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
dst_reg temp, src_reg orig_src,
int base_offset)
{
int reg_offset = base_offset + orig_src.reg_offset;
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
src_reg index = get_scratch_offset(block, inst, orig_src.reladdr,
reg_offset);
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
emit_before(block, inst, SCRATCH_READ(temp, index));
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
}
/**
* Emits an instruction after @inst to store the value to be written
* to @orig_dst to scratch space at @base_offset, from @temp.
i965/vs: Fix unit mismatch in scratch base_offset parameter. move_grf_array_access_to_scratch() calculates scratch buffer offsets in bytes. However, emit_scratch_read/write() expects the base_offset parameter to be measured in OWords. As a result, a shader using a scratch read/write offset greater than zero (in practice, a shader containing more than one variable in scratch) would use too large an offset, frequently exceeding the available scratch space. This patch corrects the mismatch by removing spurious conversion from OWords to bytes in move_grf_array_access_to_scratch(). This is based on a patch by Paul Berry. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-10-01 23:28:55 +01:00
*
* @base_offset is measured in 32-byte units (the size of a register).
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
*/
void
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
vec4_visitor::emit_scratch_write(bblock_t *block, vec4_instruction *inst,
int base_offset)
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
{
i965/vs: Simplify emit_scratch_write() prototype. Both callers used (effectively) inst->dst as the argument, so just reference it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-16 01:42:43 +01:00
int reg_offset = base_offset + inst->dst.reg_offset;
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
src_reg index = get_scratch_offset(block, inst, inst->dst.reladdr,
reg_offset);
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
i965/vs: Trim the swizzle of the scratch write temporary. This fixes confusion by the upcoming live variable analysis which saw e.g. use of temp.w when only temp.xyz were initialized in the basic block, and concluded that temp.w must have come from outside of the block (even though it was never initialized anywhere). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-16 01:51:59 +01:00
/* Create a temporary register to store *inst's result in.
*
* We have to be careful in MOVing from our temporary result register in
* the scratch write. If we swizzle from channels of the temporary that
* weren't initialized, it will confuse live interval analysis, which will
* make spilling fail to make progress.
*/
i965/vs: Do the temporary allocation in emit_scratch_write(). Both callers were doing basically the same thing, just written differently. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-16 01:48:07 +01:00
src_reg temp = src_reg(this, glsl_type::vec4_type);
temp.type = inst->dst.type;
i965/vs: Trim the swizzle of the scratch write temporary. This fixes confusion by the upcoming live variable analysis which saw e.g. use of temp.w when only temp.xyz were initialized in the basic block, and concluded that temp.w must have come from outside of the block (even though it was never initialized anywhere). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-16 01:51:59 +01:00
int first_writemask_chan = ffs(inst->dst.writemask) - 1;
int swizzles[4];
for (int i = 0; i < 4; i++)
if (inst->dst.writemask & (1 << i))
swizzles[i] = i;
else
swizzles[i] = first_writemask_chan;
temp.swizzle = BRW_SWIZZLE4(swizzles[0], swizzles[1],
swizzles[2], swizzles[3]);
i965/vs: Do the temporary allocation in emit_scratch_write(). Both callers were doing basically the same thing, just written differently. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-16 01:48:07 +01:00
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
dst_reg dst = dst_reg(brw_writemask(brw_vec8_grf(0, 0),
i965/vs: Simplify emit_scratch_write() prototype. Both callers used (effectively) inst->dst as the argument, so just reference it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-16 01:42:43 +01:00
inst->dst.writemask));
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-27 19:13:33 +01:00
vec4_instruction *write = SCRATCH_WRITE(dst, temp, index);
write->predicate = inst->predicate;
write->ir = inst->ir;
write->annotation = inst->annotation;
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
inst->insert_after(block, write);
i965/vs: Do the temporary allocation in emit_scratch_write(). Both callers were doing basically the same thing, just written differently. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-16 01:48:07 +01:00
inst->dst.file = temp.file;
inst->dst.reg = temp.reg;
inst->dst.reg_offset = temp.reg_offset;
inst->dst.reladdr = NULL;
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
}
/**
* We can't generally support array access in GRF space, because a
* single instruction's destination can only span 2 contiguous
* registers. So, we send all GRF arrays that get variable index
* access to scratch space.
*/
void
vec4_visitor::move_grf_array_access_to_scratch()
{
i965: Factor out virtual GRF allocation to a separate object. Right now virtual GRF book-keeping and allocation is performed in each visitor class separately (among other hundred different things), leading to duplicated logic in each visitor and preventing layering as it forces any code that manipulates i965 IR and needs to allocate virtual registers to depend on the specific visitor that happens to be used to translate from GLSL IR. v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor). Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-10 13:51:34 +00:00
int scratch_loc[this->alloc.count];
i965: Replace initialization loops with memset(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 05:51:28 +01:00
memset(scratch_loc, -1, sizeof(scratch_loc));
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
/* First, calculate the set of virtual GRFs that need to be punted
* to scratch due to having any array access on them, and where in
* scratch.
*/
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
if (inst->dst.file == GRF && inst->dst.reladdr &&
scratch_loc[inst->dst.reg] == -1) {
i965/vs: move VS-specific data members to vs_vec4_visitor. This patch moves the following data structures from vec4_visitor to vec4_vs_visitor, since they contain VS-specific data: - struct brw_vs_compile *c (renamed to vs_compile) - struct brw_vs_prog_data *prog_data (renamed to vs_prog_data) - src_reg *vp_temp_regs - src_reg vp_addr_reg Since brw_vs_compile and brw_vs_prog_data also contain vec4-generic data, the following pointers are added to the base class, to allow it to access the vec4-generic portions of these data structures: - struct brw_vec4_compile *c - struct brw_vec4_prog_key *key - struct brw_vec4_prog_data *prog_data Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> v2: Use shorter names in the base class and longer names in the derived class. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-17 17:09:45 +00:00
scratch_loc[inst->dst.reg] = c->last_scratch;
i965: Factor out virtual GRF allocation to a separate object. Right now virtual GRF book-keeping and allocation is performed in each visitor class separately (among other hundred different things), leading to duplicated logic in each visitor and preventing layering as it forces any code that manipulates i965 IR and needs to allocate virtual registers to depend on the specific visitor that happens to be used to translate from GLSL IR. v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor). Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-10 13:51:34 +00:00
c->last_scratch += this->alloc.sizes[inst->dst.reg];
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
}
for (int i = 0 ; i < 3; i++) {
src_reg *src = &inst->src[i];
if (src->file == GRF && src->reladdr &&
scratch_loc[src->reg] == -1) {
i965/vs: move VS-specific data members to vs_vec4_visitor. This patch moves the following data structures from vec4_visitor to vec4_vs_visitor, since they contain VS-specific data: - struct brw_vs_compile *c (renamed to vs_compile) - struct brw_vs_prog_data *prog_data (renamed to vs_prog_data) - src_reg *vp_temp_regs - src_reg vp_addr_reg Since brw_vs_compile and brw_vs_prog_data also contain vec4-generic data, the following pointers are added to the base class, to allow it to access the vec4-generic portions of these data structures: - struct brw_vec4_compile *c - struct brw_vec4_prog_key *key - struct brw_vec4_prog_data *prog_data Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> v2: Use shorter names in the base class and longer names in the derived class. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-17 17:09:45 +00:00
scratch_loc[src->reg] = c->last_scratch;
i965: Factor out virtual GRF allocation to a separate object. Right now virtual GRF book-keeping and allocation is performed in each visitor class separately (among other hundred different things), leading to duplicated logic in each visitor and preventing layering as it forces any code that manipulates i965 IR and needs to allocate virtual registers to depend on the specific visitor that happens to be used to translate from GLSL IR. v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor). Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-10 13:51:34 +00:00
c->last_scratch += this->alloc.sizes[src->reg];
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
}
}
}
/* Now, for anything that will be accessed through scratch, rewrite
* it to load/store. Note that this is a _safe list walk, because
* we may generate a new scratch_write instruction after the one
* we're processing.
*/
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
/* Set up the annotation tracking for new generated instructions. */
base_ir = inst->ir;
current_annotation = inst->annotation;
if (inst->dst.file == GRF && scratch_loc[inst->dst.reg] != -1) {
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
emit_scratch_write(block, inst, scratch_loc[inst->dst.reg]);
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
}
for (int i = 0 ; i < 3; i++) {
if (inst->src[i].file != GRF || scratch_loc[inst->src[i].reg] == -1)
continue;
dst_reg temp = dst_reg(this, glsl_type::vec4_type);
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
emit_scratch_read(block, inst, temp, inst->src[i],
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
scratch_loc[inst->src[i].reg]);
inst->src[i].file = temp.file;
inst->src[i].reg = temp.reg;
inst->src[i].reg_offset = temp.reg_offset;
inst->src[i].reladdr = NULL;
}
}
}
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
/**
* Emits an instruction before @inst to load the value named by @orig_src
* from the pull constant buffer (surface) at @base_offset to @temp.
*/
void
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
vec4_visitor::emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
dst_reg temp, src_reg orig_src,
int base_offset)
{
int reg_offset = base_offset + orig_src.reg_offset;
i965: Make a brw_stage_prog_data for storing the SURF_INDEX information. It would be nice to be able to pack our binding table so that programs that use 1 render target don't upload an extra BRW_MAX_DRAW_BUFFERS - 1 binding table entries. To do that, we need the compiled program to have information on where its surfaces go. v2: Rename size to size_bytes to be more explicit. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-02 22:07:40 +01:00
src_reg index = src_reg(prog_data->base.binding_table.pull_constants_start);
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
src_reg offset = get_pull_constant_offset(block, inst, orig_src.reladdr,
reg_offset);
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
vec4_instruction *load;
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 7) {
i965/vs: Use GRFs for pull constant offsets on gen7. This allows the computation of the offset to get written directly into the message source. shader-db results: total instructions in shared programs: 3308390 -> 3283025 (-0.77%) instructions in affected programs: 442998 -> 417633 (-5.73%) No difference in GLB2.7 low res (n=9). Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-04-04 22:10:18 +01:00
dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
grf_offset.type = offset.type;
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
emit_before(block, inst, MOV(grf_offset, offset));
i965/vs: Use GRFs for pull constant offsets on gen7. This allows the computation of the offset to get written directly into the message source. shader-db results: total instructions in shared programs: 3308390 -> 3283025 (-0.77%) instructions in affected programs: 442998 -> 417633 (-5.73%) No difference in GLB2.7 low res (n=9). Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-04-04 22:10:18 +01:00
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
load = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
i965/vs: Use GRFs for pull constant offsets on gen7. This allows the computation of the offset to get written directly into the message source. shader-db results: total instructions in shared programs: 3308390 -> 3283025 (-0.77%) instructions in affected programs: 442998 -> 417633 (-5.73%) No difference in GLB2.7 low res (n=9). Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-04-04 22:10:18 +01:00
temp, index, src_reg(grf_offset));
i965/vec4: Init mlen for several send from GRF instructions. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-03 20:52:37 +00:00
load->mlen = 1;
i965/vs: Use GRFs for pull constant offsets on gen7. This allows the computation of the offset to get written directly into the message source. shader-db results: total instructions in shared programs: 3308390 -> 3283025 (-0.77%) instructions in affected programs: 442998 -> 417633 (-5.73%) No difference in GLB2.7 low res (n=9). Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-04-04 22:10:18 +01:00
} else {
i965/vec4: Remove dependency of vec4_instruction on the visitor class. The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-05 23:25:50 +00:00
load = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD,
i965/vs: Use GRFs for pull constant offsets on gen7. This allows the computation of the offset to get written directly into the message source. shader-db results: total instructions in shared programs: 3308390 -> 3283025 (-0.77%) instructions in affected programs: 442998 -> 417633 (-5.73%) No difference in GLB2.7 low res (n=9). Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-04-04 22:10:18 +01:00
temp, index, offset);
load->base_mrf = 14;
load->mlen = 1;
}
i965/vec4: Preserve CFG in spill_reg(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 03:38:21 +01:00
emit_before(block, inst, load);
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
}
/**
* Implements array access of uniforms by inserting a
* PULL_CONSTANT_LOAD instruction.
*
* Unlike temporary GRF array access (where we don't support it due to
* the difficulty of doing relative addressing on instruction
* destinations), we could potentially do array access of uniforms
* that were loaded in GRF space as push constants. In real-world
* usage we've seen, though, the arrays being used are always larger
* than we could load as push constants, so just always move all
* uniform array access out to a pull constant buffer.
*/
void
vec4_visitor::move_uniform_array_access_to_pull_constants()
{
int pull_constant_loc[this->uniforms];
i965: Replace initialization loops with memset(). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-25 05:51:28 +01:00
memset(pull_constant_loc, -1, sizeof(pull_constant_loc));
i965: Handle nested uniform array indexing When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-18 08:15:06 +00:00
bool nested_reladdr;
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
/* Walk through and find array access of uniforms. Put a copy of that
* uniform in the pull constant buffer.
*
* Note that we don't move constant-indexed accesses to arrays. No
* testing has been done of the performance impact of this choice.
*/
i965: Handle nested uniform array indexing When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-18 08:15:06 +00:00
do {
nested_reladdr = false;
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
i965: Handle nested uniform array indexing When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-18 08:15:06 +00:00
foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
for (int i = 0 ; i < 3; i++) {
if (inst->src[i].file != UNIFORM || !inst->src[i].reladdr)
continue;
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
i965: Handle nested uniform array indexing When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-18 08:15:06 +00:00
int uniform = inst->src[i].reg;
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
i965: Handle nested uniform array indexing When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-18 08:15:06 +00:00
if (inst->src[i].reladdr->reladdr)
nested_reladdr = true; /* will need another pass */
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
i965: Handle nested uniform array indexing When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-18 08:15:06 +00:00
/* If this array isn't already present in the pull constant buffer,
* add it.
*/
if (pull_constant_loc[uniform] == -1) {
const gl_constant_value **values =
&stage_prog_data->param[uniform * 4];
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
i965: Handle nested uniform array indexing When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-18 08:15:06 +00:00
pull_constant_loc[uniform] = stage_prog_data->nr_pull_params / 4;
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
i965: Handle nested uniform array indexing When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-18 08:15:06 +00:00
assert(uniform < uniform_array_size);
for (int j = 0; j < uniform_size[uniform] * 4; j++) {
stage_prog_data->pull_param[stage_prog_data->nr_pull_params++]
= values[j];
}
}
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
i965: Handle nested uniform array indexing When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-18 08:15:06 +00:00
/* Set up the annotation tracking for new generated instructions. */
base_ir = inst->ir;
current_annotation = inst->annotation;
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
i965: Handle nested uniform array indexing When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-18 08:15:06 +00:00
dst_reg temp = dst_reg(this, glsl_type::vec4_type);
emit_pull_constant_load(block, inst, temp, inst->src[i],
pull_constant_loc[uniform]);
inst->src[i].file = temp.file;
inst->src[i].reg = temp.reg;
inst->src[i].reg_offset = temp.reg_offset;
inst->src[i].reladdr = NULL;
}
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
}
i965: Handle nested uniform array indexing When converting a uniform array reference to a pull constant load, the `reladdr` expression itself may have its own `reladdr`, arbitrarily deeply. This arises from expressions like: a[b[x]] where a, b are uniform arrays (or lowered const arrays), and x is not a constant. Just iterate the lowering to pull constants until we stop seeing these nested. For most shaders, there will be only one pass through this loop. Fixes the piglit test: tests/spec/glsl-1.20/linker/double-indirect-1.shader_test Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-18 08:15:06 +00:00
} while (nested_reladdr);
i965/vs: Track uniforms as separate vectors once we've done array access. This will make it easier to figure out which elements are totally unused and not upload them. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-23 18:22:50 +01:00
/* Now there are no accesses of the UNIFORM file with a reladdr, so
* no need to track them as larger-than-vec4 objects. This will be
* relied on in cutting out unused uniform vectors from push
* constants.
*/
split_uniform_registers();
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 18:35:24 +01:00
}
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
2011-08-07 20:15:26 +01:00
i965/vs: Fix comparisons with uint negation. The condmod instruction ends up generating garbage condition codes, because apparently the comparison happens on the accumulator value (33 bits for UD), not the truncated value that would be written. Fixes vs-op-neg-* Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-10-03 23:31:52 +01:00
void
vec4_visitor::resolve_ud_negate(src_reg *reg)
{
if (reg->type != BRW_REGISTER_TYPE_UD ||
!reg->negate)
return;
src_reg temp = src_reg(this, glsl_type::uvec4_type);
emit(BRW_OPCODE_MOV, dst_reg(temp), *reg);
*reg = temp;
}
i965: Use ~0 to represent true on all generations. Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-02 20:28:13 +00:00
/**
* Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
*
* CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
* If we need a proper boolean value, we have to fix it up to be 0 or ~0.
*/
void
vec4_visitor::resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg)
{
assert(brw->gen <= 5);
if (!rvalue->type->is_boolean())
return;
src_reg and_result = src_reg(this, rvalue->type);
src_reg neg_result = src_reg(this, rvalue->type);
emit(AND(dst_reg(and_result), *reg, src_reg(1)));
emit(MOV(dst_reg(neg_result), negate(and_result)));
*reg = neg_result;
}
i965/vs: Pass the brw_context pointer into vec4_visitor and do_vs_prog. We used to steal it out of the brw_compile struct...but vec4_visitor isn't going to have one of those in the future. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2012-11-27 06:14:27 +00:00
vec4_visitor::vec4_visitor(struct brw_context *brw,
i965/vs: move VS-specific data members to vs_vec4_visitor. This patch moves the following data structures from vec4_visitor to vec4_vs_visitor, since they contain VS-specific data: - struct brw_vs_compile *c (renamed to vs_compile) - struct brw_vs_prog_data *prog_data (renamed to vs_prog_data) - src_reg *vp_temp_regs - src_reg vp_addr_reg Since brw_vs_compile and brw_vs_prog_data also contain vec4-generic data, the following pointers are added to the base class, to allow it to access the vec4-generic portions of these data structures: - struct brw_vec4_compile *c - struct brw_vec4_prog_key *key - struct brw_vec4_prog_data *prog_data Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> v2: Use shorter names in the base class and longer names in the derived class. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-17 17:09:45 +00:00
struct brw_vec4_compile *c,
struct gl_program *prog,
i965: Rename brw_vec4_prog_data/key to brw_bue_prog_data/key These structs aren't vec4 specific, they are shared by shader stages operating on Vertex URB Entries (VUEs). VUEs are the data structures in the URB that hold vertex data between the pipeline geometry stages. Using vue in the name instead of vec4 makes a lot more sense, especially when we add scalar vertex shader support. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-25 22:29:48 +00:00
const struct brw_vue_prog_key *key,
struct brw_vue_prog_data *prog_data,
i965: Rename backend_visitor::prog to shader_prog. The next patch is going to change the type of vec4_visitor::vp from struct gl_vertex_program * to struct gl_program *, and rename it. The sensible name to change it to is vec4_visitor::prog. However, prog is already used in backend_visitor (which vec4_visitor derives from). Since backend_visitor::prog is of type struct gl_shader_program *, it makes sense to rename it to shader_prog. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-09 01:17:44 +01:00
struct gl_shader_program *shader_prog,
i965: Merge resolving of shader program source Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-02-18 20:50:13 +00:00
gl_shader_stage stage,
i965/vs: Don't hardcode DEBUG_VS in generic vec4 code. Since the vec4_visitor and vec4_generator classes are going to be re-used for geometry shaders, we can't enable their debug functionality based on (INTEL_DEBUG & DEBUG_VS) anymore. Instead, add a debug_flag boolean to these two classes, so that when they're instantiated the caller can specify whether debug dumps are needed. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-23 04:55:03 +00:00
void *mem_ctx,
i965: Add GS support to INTEL_DEBUG=shader_time. Previously, time spent in geometry shaders would be counted as part of the vertex shader time. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-01-17 22:42:48 +00:00
bool no_spills,
shader_time_shader_type st_base,
shader_time_shader_type st_written,
shader_time_shader_type st_reset)
i965: Merge resolving of shader program source Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-02-18 20:50:13 +00:00
: backend_visitor(brw, shader_prog, prog, &prog_data->base, stage),
i965: Merge initialisation of backend_visitor Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-02-14 09:54:02 +00:00
c(c),
i965/vec4: Mark invariant members as constants in vec4_visitor Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-02-15 08:26:09 +00:00
key(key),
prog_data(prog_data),
sanity_param_count(0),
i965: Initialize vec4_visitor member variables. Fixes "Uninitialized pointer field" defect reported by Coverity. Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-26 08:10:25 +01:00
fail_msg(NULL),
first_non_payload_grf(0),
need_all_constants_in_pull_buffer(false),
i965: Add GS support to INTEL_DEBUG=shader_time. Previously, time spent in geometry shaders would be counted as part of the vertex shader time. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-01-17 22:42:48 +00:00
no_spills(no_spills),
st_base(st_base),
st_written(st_written),
st_reset(st_reset)
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
{
i965/vs: Rework memory contexts for shader compilation data. During compilation, we allocate a bunch of things: the IR needs to last at least until code generation...and then the program store needs to last until after we upload the program. For simplicity's sake, just keep it all around until we upload the program. After that, it can all be freed. This will also save a lot of headaches during the upcoming refactoring. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2012-11-27 07:52:20 +00:00
this->mem_ctx = mem_ctx;
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
this->failed = false;
this->base_ir = NULL;
this->current_annotation = NULL;
i965/vp: Fix crashes with INTEL_DEBUG=vs. The VP generation doesn't set up the output reg strings, so if you didn't happen to get these values as 0 on the stack, you'd lose. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-30 21:02:11 +00:00
memset(this->output_reg_annotation, 0, sizeof(this->output_reg_annotation));
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
this->variable_ht = hash_table_ctor(0,
hash_table_pointer_hash,
hash_table_pointer_compare);
i965/vs: Make virtual grf live intervals actually cover their used range. This is the same change as the previous commit to the FS. A very few VSes are regressed by 1 or 2 instructions, which look recoverable with a bit more dead code elimination. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-04-30 23:15:21 +01:00
this->virtual_grf_start = NULL;
this->virtual_grf_end = NULL;
i965/vec4: Make live_intervals part of the vec4_visitor class. Like in fs_visitor. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-29 20:27:37 +00:00
this->live_intervals = NULL;
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
i965/vs: Avoid allocating registers in to the gen7 MRF hack region. This is the corresponding fix to the previous one for the FS, but I don't have a particular test for it. NOTE: This is a candidate for the 8.0 branch.
2012-01-27 20:59:24 +00:00
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
2011-05-04 20:50:16 +01:00
this->uniforms = 0;
i965: Allocate vec4_visitor's uniform_size and uniform_vector_size arrays dynamically. v2: Don't add function parameters, pass the required size in prog_data->nr_params. v3: - Use the name uniform_array_size instead of uniform_param_count. - Round up when dividing param_count by 4. - Use MAX2() instead of taking the maximum by hand. - Don't crash if prog_data passed to vec4_visitor constructor is NULL v4: Rebase for current master v5 (idr): Trivial whitespace change. Signed-off-by: Petri Latvala <petri.latvala@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71254 Cc: "10.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-27 14:15:04 +00:00
/* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
* at least one. See setup_uniforms() in brw_vec4.cpp.
*/
this->uniform_array_size = 1;
if (prog_data) {
this->uniform_array_size = MAX2(stage_prog_data->nr_params, 1);
}
this->uniform_size = rzalloc_array(mem_ctx, int, this->uniform_array_size);
this->uniform_vector_size = rzalloc_array(mem_ctx, int, this->uniform_array_size);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
}
vec4_visitor::~vec4_visitor()
{
hash_table_dtor(this->variable_ht);
}
void
vec4_visitor::fail(const char *format, ...)
{
va_list va;
char *msg;
if (failed)
return;
failed = true;
va_start(va, format);
msg = ralloc_vasprintf(mem_ctx, format, va);
va_end(va);
i965: Modify some error messages to refer to "vec4" instead of "vs". These messages are in code that is shared between the VS and GS back-ends, so use the terminology "vec4" to avoid confusion. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-23 14:22:08 +00:00
msg = ralloc_asprintf(mem_ctx, "vec4 compile failed: %s\n", msg);
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
this->fail_msg = msg;
i965/vec4: Replace debug_flag with debug_enabled. backend_visitor now handles this, so we can delete the vec4_visitor specific code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2015-02-19 01:50:42 +00:00
if (debug_enabled) {
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
2011-05-02 17:45:40 +01:00
fprintf(stderr, "%s", msg);
}
}
} /* namespace brw */