i965/vec4: Add support for nonconst sampler indexing in VS visitor
V2: Set force_writemask_all on ADD; this *is* necessary in the VS case too. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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@ -526,7 +526,7 @@ public:
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void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
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uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
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src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, uint32_t sampler);
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src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler);
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void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
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void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
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@ -2305,7 +2305,7 @@ vec4_visitor::visit(ir_call *ir)
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}
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src_reg
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vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg coordinate, uint32_t sampler)
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vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler)
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{
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vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXF_MCS);
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inst->base_mrf = 2;
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@ -2313,7 +2313,7 @@ vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg coordinate, uint32_t sample
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inst->dst = dst_reg(this, glsl_type::uvec4_type);
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inst->dst.writemask = WRITEMASK_XYZW;
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inst->src[1] = src_reg(sampler);
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inst->src[1] = sampler;
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/* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
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int param_base = inst->base_mrf;
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@ -2330,12 +2330,56 @@ vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg coordinate, uint32_t sample
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return src_reg(inst->dst);
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}
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static bool
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is_high_sampler(struct brw_context *brw, src_reg sampler)
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{
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if (brw->gen < 8 && !brw->is_haswell)
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return false;
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return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
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}
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void
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vec4_visitor::visit(ir_texture *ir)
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{
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uint32_t sampler =
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_mesa_get_sampler_uniform_value(ir->sampler, shader_prog, prog);
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ir_rvalue *nonconst_sampler_index =
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_mesa_get_sampler_array_nonconst_index(ir->sampler);
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/* Handle non-constant sampler array indexing */
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src_reg sampler_reg;
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if (nonconst_sampler_index) {
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/* The highest sampler which may be used by this operation is
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* the last element of the array. Mark it here, because the generator
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* doesn't have enough information to determine the bound.
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*/
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uint32_t array_size = ir->sampler->as_dereference_array()
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->array->type->array_size();
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uint32_t max_used = sampler + array_size - 1;
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if (ir->op == ir_tg4 && brw->gen < 8) {
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max_used += prog_data->base.binding_table.gather_texture_start;
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} else {
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max_used += prog_data->base.binding_table.texture_start;
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}
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brw_mark_surface_used(&prog_data->base, max_used);
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/* Emit code to evaluate the actual indexing expression */
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nonconst_sampler_index->accept(this);
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dst_reg temp(this, glsl_type::uint_type);
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emit(ADD(temp, this->result, src_reg(sampler)))
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->force_writemask_all = true;
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sampler_reg = src_reg(temp);
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} else {
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/* Single sampler, or constant array index; the indexing expression
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* is just an immediate.
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*/
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sampler_reg = src_reg(sampler);
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}
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/* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
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* emitting anything other than setting up the constant result.
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*/
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@ -2403,7 +2447,7 @@ vec4_visitor::visit(ir_texture *ir)
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sample_index_type = ir->lod_info.sample_index->type;
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if (brw->gen >= 7 && key->tex.compressed_multisample_layout_mask & (1<<sampler))
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mcs = emit_mcs_fetch(ir, coordinate, sampler);
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mcs = emit_mcs_fetch(ir, coordinate, sampler_reg);
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else
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mcs = src_reg(0u);
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break;
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@ -2458,14 +2502,14 @@ vec4_visitor::visit(ir_texture *ir)
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*/
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inst->header_present =
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brw->gen < 5 || inst->texture_offset != 0 || ir->op == ir_tg4 ||
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sampler >= 16;
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is_high_sampler(brw, sampler_reg);
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inst->base_mrf = 2;
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inst->mlen = inst->header_present + 1; /* always at least one */
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inst->dst = dst_reg(this, ir->type);
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inst->dst.writemask = WRITEMASK_XYZW;
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inst->shadow_compare = ir->shadow_comparitor != NULL;
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inst->src[1] = src_reg(sampler);
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inst->src[1] = sampler_reg;
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/* MRF for the first parameter */
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int param_base = inst->base_mrf + inst->header_present;
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