i965/vec4: Simplify visit(ir_expression *)'s result_src/dst setup.
Using dst_reg(this, ir->type) automatically sets the writemask to the proper size for the type; src_reg(dst_reg) preserves that. This should be equivalent, but less code. Note that src_reg(dst_reg) either uses SWIZZLE_XXXX or SWIZZLE_XYZW, so the old code did need the manual writemask adjustment, since it constructed the registers the other way around. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
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@ -1259,8 +1259,6 @@ vec4_visitor::visit(ir_expression *ir)
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{
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unsigned int operand;
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src_reg op[Elements(ir->operands)];
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src_reg result_src;
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dst_reg result_dst;
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vec4_instruction *inst;
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if (ir->operation == ir_binop_add) {
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@ -1273,6 +1271,12 @@ vec4_visitor::visit(ir_expression *ir)
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return;
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}
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/* Storage for our result. Ideally for an assignment we'd be using
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* the actual storage for the result here, instead.
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*/
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dst_reg result_dst(this, ir->type);
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src_reg result_src(result_dst);
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for (operand = 0; operand < ir->get_num_operands(); operand++) {
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this->result.file = BAD_FILE;
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ir->operands[operand]->accept(this);
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@ -1289,19 +1293,8 @@ vec4_visitor::visit(ir_expression *ir)
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assert(!ir->operands[operand]->type->is_matrix());
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}
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/* Storage for our result. Ideally for an assignment we'd be using
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* the actual storage for the result here, instead.
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*/
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result_src = src_reg(this, ir->type);
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/* convenience for the emit functions below. */
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result_dst = dst_reg(result_src);
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/* If nothing special happens, this is the result. */
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this->result = result_src;
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/* Limit writes to the channels that will be used by result_src later.
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* This does limit this temp's use as a temporary for multi-instruction
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* sequences.
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*/
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result_dst.writemask = (1 << ir->type->vector_elements) - 1;
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switch (ir->operation) {
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case ir_unop_logic_not:
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