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i965: Share the register file enum between the two backends. 

I need this so I can look at vec4 and fs registers' files from the same
.cpp file without namespaces.  As far as I can tell we never rely on the
particular numerical values of the files, though I thought it sounded like
a good idea when doing the VS (it turns out having 0 be BAD_FILE is nicer).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Eric Anholt 2013-04-29 16:05:05 -07:00
parent 63c8155b09
commit ab04f3b2d7
7 changed files with 24 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/mesa/drivers/dri/i965/brw_fs.cpp
View File

@ -218,7 +218,7 @@ fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1, uint32_t condition)
*/
if (intel->gen == 4) {
dst.type = src0.type;
if (dst.file == FIXED_HW_REG)
if (dst.file == HW_REG)
dst.fixed_hw_reg.type = dst.type;
}
@ -405,7 +405,7 @@ fs_reg::fs_reg(uint32_t u)
fs_reg::fs_reg(struct brw_reg fixed_hw_reg)
{
init();
this->file = FIXED_HW_REG;
this->file = HW_REG;
this->fixed_hw_reg = fixed_hw_reg;
this->type = fixed_hw_reg.type;
}
@ -1212,7 +1212,7 @@ fs_visitor::assign_curb_setup()
constant_nr / 8,
constant_nr % 8);
inst->src[i].file = FIXED_HW_REG;
inst->src[i].file = HW_REG;
inst->src[i].fixed_hw_reg = retype(brw_reg, inst->src[i].type);
}
}
@ -1280,12 +1280,12 @@ fs_visitor::assign_urb_setup()
fs_inst *inst = (fs_inst *)node;
if (inst->opcode == FS_OPCODE_LINTERP) {
assert(inst->src[2].file == FIXED_HW_REG);
assert(inst->src[2].file == HW_REG);
inst->src[2].fixed_hw_reg.nr += urb_start;
}
if (inst->opcode == FS_OPCODE_CINTERP) {
assert(inst->src[0].file == FIXED_HW_REG);
assert(inst->src[0].file == HW_REG);
inst->src[0].fixed_hw_reg.nr += urb_start;
}
}
@ -2402,7 +2402,7 @@ clear_deps_for_inst_src(fs_inst *inst, int dispatch_width, bool *deps,
int grf;
if (inst->src[i].file == GRF) {
grf = inst->src[i].reg;
} else if (inst->src[i].file == FIXED_HW_REG &&
} else if (inst->src[i].file == HW_REG &&
inst->src[i].fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
grf = inst->src[i].fixed_hw_reg.nr;
} else {

10
src/mesa/drivers/dri/i965/brw_fs.h
View File

@ -55,16 +55,6 @@ namespace {
struct acp_entry;
}
enum register_file {
BAD_FILE,
ARF,
GRF,
MRF,
IMM,
FIXED_HW_REG, /* a struct brw_reg */
UNIFORM, /* prog_data->params[reg] */
};
class fs_reg {
public:
/* Callers of this ralloc-based new need not call delete. It's

2
src/mesa/drivers/dri/i965/brw_fs_emit.cpp
View File

@ -854,7 +854,7 @@ brw_reg_from_fs_reg(fs_reg *reg)
break;
}
break;
case FIXED_HW_REG:
case HW_REG:
brw_reg = reg->fixed_hw_reg;
break;
case BAD_FILE:

4
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
View File

@ -258,7 +258,7 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
* the start (see interp_reg()).
*/
for (int i = 0; i < 3; i++) {
if (inst->src[i].file == FIXED_HW_REG &&
if (inst->src[i].file == HW_REG &&
inst->src[i].fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
int node_nr = inst->src[i].fixed_hw_reg.nr / reg_width;
if (node_nr >= payload_node_count)
@ -288,7 +288,7 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
*/
if (intel->gen >= 6) {
int delta_x_arg = 0;
if (inst->src[delta_x_arg].file == FIXED_HW_REG &&
if (inst->src[delta_x_arg].file == HW_REG &&
inst->src[delta_x_arg].fixed_hw_reg.file ==
BRW_GENERAL_REGISTER_FILE) {
int sechalf_node = (inst->src[delta_x_arg].fixed_hw_reg.nr /

8
src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
View File

@ -524,7 +524,7 @@ instruction_scheduler::calculate_deps()
} else {
add_dep(last_grf_write[inst->src[i].reg], n);
}
} else if (inst->src[i].file == FIXED_HW_REG &&
} else if (inst->src[i].file == HW_REG &&
(inst->src[i].fixed_hw_reg.file ==
BRW_GENERAL_REGISTER_FILE)) {
if (post_reg_alloc) {
@ -577,7 +577,7 @@ instruction_scheduler::calculate_deps()
add_dep(last_mrf_write[reg], n);
last_mrf_write[reg] = n;
}
} else if (inst->dst.file == FIXED_HW_REG &&
} else if (inst->dst.file == HW_REG &&
inst->dst.fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
if (post_reg_alloc) {
for (int r = 0; r < reg_width; r++)
@ -629,7 +629,7 @@ instruction_scheduler::calculate_deps()
} else {
add_dep(n, last_grf_write[inst->src[i].reg]);
}
} else if (inst->src[i].file == FIXED_HW_REG &&
} else if (inst->src[i].file == HW_REG &&
(inst->src[i].fixed_hw_reg.file ==
BRW_GENERAL_REGISTER_FILE)) {
if (post_reg_alloc) {
@ -681,7 +681,7 @@ instruction_scheduler::calculate_deps()
last_mrf_write[reg] = n;
}
} else if (inst->dst.file == FIXED_HW_REG &&
} else if (inst->dst.file == HW_REG &&
inst->dst.fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
if (post_reg_alloc) {
for (int r = 0; r < reg_width; r++)

11
src/mesa/drivers/dri/i965/brw_shader.h
View File

@ -27,6 +27,17 @@
#pragma once
enum register_file {
BAD_FILE,
ARF,
GRF,
MRF,
IMM,
HW_REG, /* a struct brw_reg */
ATTR,
UNIFORM, /* prog_data->params[reg] */
};
class backend_instruction : public exec_node {
public:
bool is_tex();

11
src/mesa/drivers/dri/i965/brw_vec4.h
View File

@ -44,17 +44,6 @@ class dst_reg;
unsigned
swizzle_for_size(int size);
enum register_file {
ARF = BRW_ARCHITECTURE_REGISTER_FILE,
GRF = BRW_GENERAL_REGISTER_FILE,
MRF = BRW_MESSAGE_REGISTER_FILE,
IMM = BRW_IMMEDIATE_VALUE,
HW_REG, /* a struct brw_reg */
ATTR,
UNIFORM, /* prog_data->params[hw_reg] */
BAD_FILE
};
class reg
{
public: