2015-04-15 15:16:31 +01:00
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/*
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* Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#ifndef IR3_NIR_H_
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#define IR3_NIR_H_
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2016-01-18 10:54:03 +00:00
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#include "compiler/nir/nir.h"
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2019-03-26 17:31:54 +00:00
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#include "compiler/nir/nir_builder.h"
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2016-01-18 08:47:13 +00:00
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#include "compiler/shader_enums.h"
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2015-04-15 15:16:31 +01:00
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2015-10-24 19:30:31 +01:00
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#include "ir3_shader.h"
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2016-04-23 14:03:28 +01:00
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bool ir3_nir_apply_trig_workarounds(nir_shader *shader);
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ir3/nir: Add new NIR AlgebraicPass for lowering imul
Currently, ir3 backend compiler is lowering integer multiplication from:
dst = a * b
to:
dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
by emitting this code:
mull.u tmp0, a, b ; mul low, i.e. al * bl
madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
which at that point has very low chances of being optimized.
This patch adds a new nir_algebraic.AlgebraicPass to performs this
lowering during NIR algebraic optimization passes, giving it a better
chance for optimizing the resulting code.
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-05-12 23:23:58 +01:00
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bool ir3_nir_lower_imul(nir_shader *shader);
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2017-11-19 17:28:53 +00:00
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bool ir3_nir_lower_tg4_to_tex(nir_shader *shader);
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2020-04-21 00:39:54 +01:00
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bool ir3_nir_lower_io_offsets(nir_shader *shader, int gpu_id);
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2019-04-19 19:12:34 +01:00
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bool ir3_nir_lower_load_barycentric_at_sample(nir_shader *shader);
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2019-04-19 19:15:40 +01:00
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bool ir3_nir_lower_load_barycentric_at_offset(nir_shader *shader);
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2019-03-26 15:28:34 +00:00
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bool ir3_nir_move_varying_inputs(nir_shader *shader);
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2019-08-05 07:09:23 +01:00
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int ir3_nir_coord_offset(nir_ssa_def *ssa);
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bool ir3_nir_lower_tex_prefetch(nir_shader *shader);
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2015-04-15 15:16:31 +01:00
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2020-04-28 20:29:46 +01:00
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void ir3_nir_lower_to_explicit_output(nir_shader *shader,
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2020-06-15 22:12:58 +01:00
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struct ir3_shader_variant *v, unsigned topology);
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ir3: Switch tess lowering to use location
Clip & cull distances, which are compact arrays, exposed a lot of holes
because they can take up multiple slots and partially overlap.
I wanted to eliminate our dependence on knowing the layout of the
variables, as this can get complicated with things like partially
overlapping arrays, which can happen with ARB_enhanced_layouts or with
clip/cull distance arrays. This means no longer changing the layout
based on whether the i/o is part of an array or not, and no longer
matching producer <-> consumer based on the variables. At the end of the
day we have to match things based on the user-specified location, so for
simplicity this switches the entire i/o handling to be based off the
user location rather than the driver location. This means that the
primitive map may be a little bigger, but it reduces the complexity
because we never have to build a table mapping user location to driver
location, and it reduces the amount of work done at link time in the SSO
case. It also brings us closer to what the other drivers do.
While here, I also fixed the handling of component qualifiers, which was
another thing broken with clip/cull distances.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6959>
2020-09-24 15:24:55 +01:00
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void ir3_nir_lower_to_explicit_input(nir_shader *shader, struct ir3_shader_variant *v);
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2020-06-15 22:12:58 +01:00
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void ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader_variant *v, unsigned topology);
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ir3: Switch tess lowering to use location
Clip & cull distances, which are compact arrays, exposed a lot of holes
because they can take up multiple slots and partially overlap.
I wanted to eliminate our dependence on knowing the layout of the
variables, as this can get complicated with things like partially
overlapping arrays, which can happen with ARB_enhanced_layouts or with
clip/cull distance arrays. This means no longer changing the layout
based on whether the i/o is part of an array or not, and no longer
matching producer <-> consumer based on the variables. At the end of the
day we have to match things based on the user-specified location, so for
simplicity this switches the entire i/o handling to be based off the
user location rather than the driver location. This means that the
primitive map may be a little bigger, but it reduces the complexity
because we never have to build a table mapping user location to driver
location, and it reduces the amount of work done at link time in the SSO
case. It also brings us closer to what the other drivers do.
While here, I also fixed the handling of component qualifiers, which was
another thing broken with clip/cull distances.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6959>
2020-09-24 15:24:55 +01:00
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void ir3_nir_lower_tess_eval(nir_shader *shader, struct ir3_shader_variant *v, unsigned topology);
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2020-04-28 20:52:42 +01:00
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void ir3_nir_lower_gs(nir_shader *shader);
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2019-10-11 01:17:10 +01:00
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2017-05-23 14:09:41 +01:00
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const nir_shader_compiler_options * ir3_get_compiler_options(struct ir3_compiler *compiler);
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2020-07-06 17:26:14 +01:00
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void ir3_optimize_loop(nir_shader *s);
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2020-06-15 22:24:00 +01:00
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void ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s);
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void ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s);
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2020-06-10 10:11:27 +01:00
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void ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s);
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2015-10-24 19:30:31 +01:00
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2020-06-15 20:14:04 +01:00
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void ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
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2020-05-30 00:31:43 +01:00
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struct ir3_const_state *const_state);
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2020-07-07 19:56:35 +01:00
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bool ir3_nir_lower_load_constant(nir_shader *nir, struct ir3_shader_variant *v);
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2020-06-17 18:07:09 +01:00
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void ir3_nir_analyze_ubo_ranges(nir_shader *nir, struct ir3_shader_variant *v);
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bool ir3_nir_lower_ubo_loads(nir_shader *nir, struct ir3_shader_variant *v);
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2020-11-13 19:48:57 +00:00
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bool ir3_nir_fixup_load_uniform(nir_shader *nir);
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2019-03-26 17:31:54 +00:00
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nir_ssa_def *
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ir3_nir_try_propagate_bit_shift(nir_builder *b, nir_ssa_def *offset, int32_t shift);
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2020-03-19 13:15:26 +00:00
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static inline nir_intrinsic_instr *
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ir3_bindless_resource(nir_src src)
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{
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if (!src.is_ssa)
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return NULL;
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if (src.ssa->parent_instr->type != nir_instr_type_intrinsic)
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return NULL;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(src.ssa->parent_instr);
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if (intrin->intrinsic != nir_intrinsic_bindless_resource_ir3)
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return NULL;
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return intrin;
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}
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2015-04-15 15:16:31 +01:00
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#endif /* IR3_NIR_H_ */
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