freedreno/ir3: Enable PIPE_CAP_PACKED_UNIFORMS
This commit turns on the gallium cap and adds a pass to lower the load_ubo intrinsics for block 0 back to load_uniform intrinsics and adjust the backend where the cap switches units from vec4s to dwords. As we stop using ir3_glsl_type_size() for uniform layout, this also corrects an issue where we would allocate a vec4 slot for samplers in uniforms, fixing: dEQP-GLES3.functional.shaders.struct.uniform.sampler_array_fragment dEQP-GLES3.functional.shaders.struct.uniform.sampler_array_vertex dEQP-GLES3.functional.shaders.struct.uniform.sampler_nested_fragment dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_vertex dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_fragment Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org> Reviewed-by: Rob Clark <robdclark@gmail.com>
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56b4bc292f
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@ -35,6 +35,7 @@ ir3_SOURCES := \
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ir3/ir3_legalize.c \
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ir3/ir3_nir.c \
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ir3/ir3_nir.h \
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ir3/ir3_nir_analyze_ubo_ranges.c \
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ir3/ir3_nir_lower_io_offsets.c \
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ir3/ir3_nir_lower_tg4_to_tex.c \
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ir3/ir3_print.c \
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@ -681,8 +681,10 @@ emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
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nir_const_value *const_offset;
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/* UBO addresses are the first driver params: */
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unsigned ubo = regid(ctx->so->constbase.ubo, 0);
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/* UBO addresses are the first driver params, but subtract 2 here to
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* account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
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* is the uniforms: */
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unsigned ubo = regid(ctx->so->constbase.ubo, 0) - 2;
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const unsigned ptrsz = ir3_pointer_size(ctx);
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int off = 0;
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@ -1151,15 +1153,13 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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if (const_offset) {
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idx += const_offset->u32[0];
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for (int i = 0; i < intr->num_components; i++) {
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unsigned n = idx * 4 + i;
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dst[i] = create_uniform(b, n);
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dst[i] = create_uniform(b, idx + i);
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}
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} else {
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src = ir3_get_src(ctx, &intr->src[0]);
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for (int i = 0; i < intr->num_components; i++) {
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int n = idx * 4 + i;
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dst[i] = create_uniform_indirect(b, n,
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ir3_get_addr(ctx, src[0], 4));
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dst[i] = create_uniform_indirect(b, idx + i,
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ir3_get_addr(ctx, src[0], 1));
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}
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/* NOTE: if relative addressing is used, we set
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* constlen in the compiler (to worst-case value)
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@ -224,10 +224,13 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
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ir3_optimize_loop(s);
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/* do idiv lowering after first opt loop to give a chance for
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* divide by immed power-of-two to be caught first:
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/* do ubo load and idiv lowering after first opt loop to get a chance to
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* propagate constants for divide by immed power-of-two and constant ubo
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* block/offsets:
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*/
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if (OPT(s, nir_lower_idiv))
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const bool ubo_progress = OPT(s, ir3_nir_analyze_ubo_ranges, shader);
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const bool idiv_progress = OPT(s, nir_lower_idiv);
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if (ubo_progress || idiv_progress)
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ir3_optimize_loop(s);
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OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
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@ -28,6 +28,7 @@
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#define IR3_NIR_H_
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#include "compiler/nir/nir.h"
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#include "compiler/nir/nir_builder.h"
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#include "compiler/shader_enums.h"
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#include "ir3_shader.h"
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@ -43,4 +44,9 @@ bool ir3_key_lowers_nir(const struct ir3_shader_key *key);
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struct nir_shader * ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
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const struct ir3_shader_key *key);
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bool ir3_nir_analyze_ubo_ranges(nir_shader *nir, struct ir3_shader *shader);
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nir_ssa_def *
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ir3_nir_try_propagate_bit_shift(nir_builder *b, nir_ssa_def *offset, int32_t shift);
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#endif /* IR3_NIR_H_ */
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@ -0,0 +1,95 @@
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/*
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* Copyright © 2019 Google, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "ir3_nir.h"
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#include "compiler/nir/nir.h"
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#include "compiler/nir/nir_builder.h"
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#include "util/u_dynarray.h"
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#include "mesa/main/macros.h"
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struct ir3_ubo_analysis_state {
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unsigned lower_count;
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};
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static void
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lower_ubo_load_to_uniform(nir_intrinsic_instr *instr, nir_builder *b,
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struct ir3_ubo_analysis_state *state)
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{
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/* We don't lower dynamic block index UBO loads to load_uniform, but we
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* could probably with some effort determine a block stride in number of
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* registers.
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*/
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if (!nir_src_is_const(instr->src[0]))
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return;
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const uint32_t block = nir_src_as_uint(instr->src[0]);
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if (block > 0)
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return;
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b->cursor = nir_before_instr(&instr->instr);
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nir_ssa_def *ubo_offset = nir_ssa_for_src(b, instr->src[1], 1);
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nir_ssa_def *uniform_offset = ir3_nir_try_propagate_bit_shift(b, ubo_offset, -2);
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if (uniform_offset == NULL)
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uniform_offset = nir_ushr(b, ubo_offset, nir_imm_int(b, 2));
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nir_intrinsic_instr *uniform =
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nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
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uniform->num_components = instr->num_components;
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uniform->src[0] = nir_src_for_ssa(uniform_offset);
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nir_ssa_dest_init(&uniform->instr, &uniform->dest,
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uniform->num_components, instr->dest.ssa.bit_size,
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instr->dest.ssa.name);
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nir_builder_instr_insert(b, &uniform->instr);
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nir_ssa_def_rewrite_uses(&instr->dest.ssa,
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nir_src_for_ssa(&uniform->dest.ssa));
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nir_instr_remove(&instr->instr);
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state->lower_count++;
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}
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bool
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ir3_nir_analyze_ubo_ranges(nir_shader *nir, struct ir3_shader *shader)
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{
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struct ir3_ubo_analysis_state state = { 0 };
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nir_foreach_function(function, nir) {
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if (function->impl) {
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nir_builder builder;
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nir_builder_init(&builder, function->impl);
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nir_foreach_block(block, function->impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type == nir_instr_type_intrinsic &&
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nir_instr_as_intrinsic(instr)->intrinsic == nir_intrinsic_load_ubo)
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lower_ubo_load_to_uniform(nir_instr_as_intrinsic(instr), &builder, &state);
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}
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}
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nir_metadata_preserve(function->impl, nir_metadata_block_index |
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nir_metadata_dominance);
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}
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}
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return state.lower_count > 0;
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}
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@ -124,8 +124,8 @@ check_and_propagate_bit_shift32(nir_builder *b, nir_ssa_def *offset,
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return shift_ssa;
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}
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static nir_ssa_def *
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try_propagate_bit_shift(nir_builder *b, nir_ssa_def *offset, int32_t shift)
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nir_ssa_def *
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ir3_nir_try_propagate_bit_shift(nir_builder *b, nir_ssa_def *offset, int32_t shift)
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{
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nir_instr *offset_instr = offset->parent_instr;
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if (offset_instr->type != nir_instr_type_alu)
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@ -187,7 +187,7 @@ lower_offset_for_ssbo(nir_intrinsic_instr *intrinsic, nir_builder *b,
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* Here we use the convention that shifting right is negative while shifting
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* left is positive. So 'x / 4' ~ 'x >> 2' or 'x << -2'.
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*/
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nir_ssa_def *new_offset = try_propagate_bit_shift(b, offset, -2);
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nir_ssa_def *new_offset = ir3_nir_try_propagate_bit_shift(b, offset, -2);
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/* The new source that will hold the dword-offset is always the last
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* one for every intrinsic.
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@ -50,6 +50,7 @@ libfreedreno_ir3_files = files(
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'ir3_legalize.c',
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'ir3_nir.c',
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'ir3_nir.h',
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'ir3_nir_analyze_ubo_ranges.c',
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'ir3_nir_lower_io_offsets.c',
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'ir3_nir_lower_tg4_to_tex.c',
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'ir3_print.c',
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@ -195,6 +195,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
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case PIPE_CAP_TEXTURE_BARRIER:
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case PIPE_CAP_INVALIDATE_BUFFER:
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case PIPE_CAP_PACKED_UNIFORMS:
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return 1;
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case PIPE_CAP_VERTEXID_NOBASE:
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