freedreno/ir3: move output_loc to variant
This moves the last bit of important state to be serialized from ir3_shader to ir3_shader_variant. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
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@ -282,18 +282,18 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
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if (so->key.has_gs || so->key.tessellation) {
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switch (so->shader->type) {
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case MESA_SHADER_VERTEX:
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NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so->shader, so->key.tessellation);
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NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
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progress = true;
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break;
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case MESA_SHADER_TESS_CTRL:
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NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so->shader, so->key.tessellation);
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NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so, so->key.tessellation);
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NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
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progress = true;
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break;
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case MESA_SHADER_TESS_EVAL:
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NIR_PASS_V(s, ir3_nir_lower_tess_eval, so->key.tessellation);
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if (so->key.has_gs)
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NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so->shader, so->key.tessellation);
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NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
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progress = true;
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break;
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case MESA_SHADER_GEOMETRY:
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@ -45,9 +45,9 @@ bool ir3_nir_lower_tex_prefetch(nir_shader *shader);
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void ir3_nir_lower_to_explicit_output(nir_shader *shader,
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struct ir3_shader *s, unsigned topology);
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struct ir3_shader_variant *v, unsigned topology);
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void ir3_nir_lower_to_explicit_input(nir_shader *shader);
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void ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader *s, unsigned topology);
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void ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader_variant *v, unsigned topology);
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void ir3_nir_lower_tess_eval(nir_shader *shader, unsigned topology);
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void ir3_nir_lower_gs(nir_shader *shader);
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@ -227,12 +227,13 @@ local_thread_id(nir_builder *b)
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}
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void
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ir3_nir_lower_to_explicit_output(nir_shader *shader, struct ir3_shader *s, unsigned topology)
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ir3_nir_lower_to_explicit_output(nir_shader *shader, struct ir3_shader_variant *v,
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unsigned topology)
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{
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struct state state = { };
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build_primitive_map(shader, &state.map, &shader->outputs);
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memcpy(s->output_loc, state.map.loc, sizeof(s->output_loc));
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memcpy(v->output_loc, state.map.loc, sizeof(v->output_loc));
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nir_function_impl *impl = nir_shader_get_entrypoint(shader);
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assert(impl);
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@ -241,7 +242,7 @@ ir3_nir_lower_to_explicit_output(nir_shader *shader, struct ir3_shader *s, unsig
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nir_builder_init(&b, impl);
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b.cursor = nir_before_cf_list(&impl->body);
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if (s->type == MESA_SHADER_VERTEX && topology != IR3_TESS_NONE)
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if (v->type == MESA_SHADER_VERTEX && topology != IR3_TESS_NONE)
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state.header = nir_load_tcs_header_ir3(&b);
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else
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state.header = nir_load_gs_header_ir3(&b);
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@ -252,7 +253,7 @@ ir3_nir_lower_to_explicit_output(nir_shader *shader, struct ir3_shader *s, unsig
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nir_metadata_preserve(impl, nir_metadata_block_index |
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nir_metadata_dominance);
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s->output_size = state.map.stride;
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v->output_size = state.map.stride;
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}
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@ -595,7 +596,8 @@ emit_tess_epilouge(nir_builder *b, struct state *state)
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}
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void
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ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader *s, unsigned topology)
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ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader_variant *v,
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unsigned topology)
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{
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struct state state = { .topology = topology };
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@ -606,8 +608,8 @@ ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader *s, unsigned topol
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}
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build_primitive_map(shader, &state.map, &shader->outputs);
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memcpy(s->output_loc, state.map.loc, sizeof(s->output_loc));
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s->output_size = state.map.stride;
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memcpy(v->output_loc, state.map.loc, sizeof(v->output_loc));
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v->output_size = state.map.stride;
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nir_function_impl *impl = nir_shader_get_entrypoint(shader);
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assert(impl);
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@ -984,7 +986,7 @@ ir3_link_geometry_stages(const struct ir3_shader_variant *producer,
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nir_foreach_variable(out_var, &producer->shader->nir->outputs) {
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if (in_var->data.location == out_var->data.location) {
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locs[in_var->data.driver_location] =
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producer->shader->output_loc[out_var->data.driver_location] * factor;
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producer->output_loc[out_var->data.driver_location] * factor;
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debug_assert(num_loc <= in_var->data.driver_location + 1);
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num_loc = in_var->data.driver_location + 1;
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@ -497,6 +497,12 @@ struct ir3_shader_variant {
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} outputs[32 + 2]; /* +POSITION +PSIZE */
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bool writes_pos, writes_smask, writes_psize;
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/* Size in dwords of all outputs for VS, size of entire patch for HS. */
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uint32_t output_size;
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/* Map from driver_location to byte offset in per-primitive storage */
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unsigned output_loc[32];
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/* attributes (VS) / varyings (FS):
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* Note that sysval's should come *after* normal inputs.
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*/
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@ -631,11 +637,6 @@ struct ir3_shader {
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struct ir3_shader_variant *variants;
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mtx_t variants_lock;
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uint32_t output_size; /* Size in dwords of all outputs for VS, size of entire patch for HS. */
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/* Map from driver_location to byte offset in per-primitive storage */
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unsigned output_loc[32];
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/* Bitmask of bits of the shader key used by this shader. Used to avoid
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* recompiles for GL NOS that doesn't actually apply to the shader.
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*/
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@ -783,7 +783,7 @@ tu6_emit_vpc(struct tu_cs *cs,
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invocations = gs->shader->nir->info.gs.invocations - 1;
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/* Size of per-primitive alloction in ldlw memory in vec4s. */
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vec4_size = gs->shader->nir->info.gs.vertices_in *
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DIV_ROUND_UP(vs->shader->output_size, 4);
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DIV_ROUND_UP(vs->output_size, 4);
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} else {
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vertices_out = 3;
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output = TESS_CW_TRIS;
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@ -843,7 +843,7 @@ tu6_emit_vpc(struct tu_cs *cs,
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tu_cs_emit(cs, 0);
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
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tu_cs_emit(cs, vs->shader->output_size);
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tu_cs_emit(cs, vs->output_size);
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}
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
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@ -1135,8 +1135,8 @@ tu6_emit_geometry_consts(struct tu_cs *cs,
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unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
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uint32_t params[4] = {
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vs->shader->output_size * num_vertices * 4, /* primitive stride */
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vs->shader->output_size * 4, /* vertex stride */
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vs->output_size * num_vertices * 4, /* primitive stride */
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vs->output_size * 4, /* vertex stride */
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0,
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0,
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};
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@ -175,8 +175,8 @@ emit_tess_consts(struct fd6_emit *emit)
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emit->gs->shader->nir->info.gs.vertices_in;
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uint32_t vs_params[4] = {
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emit->vs->shader->output_size * num_vertices * 4, /* vs primitive stride */
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emit->vs->shader->output_size * 4, /* vs vertex stride */
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emit->vs->output_size * num_vertices * 4, /* vs primitive stride */
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emit->vs->output_size * 4, /* vs vertex stride */
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0,
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0
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};
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@ -185,9 +185,9 @@ emit_tess_consts(struct fd6_emit *emit)
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if (emit->hs) {
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uint32_t hs_params[4] = {
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emit->vs->shader->output_size * num_vertices * 4, /* vs primitive stride */
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emit->vs->shader->output_size * 4, /* vs vertex stride */
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emit->hs->shader->output_size,
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emit->vs->output_size * num_vertices * 4, /* vs primitive stride */
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emit->vs->output_size * 4, /* vs vertex stride */
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emit->hs->output_size,
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emit->info->vertices_per_patch
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};
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@ -198,9 +198,9 @@ emit_tess_consts(struct fd6_emit *emit)
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num_vertices = emit->gs->shader->nir->info.gs.vertices_in;
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uint32_t ds_params[4] = {
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emit->ds->shader->output_size * num_vertices * 4, /* ds primitive stride */
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emit->ds->shader->output_size * 4, /* ds vertex stride */
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emit->hs->shader->output_size, /* hs vertex stride (dwords) */
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emit->ds->output_size * num_vertices * 4, /* ds primitive stride */
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emit->ds->output_size * 4, /* ds vertex stride */
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emit->hs->output_size, /* hs vertex stride (dwords) */
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emit->hs->shader->nir->info.tess.tcs_vertices_out
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};
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@ -216,8 +216,8 @@ emit_tess_consts(struct fd6_emit *emit)
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prev = emit->vs;
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uint32_t gs_params[4] = {
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prev->shader->output_size * num_vertices * 4, /* ds primitive stride */
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prev->shader->output_size * 4, /* ds vertex stride */
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prev->output_size * num_vertices * 4, /* ds primitive stride */
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prev->output_size * 4, /* ds vertex stride */
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0,
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0,
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};
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@ -258,7 +258,7 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
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ctx->batch->tessellation = true;
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ctx->batch->tessparam_size = MAX2(ctx->batch->tessparam_size,
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emit.hs->shader->output_size * 4 * info->count);
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emit.hs->output_size * 4 * info->count);
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ctx->batch->tessfactor_size = MAX2(ctx->batch->tessfactor_size,
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factor_stride * info->count);
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@ -562,10 +562,10 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
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/* Total attribute slots in HS incoming patch. */
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OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9801, 1);
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OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->shader->output_size / 4);
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OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->output_size / 4);
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OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
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OUT_RING(ring, vs->shader->output_size);
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OUT_RING(ring, vs->output_size);
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shader_info *ds_info = &ds->shader->nir->info;
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OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
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@ -791,7 +791,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
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/* Size of per-primitive alloction in ldlw memory in vec4s. */
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uint32_t vec4_size =
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gs->shader->nir->info.gs.vertices_in *
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DIV_ROUND_UP(prev->shader->output_size, 4);
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DIV_ROUND_UP(prev->output_size, 4);
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OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
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OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
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@ -799,7 +799,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
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OUT_RING(ring, 0);
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OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
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OUT_RING(ring, prev->shader->output_size);
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OUT_RING(ring, prev->output_size);
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} else {
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OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
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OUT_RING(ring, 0);
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