2020-03-03 00:47:11 +00:00
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/*
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* Copyright (C) 2020 Collabora Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors (Collabora):
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* Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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*/
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#include "main/mtypes.h"
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#include "compiler/glsl/glsl_to_nir.h"
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#include "compiler/nir_types.h"
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#include "compiler/nir/nir_builder.h"
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2020-04-30 08:29:10 +01:00
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#include "util/u_debug.h"
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2020-03-03 00:47:11 +00:00
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#include "disassemble.h"
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#include "bifrost_compile.h"
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2020-03-10 12:20:59 +00:00
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#include "bifrost_nir.h"
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2020-03-03 00:47:11 +00:00
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#include "compiler.h"
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2020-03-03 19:27:05 +00:00
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#include "bi_quirks.h"
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2020-03-05 15:25:19 +00:00
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#include "bi_print.h"
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2020-04-30 08:29:10 +01:00
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static const struct debug_named_value debug_options[] = {
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{"msgs", BIFROST_DBG_MSGS, "Print debug messages"},
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{"shaders", BIFROST_DBG_SHADERS, "Dump shaders in NIR and MIR"},
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DEBUG_NAMED_VALUE_END
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};
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DEBUG_GET_ONCE_FLAGS_OPTION(bifrost_debug, "BIFROST_MESA_DEBUG", debug_options, 0)
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int bifrost_debug = 0;
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#define DBG(fmt, ...) \
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do { if (bifrost_debug & BIFROST_DBG_MSGS) \
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fprintf(stderr, "%s:%d: "fmt, \
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__FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
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2020-03-05 15:25:19 +00:00
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static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
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2020-03-05 22:10:46 +00:00
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static bi_instruction *bi_emit_branch(bi_context *ctx);
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static void
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emit_jump(bi_context *ctx, nir_jump_instr *instr)
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{
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bi_instruction *branch = bi_emit_branch(ctx);
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switch (instr->type) {
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case nir_jump_break:
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2020-05-01 23:13:54 +01:00
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branch->branch_target = ctx->break_block;
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2020-03-05 22:10:46 +00:00
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break;
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case nir_jump_continue:
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2020-05-01 23:13:54 +01:00
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branch->branch_target = ctx->continue_block;
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2020-03-05 22:10:46 +00:00
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break;
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default:
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unreachable("Unhandled jump type");
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}
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2020-05-01 23:13:54 +01:00
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pan_block_add_successor(&ctx->current_block->base, &branch->branch_target->base);
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2020-10-02 18:06:54 +01:00
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ctx->current_block->base.unconditional_jumps = true;
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2020-03-05 22:10:46 +00:00
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}
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2020-03-09 23:52:56 +00:00
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static bi_instruction
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bi_load(enum bi_class T, nir_intrinsic_instr *instr)
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2020-03-05 22:50:18 +00:00
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{
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2020-03-09 23:52:56 +00:00
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bi_instruction load = {
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.type = T,
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2020-04-24 22:20:28 +01:00
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.vector_channels = instr->num_components,
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2020-03-09 23:52:56 +00:00
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.src = { BIR_INDEX_CONSTANT },
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2020-04-15 01:09:00 +01:00
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.src_types = { nir_type_uint32 },
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2020-03-09 23:52:56 +00:00
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.constant = { .u64 = nir_intrinsic_base(instr) },
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2020-03-05 22:50:18 +00:00
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};
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2020-03-09 23:52:56 +00:00
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const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
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if (info->has_dest)
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2020-04-27 21:04:05 +01:00
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load.dest = pan_dest_index(&instr->dest);
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2020-03-09 23:52:56 +00:00
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2020-10-01 03:20:53 +01:00
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if (info->has_dest && nir_intrinsic_has_dest_type(instr))
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load.dest_type = nir_intrinsic_dest_type(instr);
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2020-03-09 23:52:56 +00:00
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2020-03-05 22:50:18 +00:00
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nir_src *offset = nir_get_io_offset_src(instr);
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if (nir_src_is_const(*offset))
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2020-03-09 23:52:56 +00:00
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load.constant.u64 += nir_src_as_uint(*offset);
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2020-03-05 22:50:18 +00:00
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else
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2020-04-27 21:04:05 +01:00
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load.src[0] = pan_src_index(offset);
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2020-03-05 22:50:18 +00:00
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2020-03-09 23:52:56 +00:00
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return load;
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}
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2020-10-12 14:02:29 +01:00
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static void
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bi_emit_ld_output(bi_context *ctx, nir_intrinsic_instr *instr)
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{
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assert(ctx->is_blend);
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bi_instruction ins = {
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.type = BI_LOAD_TILE,
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.vector_channels = instr->num_components,
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.dest = pan_dest_index(&instr->dest),
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.dest_type = nir_type_float16,
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.src = {
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/* PixelIndices */
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BIR_INDEX_CONSTANT,
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/* PixelCoverage: we simply pass r60 which contains the cumulative
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* coverage bitmap
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*/
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BIR_INDEX_REGISTER | 60,
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/* InternalConversionDescriptor (see src/panfrost/lib/midgard.xml for more
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* details)
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*/
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BIR_INDEX_CONSTANT | 32
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},
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.src_types = { nir_type_uint32, nir_type_uint32, nir_type_uint32 },
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};
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/* We want to load the current pixel.
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* FIXME: The sample to load is currently hardcoded to 0. This should
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* be addressed for multi-sample FBs.
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*/
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struct bifrost_pixel_indices pix = {
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.y = BIFROST_CURRENT_PIXEL,
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};
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memcpy(&ins.constant.u64, &pix, sizeof(pix));
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/* Only keep the conversion part of the blend descriptor. */
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ins.constant.u64 |= ctx->blend_desc & 0xffffffff00000000ULL;
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bi_emit(ctx, ins);
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}
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2020-11-05 11:11:54 +00:00
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static enum bifrost_interp_mode
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bi_interp_for_intrinsic(nir_intrinsic_op op)
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{
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switch (op) {
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case nir_intrinsic_load_barycentric_centroid:
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return BIFROST_INTERP_CENTROID;
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case nir_intrinsic_load_barycentric_sample:
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return BIFROST_INTERP_SAMPLE;
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case nir_intrinsic_load_barycentric_pixel:
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default:
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return BIFROST_INTERP_CENTER;
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}
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}
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2020-03-09 23:52:56 +00:00
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static void
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bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
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{
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bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
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2020-11-05 11:10:42 +00:00
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ins.load_vary.interp_mode = BIFROST_INTERP_CENTER; /* TODO */
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2020-03-09 23:52:56 +00:00
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ins.load_vary.reuse = false; /* TODO */
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ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
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2020-03-18 15:55:10 +00:00
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ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
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2020-07-31 23:48:27 +01:00
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ins.format = ins.dest_type;
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2020-03-18 15:55:10 +00:00
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2020-11-05 11:11:54 +00:00
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if (instr->intrinsic == nir_intrinsic_load_interpolated_input) {
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nir_intrinsic_instr *parent = nir_src_as_intrinsic(instr->src[0]);
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if (parent) {
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ins.load_vary.interp_mode =
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bi_interp_for_intrinsic(parent->intrinsic);
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}
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}
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2020-03-18 15:55:10 +00:00
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if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
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/* Zero it out for direct */
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ins.src[1] = BIR_INDEX_ZERO;
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} else {
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/* R61 contains sample mask stuff, TODO RA XXX */
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ins.src[1] = BIR_INDEX_REGISTER | 61;
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}
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2020-03-05 22:50:18 +00:00
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bi_emit(ctx, ins);
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}
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2020-10-14 13:11:52 +01:00
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static void
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bi_emit_ld_blend_input(bi_context *ctx, nir_intrinsic_instr *instr)
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{
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ASSERTED nir_io_semantics sem = nir_intrinsic_io_semantics(instr);
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/* We don't support dual-source blending yet. */
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assert(sem.location == VARYING_SLOT_COL0);
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bi_instruction ins = {
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.type = BI_COMBINE,
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.dest_type = nir_type_uint32,
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.dest = pan_dest_index(&instr->dest),
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.src_types = {
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nir_type_uint32, nir_type_uint32,
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nir_type_uint32, nir_type_uint32,
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},
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/* Source color is passed through r0-r3.
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* TODO: We should probably find a way to avoid this
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* combine/mov and use r0-r3 directly.
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*/
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.src = {
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BIR_INDEX_REGISTER | 0,
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BIR_INDEX_REGISTER | 1,
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BIR_INDEX_REGISTER | 2,
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BIR_INDEX_REGISTER | 3,
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},
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};
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bi_emit(ctx, ins);
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}
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2020-11-04 13:42:51 +00:00
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static void
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bi_emit_atest(bi_context *ctx, unsigned rgba, nir_alu_type T)
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{
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bi_instruction ins = {
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.type = BI_ATEST,
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.src = {
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BIR_INDEX_REGISTER | 60 /* TODO: RA */,
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rgba,
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},
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.src_types = { nir_type_uint32, T },
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.swizzle = {
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{ 0 },
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{ 3, 0 } /* swizzle out the alpha */
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},
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.dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
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.dest_type = nir_type_uint32,
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};
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bi_emit(ctx, ins);
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}
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2020-03-06 14:26:44 +00:00
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static void
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2020-11-04 13:46:32 +00:00
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bi_emit_blend(bi_context *ctx, unsigned rgba, nir_alu_type T, unsigned rt)
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2020-03-06 14:26:44 +00:00
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{
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bi_instruction blend = {
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.type = BI_BLEND,
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2020-11-04 13:46:32 +00:00
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.blend_location = rt,
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2020-03-06 14:26:44 +00:00
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.src = {
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2020-11-04 13:46:32 +00:00
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rgba,
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BIR_INDEX_REGISTER | 60 /* TODO: RA */
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2020-03-09 18:09:04 +00:00
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},
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2020-03-12 01:45:32 +00:00
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.src_types = {
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2020-11-04 13:46:32 +00:00
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T,
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2020-10-12 14:17:42 +01:00
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nir_type_uint32,
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nir_type_uint32,
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nir_type_uint32,
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2020-03-12 01:45:32 +00:00
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},
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2020-03-09 18:09:04 +00:00
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.swizzle = {
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2020-04-10 04:04:41 +01:00
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{ 0, 1, 2, 3 },
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{ 0 }
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2020-03-19 03:12:23 +00:00
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},
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.dest_type = nir_type_uint32,
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2020-04-24 22:20:28 +01:00
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.vector_channels = 4
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2020-03-06 14:26:44 +00:00
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};
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2020-10-12 14:17:42 +01:00
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if (ctx->is_blend) {
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/* Blend descriptor comes from the compile inputs */
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blend.src[2] = BIR_INDEX_CONSTANT | 0;
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blend.src[3] = BIR_INDEX_CONSTANT | 32;
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blend.constant.u64 = ctx->blend_desc;
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/* Put the result in r0 */
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blend.dest = BIR_INDEX_REGISTER | 0;
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} else {
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/* Blend descriptor comes from the FAU RAM */
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blend.src[2] = BIR_INDEX_BLEND | BIFROST_SRC_FAU_LO;
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blend.src[3] = BIR_INDEX_BLEND | BIFROST_SRC_FAU_HI;
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/* By convention, the return address is stored in r48 and will
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* be used by the blend shader to jump back to the fragment
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* shader when it's done.
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*/
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blend.dest = BIR_INDEX_REGISTER | 48;
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}
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2020-08-05 23:10:41 +01:00
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assert(blend.blend_location < 8);
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2020-04-24 00:26:01 +01:00
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assert(ctx->blend_types);
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2020-04-24 07:40:51 +01:00
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assert(blend.src_types[0]);
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2020-04-24 00:26:01 +01:00
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ctx->blend_types[blend.blend_location] = blend.src_types[0];
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2020-03-06 14:26:44 +00:00
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bi_emit(ctx, blend);
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2020-11-04 13:46:32 +00:00
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}
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2020-11-04 14:05:39 +00:00
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static void
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bi_emit_zs_emit(bi_context *ctx, unsigned z, unsigned stencil)
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{
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bi_instruction ins = {
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.type = BI_ZS_EMIT,
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.src = {
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z,
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stencil,
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BIR_INDEX_REGISTER | 60 /* TODO: RA */,
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},
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.src_types = {
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nir_type_float32,
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nir_type_uint8,
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nir_type_uint32,
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},
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.swizzle = { { 0 }, { 0 }, { 0 } },
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.dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
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.dest_type = nir_type_uint32,
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|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, ins);
|
|
|
|
}
|
|
|
|
|
2020-11-04 13:46:32 +00:00
|
|
|
static void
|
|
|
|
bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
2020-11-04 13:52:48 +00:00
|
|
|
bool combined = instr->intrinsic ==
|
|
|
|
nir_intrinsic_store_combined_output_pan;
|
|
|
|
|
|
|
|
unsigned writeout = combined ? nir_intrinsic_component(instr) :
|
|
|
|
PAN_WRITEOUT_C;
|
|
|
|
|
|
|
|
bool emit_blend = writeout & (PAN_WRITEOUT_C);
|
|
|
|
bool emit_zs = writeout & (PAN_WRITEOUT_Z | PAN_WRITEOUT_S);
|
|
|
|
|
2020-11-04 16:13:55 +00:00
|
|
|
const nir_variable *var =
|
|
|
|
nir_find_variable_with_driver_location(ctx->nir, nir_var_shader_out,
|
|
|
|
nir_intrinsic_base(instr));
|
|
|
|
assert(var);
|
|
|
|
|
2020-11-04 13:46:32 +00:00
|
|
|
if (!ctx->emitted_atest && !ctx->is_blend) {
|
|
|
|
bi_emit_atest(ctx,
|
|
|
|
pan_src_index(&instr->src[0]),
|
|
|
|
nir_intrinsic_src_type(instr));
|
|
|
|
|
|
|
|
ctx->emitted_atest = true;
|
|
|
|
}
|
|
|
|
|
2020-11-04 13:52:48 +00:00
|
|
|
if (emit_zs) {
|
2020-11-04 14:05:39 +00:00
|
|
|
unsigned z = writeout & PAN_WRITEOUT_Z ?
|
|
|
|
pan_src_index(&instr->src[2]) : 0;
|
|
|
|
unsigned s = writeout & PAN_WRITEOUT_S ?
|
|
|
|
pan_src_index(&instr->src[3]) : 0;
|
|
|
|
|
|
|
|
bi_emit_zs_emit(ctx, z, s);
|
2020-11-04 13:52:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (emit_blend) {
|
2020-11-04 16:13:55 +00:00
|
|
|
unsigned loc = var->data.location;
|
|
|
|
assert(loc == FRAG_RESULT_COLOR || loc >= FRAG_RESULT_DATA0);
|
|
|
|
|
|
|
|
unsigned rt = loc == FRAG_RESULT_COLOR ? 0 :
|
|
|
|
(loc - FRAG_RESULT_DATA0);
|
|
|
|
|
2020-11-04 13:52:48 +00:00
|
|
|
bi_emit_blend(ctx,
|
|
|
|
pan_src_index(&instr->src[0]),
|
|
|
|
nir_intrinsic_src_type(instr),
|
2020-11-04 16:13:55 +00:00
|
|
|
rt);
|
2020-11-04 13:52:48 +00:00
|
|
|
}
|
2020-10-12 14:17:42 +01:00
|
|
|
|
|
|
|
if (ctx->is_blend) {
|
|
|
|
/* Jump back to the fragment shader, return address is stored
|
|
|
|
* in r48 (see above).
|
|
|
|
*/
|
|
|
|
bi_instruction *ret = bi_emit_branch(ctx);
|
|
|
|
ret->src[2] = BIR_INDEX_REGISTER | 48;
|
|
|
|
}
|
2020-03-06 14:26:44 +00:00
|
|
|
}
|
|
|
|
|
2020-03-21 19:25:54 +00:00
|
|
|
static bi_instruction
|
|
|
|
bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
bi_instruction ld = bi_load(T, instr);
|
|
|
|
ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
|
|
|
|
ld.src[2] = BIR_INDEX_REGISTER | 62;
|
|
|
|
ld.src_types[1] = nir_type_uint32;
|
|
|
|
ld.src_types[2] = nir_type_uint32;
|
2020-10-02 17:02:36 +01:00
|
|
|
ld.format = instr->intrinsic == nir_intrinsic_store_output ?
|
|
|
|
nir_intrinsic_src_type(instr) :
|
|
|
|
nir_intrinsic_dest_type(instr);
|
2020-03-21 19:25:54 +00:00
|
|
|
return ld;
|
|
|
|
}
|
|
|
|
|
2020-03-06 14:44:19 +00:00
|
|
|
static void
|
|
|
|
bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
2020-03-21 19:25:54 +00:00
|
|
|
bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
|
2020-03-09 23:52:56 +00:00
|
|
|
address.dest = bi_make_temp(ctx);
|
2020-03-20 16:25:08 +00:00
|
|
|
address.dest_type = nir_type_uint32;
|
2020-04-24 22:20:28 +01:00
|
|
|
address.vector_channels = 3;
|
2020-03-06 14:44:19 +00:00
|
|
|
|
2020-04-15 01:20:37 +01:00
|
|
|
unsigned nr = nir_intrinsic_src_components(instr, 0);
|
|
|
|
assert(nir_intrinsic_write_mask(instr) == ((1 << nr) - 1));
|
|
|
|
|
2020-03-06 14:44:19 +00:00
|
|
|
bi_instruction st = {
|
|
|
|
.type = BI_STORE_VAR,
|
|
|
|
.src = {
|
2020-04-27 21:04:05 +01:00
|
|
|
pan_src_index(&instr->src[0]),
|
2020-03-20 16:25:08 +00:00
|
|
|
address.dest, address.dest, address.dest,
|
2020-03-09 18:09:04 +00:00
|
|
|
},
|
2020-03-12 01:45:32 +00:00
|
|
|
.src_types = {
|
2020-03-20 16:25:08 +00:00
|
|
|
nir_type_uint32,
|
|
|
|
nir_type_uint32, nir_type_uint32, nir_type_uint32,
|
2020-03-12 01:45:32 +00:00
|
|
|
},
|
2020-03-09 18:09:04 +00:00
|
|
|
.swizzle = {
|
2020-04-15 01:20:37 +01:00
|
|
|
{ 0 },
|
2020-03-20 16:25:08 +00:00
|
|
|
{ 0 }, { 1 }, { 2}
|
2020-03-20 16:38:53 +00:00
|
|
|
},
|
2020-04-24 22:20:28 +01:00
|
|
|
.vector_channels = nr,
|
2020-03-06 14:44:19 +00:00
|
|
|
};
|
|
|
|
|
2020-04-15 01:20:37 +01:00
|
|
|
for (unsigned i = 0; i < nr; ++i)
|
|
|
|
st.swizzle[0][i] = i;
|
|
|
|
|
2020-03-06 14:44:19 +00:00
|
|
|
bi_emit(ctx, address);
|
|
|
|
bi_emit(ctx, st);
|
|
|
|
}
|
|
|
|
|
2020-11-06 08:55:02 +00:00
|
|
|
static void
|
|
|
|
bi_emit_ld_ubo(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
/* nir_lower_uniforms_to_ubo() should have been called, reserving
|
|
|
|
* UBO #0 for uniforms even if the shaders doesn't have uniforms.
|
|
|
|
*/
|
|
|
|
assert(ctx->nir->info.first_ubo_is_default_ubo);
|
|
|
|
|
|
|
|
bool offset_is_const = nir_src_is_const(instr->src[1]);
|
|
|
|
unsigned dyn_offset = pan_src_index(&instr->src[1]);
|
|
|
|
uint32_t const_offset = 0;
|
|
|
|
|
|
|
|
if (nir_src_is_const(instr->src[1]))
|
|
|
|
const_offset = nir_src_as_uint(instr->src[1]);
|
|
|
|
|
|
|
|
if (nir_src_is_const(instr->src[0]) &&
|
|
|
|
nir_src_as_uint(instr->src[0]) == 0 &&
|
|
|
|
ctx->sysvals.sysval_count) {
|
|
|
|
if (offset_is_const) {
|
|
|
|
const_offset += 16 * ctx->sysvals.sysval_count;
|
|
|
|
} else {
|
|
|
|
bi_instruction add = {
|
|
|
|
.type = BI_IMATH,
|
|
|
|
.op.imath = BI_IMATH_ADD,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.src = { dyn_offset, BIR_INDEX_CONSTANT | 0, BIR_INDEX_ZERO },
|
|
|
|
.src_types = { nir_type_uint32, nir_type_uint32, nir_type_uint32 },
|
|
|
|
.constant.u64 = 16 * ctx->sysvals.sysval_count,
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, add);
|
|
|
|
dyn_offset = add.dest;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
bi_instruction ld = {
|
|
|
|
.type = BI_LOAD_UNIFORM,
|
|
|
|
.segment = BI_SEGMENT_UBO,
|
|
|
|
.vector_channels = instr->num_components,
|
|
|
|
.src_types = { nir_type_uint32, nir_type_uint32 },
|
|
|
|
.dest = pan_dest_index(&instr->dest),
|
|
|
|
.dest_type = nir_type_uint | nir_dest_bit_size(instr->dest),
|
|
|
|
};
|
|
|
|
|
|
|
|
if (offset_is_const) {
|
|
|
|
ld.src[0] = BIR_INDEX_CONSTANT | 0;
|
|
|
|
ld.constant.u64 |= const_offset;
|
|
|
|
} else {
|
|
|
|
ld.src[0] = dyn_offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (nir_src_is_const(instr->src[0])) {
|
|
|
|
ld.src[1] = BIR_INDEX_CONSTANT | 32;
|
|
|
|
ld.constant.u64 |= nir_src_as_uint(instr->src[0]) << 32;
|
|
|
|
} else {
|
|
|
|
ld.src[1] = pan_src_index(&instr->src[0]);
|
|
|
|
}
|
|
|
|
|
|
|
|
bi_emit(ctx, ld);
|
|
|
|
}
|
|
|
|
|
2020-03-10 20:20:18 +00:00
|
|
|
static void
|
|
|
|
bi_emit_sysval(bi_context *ctx, nir_instr *instr,
|
|
|
|
unsigned nr_components, unsigned offset)
|
|
|
|
{
|
|
|
|
nir_dest nir_dest;
|
|
|
|
|
|
|
|
/* Figure out which uniform this is */
|
|
|
|
int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
|
|
|
|
void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
|
|
|
|
|
|
|
|
/* Sysvals are prefix uniforms */
|
|
|
|
unsigned uniform = ((uintptr_t) val) - 1;
|
|
|
|
|
|
|
|
/* Emit the read itself -- this is never indirect */
|
|
|
|
|
|
|
|
bi_instruction load = {
|
|
|
|
.type = BI_LOAD_UNIFORM,
|
2020-07-31 22:29:50 +01:00
|
|
|
.segment = BI_SEGMENT_UBO,
|
2020-04-24 22:20:28 +01:00
|
|
|
.vector_channels = nr_components,
|
2020-03-20 15:38:21 +00:00
|
|
|
.src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
|
2020-04-15 01:09:00 +01:00
|
|
|
.src_types = { nir_type_uint32, nir_type_uint32 },
|
2020-03-10 20:20:18 +00:00
|
|
|
.constant = { (uniform * 16) + offset },
|
2020-04-27 21:04:05 +01:00
|
|
|
.dest = pan_dest_index(&nir_dest),
|
2020-03-10 20:20:18 +00:00
|
|
|
.dest_type = nir_type_uint32, /* TODO */
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, load);
|
|
|
|
}
|
|
|
|
|
2020-05-01 19:55:04 +01:00
|
|
|
/* gl_FragCoord.xy = u16_to_f32(R59.xy) + 0.5
|
|
|
|
* gl_FragCoord.z = ld_vary(fragz)
|
|
|
|
* gl_FragCoord.w = ld_vary(fragw)
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void
|
|
|
|
bi_emit_ld_frag_coord(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
/* Future proofing for mediump fragcoord at some point.. */
|
|
|
|
nir_alu_type T = nir_type_float32;
|
|
|
|
|
|
|
|
/* First, sketch a combine */
|
|
|
|
bi_instruction combine = {
|
|
|
|
.type = BI_COMBINE,
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.dest = pan_dest_index(&instr->dest),
|
|
|
|
.src_types = { T, T, T, T },
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Second, handle xy */
|
|
|
|
for (unsigned i = 0; i < 2; ++i) {
|
|
|
|
bi_instruction conv = {
|
|
|
|
.type = BI_CONVERT,
|
|
|
|
.dest_type = T,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.src = {
|
|
|
|
/* TODO: RA XXX */
|
|
|
|
BIR_INDEX_REGISTER | 59
|
|
|
|
},
|
|
|
|
.src_types = { nir_type_uint16 },
|
|
|
|
.swizzle = { { i } }
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_instruction add = {
|
|
|
|
.type = BI_ADD,
|
|
|
|
.dest_type = T,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.src = { conv.dest, BIR_INDEX_CONSTANT },
|
|
|
|
.src_types = { T, T },
|
|
|
|
};
|
|
|
|
|
|
|
|
float half = 0.5;
|
|
|
|
memcpy(&add.constant.u32, &half, sizeof(float));
|
|
|
|
|
|
|
|
bi_emit(ctx, conv);
|
|
|
|
bi_emit(ctx, add);
|
|
|
|
|
|
|
|
combine.src[i] = add.dest;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Third, zw */
|
|
|
|
for (unsigned i = 0; i < 2; ++i) {
|
|
|
|
bi_instruction load = {
|
|
|
|
.type = BI_LOAD_VAR,
|
|
|
|
.load_vary = {
|
2020-11-05 11:10:42 +00:00
|
|
|
.interp_mode = BIFROST_INTERP_CENTER,
|
2020-05-01 19:55:04 +01:00
|
|
|
.reuse = false,
|
|
|
|
.flat = true
|
|
|
|
},
|
|
|
|
.vector_channels = 1,
|
|
|
|
.dest_type = nir_type_float32,
|
2020-07-31 23:48:27 +01:00
|
|
|
.format = nir_type_float32,
|
2020-05-01 19:55:04 +01:00
|
|
|
.dest = bi_make_temp(ctx),
|
2020-08-03 17:48:44 +01:00
|
|
|
.src = {
|
|
|
|
BIR_INDEX_CONSTANT,
|
2020-10-12 09:57:40 +01:00
|
|
|
BIR_INDEX_PASS | BIFROST_SRC_FAU_LO
|
2020-08-03 17:48:44 +01:00
|
|
|
},
|
2020-05-01 19:55:04 +01:00
|
|
|
.src_types = { nir_type_uint32, nir_type_uint32 },
|
|
|
|
.constant = {
|
|
|
|
.u32 = (i == 0) ? BIFROST_FRAGZ : BIFROST_FRAGW
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, load);
|
|
|
|
|
|
|
|
combine.src[i + 2] = load.dest;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Finally, emit the combine */
|
|
|
|
bi_emit(ctx, combine);
|
|
|
|
}
|
|
|
|
|
2020-05-01 23:26:18 +01:00
|
|
|
static void
|
|
|
|
bi_emit_discard(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
/* Goofy lowering */
|
|
|
|
bi_instruction discard = {
|
|
|
|
.type = BI_DISCARD,
|
|
|
|
.cond = BI_COND_EQ,
|
|
|
|
.src_types = { nir_type_uint32, nir_type_uint32 },
|
|
|
|
.src = { BIR_INDEX_ZERO, BIR_INDEX_ZERO },
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, discard);
|
|
|
|
}
|
|
|
|
|
2020-05-01 23:36:42 +01:00
|
|
|
static void
|
|
|
|
bi_fuse_cond(bi_instruction *csel, nir_alu_src cond,
|
|
|
|
unsigned *constants_left, unsigned *constant_shift,
|
|
|
|
unsigned comps, bool float_only);
|
|
|
|
|
2020-05-01 23:24:11 +01:00
|
|
|
static void
|
|
|
|
bi_emit_discard_if(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
nir_src cond = instr->src[0];
|
|
|
|
nir_alu_type T = nir_type_uint | nir_src_bit_size(cond);
|
|
|
|
|
|
|
|
bi_instruction discard = {
|
|
|
|
.type = BI_DISCARD,
|
|
|
|
.cond = BI_COND_NE,
|
|
|
|
.src_types = { T, T },
|
|
|
|
.src = {
|
|
|
|
pan_src_index(&cond),
|
|
|
|
BIR_INDEX_ZERO
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2020-05-01 23:36:42 +01:00
|
|
|
/* Try to fuse in the condition */
|
|
|
|
unsigned constants_left = 1, constant_shift = 0;
|
|
|
|
|
|
|
|
/* Scalar so no swizzle */
|
|
|
|
nir_alu_src wrap = {
|
|
|
|
.src = instr->src[0]
|
|
|
|
};
|
|
|
|
|
|
|
|
/* May or may not succeed but we're optimistic */
|
|
|
|
bi_fuse_cond(&discard, wrap, &constants_left, &constant_shift, 1, true);
|
|
|
|
|
2020-05-01 23:24:11 +01:00
|
|
|
bi_emit(ctx, discard);
|
|
|
|
}
|
|
|
|
|
2020-10-12 10:25:25 +01:00
|
|
|
static void
|
|
|
|
bi_emit_blend_const(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
assert(ctx->is_blend);
|
|
|
|
|
|
|
|
unsigned comp;
|
|
|
|
switch (instr->intrinsic) {
|
|
|
|
case nir_intrinsic_load_blend_const_color_r_float: comp = 0; break;
|
|
|
|
case nir_intrinsic_load_blend_const_color_g_float: comp = 1; break;
|
|
|
|
case nir_intrinsic_load_blend_const_color_b_float: comp = 2; break;
|
|
|
|
case nir_intrinsic_load_blend_const_color_a_float: comp = 3; break;
|
|
|
|
default: unreachable("Invalid load blend constant intrinsic");
|
|
|
|
}
|
|
|
|
|
|
|
|
bi_instruction move = {
|
|
|
|
.type = BI_MOV,
|
|
|
|
.dest = pan_dest_index(&instr->dest),
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.src = { BIR_INDEX_CONSTANT },
|
|
|
|
.src_types = { nir_type_uint32 },
|
|
|
|
};
|
|
|
|
|
|
|
|
memcpy(&move.constant.u32, &ctx->blend_constants[comp], sizeof(float));
|
|
|
|
|
|
|
|
bi_emit(ctx, move);
|
|
|
|
}
|
|
|
|
|
2020-10-17 10:24:17 +01:00
|
|
|
static void
|
|
|
|
bi_emit_sample_id(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
bi_instruction ins = {
|
|
|
|
.type = BI_BITWISE,
|
|
|
|
.op.bitwise = BI_BITWISE_AND,
|
|
|
|
.bitwise.rshift = true,
|
|
|
|
.dest = pan_dest_index(&instr->dest),
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.src = {
|
|
|
|
/* r61[16:23] contains the sampleID */
|
|
|
|
BIR_INDEX_REGISTER | 61,
|
|
|
|
/* mask */
|
|
|
|
BIR_INDEX_CONSTANT | 0,
|
|
|
|
/* shift */
|
|
|
|
BIR_INDEX_CONSTANT | 32,
|
|
|
|
},
|
|
|
|
.src_types = {
|
|
|
|
nir_type_uint32,
|
|
|
|
nir_type_uint32,
|
|
|
|
nir_type_uint8,
|
|
|
|
},
|
|
|
|
.constant.u64 = 0xffull | (0x10ull << 32ull)
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, ins);
|
|
|
|
}
|
|
|
|
|
2020-10-18 17:06:29 +01:00
|
|
|
static void
|
|
|
|
bi_emit_front_face(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
bi_instruction ins = {
|
|
|
|
.type = BI_CMP,
|
|
|
|
.cond = BI_COND_EQ,
|
|
|
|
.dest = pan_dest_index(&instr->dest),
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.src = {
|
|
|
|
/* r58 == 0 means primitive is front facing */
|
|
|
|
BIR_INDEX_REGISTER | 58,
|
|
|
|
BIR_INDEX_ZERO,
|
|
|
|
},
|
|
|
|
.src_types = {
|
|
|
|
nir_type_uint32,
|
|
|
|
nir_type_uint32,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, ins);
|
|
|
|
}
|
|
|
|
|
2020-10-18 20:11:49 +01:00
|
|
|
static void
|
|
|
|
bi_emit_point_coord(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
bi_instruction ins = {
|
|
|
|
.type = BI_LOAD_VAR,
|
|
|
|
.vector_channels = 2,
|
|
|
|
.dest = pan_dest_index(&instr->dest),
|
|
|
|
.dest_type = nir_type_float32,
|
|
|
|
.format = nir_type_float32,
|
|
|
|
.src = {
|
|
|
|
BIR_INDEX_CONSTANT,
|
|
|
|
BIR_INDEX_ZERO,
|
|
|
|
},
|
|
|
|
.src_types = {
|
|
|
|
nir_type_uint32,
|
|
|
|
},
|
|
|
|
.constant.u64 = 20,
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, ins);
|
|
|
|
}
|
|
|
|
|
2020-03-05 22:50:18 +00:00
|
|
|
static void
|
|
|
|
emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
|
|
|
|
switch (instr->intrinsic) {
|
|
|
|
case nir_intrinsic_load_barycentric_pixel:
|
2020-11-05 11:11:54 +00:00
|
|
|
case nir_intrinsic_load_barycentric_centroid:
|
|
|
|
case nir_intrinsic_load_barycentric_sample:
|
2020-03-05 22:50:18 +00:00
|
|
|
/* stub */
|
|
|
|
break;
|
|
|
|
case nir_intrinsic_load_interpolated_input:
|
2020-03-06 14:33:52 +00:00
|
|
|
case nir_intrinsic_load_input:
|
2020-10-14 13:11:52 +01:00
|
|
|
if (ctx->is_blend)
|
|
|
|
bi_emit_ld_blend_input(ctx, instr);
|
|
|
|
else if (ctx->stage == MESA_SHADER_FRAGMENT)
|
2020-03-06 14:33:52 +00:00
|
|
|
bi_emit_ld_vary(ctx, instr);
|
|
|
|
else if (ctx->stage == MESA_SHADER_VERTEX)
|
2020-03-21 19:25:54 +00:00
|
|
|
bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
|
2020-03-06 14:33:52 +00:00
|
|
|
else {
|
|
|
|
unreachable("Unsupported shader stage");
|
|
|
|
}
|
2020-03-05 22:50:18 +00:00
|
|
|
break;
|
2020-03-06 14:33:52 +00:00
|
|
|
|
2020-03-06 14:26:44 +00:00
|
|
|
case nir_intrinsic_store_output:
|
|
|
|
if (ctx->stage == MESA_SHADER_FRAGMENT)
|
|
|
|
bi_emit_frag_out(ctx, instr);
|
2020-03-06 14:44:19 +00:00
|
|
|
else if (ctx->stage == MESA_SHADER_VERTEX)
|
|
|
|
bi_emit_st_vary(ctx, instr);
|
|
|
|
else
|
|
|
|
unreachable("Unsupported shader stage");
|
2020-03-06 14:26:44 +00:00
|
|
|
break;
|
2020-03-06 14:52:09 +00:00
|
|
|
|
2020-11-04 13:52:48 +00:00
|
|
|
case nir_intrinsic_store_combined_output_pan:
|
|
|
|
assert(ctx->stage == MESA_SHADER_FRAGMENT);
|
|
|
|
bi_emit_frag_out(ctx, instr);
|
|
|
|
break;
|
|
|
|
|
2020-11-06 08:55:02 +00:00
|
|
|
case nir_intrinsic_load_ubo:
|
|
|
|
bi_emit_ld_ubo(ctx, instr);
|
|
|
|
break;
|
|
|
|
|
2020-05-01 19:55:04 +01:00
|
|
|
case nir_intrinsic_load_frag_coord:
|
|
|
|
bi_emit_ld_frag_coord(ctx, instr);
|
|
|
|
break;
|
|
|
|
|
2020-05-01 23:26:18 +01:00
|
|
|
case nir_intrinsic_discard:
|
|
|
|
bi_emit_discard(ctx, instr);
|
|
|
|
break;
|
|
|
|
|
2020-05-01 23:24:11 +01:00
|
|
|
case nir_intrinsic_discard_if:
|
|
|
|
bi_emit_discard_if(ctx, instr);
|
|
|
|
break;
|
|
|
|
|
2020-03-10 20:20:18 +00:00
|
|
|
case nir_intrinsic_load_ssbo_address:
|
|
|
|
bi_emit_sysval(ctx, &instr->instr, 1, 0);
|
|
|
|
break;
|
|
|
|
|
2020-09-22 09:24:45 +01:00
|
|
|
case nir_intrinsic_get_ssbo_size:
|
2020-03-10 20:20:18 +00:00
|
|
|
bi_emit_sysval(ctx, &instr->instr, 1, 8);
|
|
|
|
break;
|
|
|
|
|
2020-10-12 14:02:29 +01:00
|
|
|
case nir_intrinsic_load_output:
|
|
|
|
bi_emit_ld_output(ctx, instr);
|
|
|
|
break;
|
|
|
|
|
2020-03-10 20:20:18 +00:00
|
|
|
case nir_intrinsic_load_viewport_scale:
|
|
|
|
case nir_intrinsic_load_viewport_offset:
|
|
|
|
case nir_intrinsic_load_num_work_groups:
|
|
|
|
case nir_intrinsic_load_sampler_lod_parameters_pan:
|
|
|
|
bi_emit_sysval(ctx, &instr->instr, 3, 0);
|
|
|
|
break;
|
|
|
|
|
2020-10-12 10:25:25 +01:00
|
|
|
case nir_intrinsic_load_blend_const_color_r_float:
|
|
|
|
case nir_intrinsic_load_blend_const_color_g_float:
|
|
|
|
case nir_intrinsic_load_blend_const_color_b_float:
|
|
|
|
case nir_intrinsic_load_blend_const_color_a_float:
|
|
|
|
bi_emit_blend_const(ctx, instr);
|
|
|
|
break;
|
|
|
|
|
2020-10-17 10:24:17 +01:00
|
|
|
case nir_intrinsic_load_sample_id:
|
|
|
|
bi_emit_sample_id(ctx, instr);
|
|
|
|
break;
|
|
|
|
|
2020-10-18 17:06:29 +01:00
|
|
|
case nir_intrinsic_load_front_face:
|
|
|
|
bi_emit_front_face(ctx, instr);
|
|
|
|
break;
|
|
|
|
|
2020-10-18 20:11:49 +01:00
|
|
|
case nir_intrinsic_load_point_coord:
|
|
|
|
bi_emit_point_coord(ctx, instr);
|
|
|
|
break;
|
|
|
|
|
2020-03-05 22:50:18 +00:00
|
|
|
default:
|
2020-05-01 19:13:10 +01:00
|
|
|
unreachable("Unknown intrinsic");
|
2020-03-05 22:50:18 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-06 21:29:35 +00:00
|
|
|
static void
|
|
|
|
emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
|
|
|
|
{
|
|
|
|
/* Make sure we've been lowered */
|
2020-06-03 00:30:56 +01:00
|
|
|
assert(instr->def.num_components <= (32 / instr->def.bit_size));
|
|
|
|
|
|
|
|
/* Accumulate all the channels of the constant, as if we did an
|
|
|
|
* implicit SEL over them */
|
|
|
|
uint32_t acc = 0;
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < instr->def.num_components; ++i) {
|
|
|
|
unsigned v = nir_const_value_as_uint(instr->value[i], instr->def.bit_size);
|
|
|
|
acc |= (v << (i * instr->def.bit_size));
|
|
|
|
}
|
2020-03-06 21:29:35 +00:00
|
|
|
|
|
|
|
bi_instruction move = {
|
|
|
|
.type = BI_MOV,
|
2020-04-27 21:04:05 +01:00
|
|
|
.dest = pan_ssa_index(&instr->def),
|
2020-06-03 00:30:56 +01:00
|
|
|
.dest_type = nir_type_uint32,
|
2020-03-06 21:29:35 +00:00
|
|
|
.src = {
|
|
|
|
BIR_INDEX_CONSTANT
|
|
|
|
},
|
2020-03-31 01:54:51 +01:00
|
|
|
.src_types = {
|
2020-06-03 00:30:56 +01:00
|
|
|
nir_type_uint32,
|
2020-03-31 01:54:51 +01:00
|
|
|
},
|
2020-03-06 21:29:35 +00:00
|
|
|
.constant = {
|
2020-06-03 00:30:56 +01:00
|
|
|
.u32 = acc
|
2020-03-06 21:29:35 +00:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, move);
|
|
|
|
}
|
|
|
|
|
2020-03-21 21:37:47 +00:00
|
|
|
#define BI_CASE_CMP(op) \
|
|
|
|
case op##8: \
|
|
|
|
case op##16: \
|
|
|
|
case op##32: \
|
|
|
|
|
2020-03-10 00:19:51 +00:00
|
|
|
static enum bi_class
|
|
|
|
bi_class_for_nir_alu(nir_op op)
|
|
|
|
{
|
|
|
|
switch (op) {
|
2020-03-10 01:10:41 +00:00
|
|
|
case nir_op_fadd:
|
2020-03-10 11:56:14 +00:00
|
|
|
case nir_op_fsub:
|
2020-03-10 01:10:41 +00:00
|
|
|
return BI_ADD;
|
2020-05-04 19:04:35 +01:00
|
|
|
|
|
|
|
case nir_op_iadd:
|
2020-03-10 12:03:20 +00:00
|
|
|
case nir_op_isub:
|
2020-05-04 19:00:13 +01:00
|
|
|
return BI_IMATH;
|
2020-03-10 01:10:41 +00:00
|
|
|
|
2020-07-26 23:54:14 +01:00
|
|
|
case nir_op_imul:
|
|
|
|
return BI_IMUL;
|
|
|
|
|
2020-04-28 19:36:17 +01:00
|
|
|
case nir_op_iand:
|
|
|
|
case nir_op_ior:
|
|
|
|
case nir_op_ixor:
|
2020-07-26 19:37:42 +01:00
|
|
|
case nir_op_inot:
|
2020-07-26 20:18:54 +01:00
|
|
|
case nir_op_ishl:
|
2020-04-28 19:36:17 +01:00
|
|
|
return BI_BITWISE;
|
|
|
|
|
2020-03-21 21:37:47 +00:00
|
|
|
BI_CASE_CMP(nir_op_flt)
|
|
|
|
BI_CASE_CMP(nir_op_fge)
|
|
|
|
BI_CASE_CMP(nir_op_feq)
|
2020-08-18 18:51:57 +01:00
|
|
|
BI_CASE_CMP(nir_op_fneu)
|
2020-03-21 21:37:47 +00:00
|
|
|
BI_CASE_CMP(nir_op_ilt)
|
|
|
|
BI_CASE_CMP(nir_op_ige)
|
|
|
|
BI_CASE_CMP(nir_op_ieq)
|
|
|
|
BI_CASE_CMP(nir_op_ine)
|
2020-07-26 20:41:17 +01:00
|
|
|
BI_CASE_CMP(nir_op_uge)
|
2020-10-18 21:19:15 +01:00
|
|
|
BI_CASE_CMP(nir_op_ult)
|
2020-03-10 12:21:35 +00:00
|
|
|
return BI_CMP;
|
|
|
|
|
2020-03-21 21:37:47 +00:00
|
|
|
case nir_op_b8csel:
|
|
|
|
case nir_op_b16csel:
|
|
|
|
case nir_op_b32csel:
|
2020-03-10 12:32:56 +00:00
|
|
|
return BI_CSEL;
|
|
|
|
|
2020-03-10 01:10:41 +00:00
|
|
|
case nir_op_i2i8:
|
|
|
|
case nir_op_i2i16:
|
|
|
|
case nir_op_i2i32:
|
|
|
|
case nir_op_i2i64:
|
|
|
|
case nir_op_u2u8:
|
|
|
|
case nir_op_u2u16:
|
|
|
|
case nir_op_u2u32:
|
|
|
|
case nir_op_u2u64:
|
|
|
|
case nir_op_f2i16:
|
|
|
|
case nir_op_f2i32:
|
|
|
|
case nir_op_f2i64:
|
|
|
|
case nir_op_f2u16:
|
|
|
|
case nir_op_f2u32:
|
|
|
|
case nir_op_f2u64:
|
|
|
|
case nir_op_i2f16:
|
|
|
|
case nir_op_i2f32:
|
|
|
|
case nir_op_i2f64:
|
|
|
|
case nir_op_u2f16:
|
|
|
|
case nir_op_u2f32:
|
|
|
|
case nir_op_u2f64:
|
2020-03-27 18:40:04 +00:00
|
|
|
case nir_op_f2f16:
|
|
|
|
case nir_op_f2f32:
|
|
|
|
case nir_op_f2f64:
|
|
|
|
case nir_op_f2fmp:
|
2020-03-10 01:10:41 +00:00
|
|
|
return BI_CONVERT;
|
|
|
|
|
2020-03-22 21:31:23 +00:00
|
|
|
case nir_op_vec2:
|
|
|
|
case nir_op_vec3:
|
|
|
|
case nir_op_vec4:
|
|
|
|
return BI_COMBINE;
|
|
|
|
|
|
|
|
case nir_op_vec8:
|
|
|
|
case nir_op_vec16:
|
|
|
|
unreachable("should've been lowered");
|
|
|
|
|
2020-03-11 19:15:41 +00:00
|
|
|
case nir_op_ffma:
|
2020-03-10 01:10:41 +00:00
|
|
|
case nir_op_fmul:
|
|
|
|
return BI_FMA;
|
|
|
|
|
|
|
|
case nir_op_imin:
|
|
|
|
case nir_op_imax:
|
|
|
|
case nir_op_umin:
|
|
|
|
case nir_op_umax:
|
|
|
|
case nir_op_fmin:
|
|
|
|
case nir_op_fmax:
|
|
|
|
return BI_MINMAX;
|
|
|
|
|
2020-03-10 01:02:51 +00:00
|
|
|
case nir_op_fsat:
|
2020-03-10 11:52:24 +00:00
|
|
|
case nir_op_fneg:
|
|
|
|
case nir_op_fabs:
|
2020-03-19 20:58:48 +00:00
|
|
|
return BI_FMOV;
|
2020-03-10 01:10:41 +00:00
|
|
|
case nir_op_mov:
|
|
|
|
return BI_MOV;
|
|
|
|
|
2020-03-28 00:28:09 +00:00
|
|
|
case nir_op_fround_even:
|
|
|
|
case nir_op_fceil:
|
|
|
|
case nir_op_ffloor:
|
|
|
|
case nir_op_ftrunc:
|
|
|
|
return BI_ROUND;
|
|
|
|
|
2020-03-10 01:20:20 +00:00
|
|
|
case nir_op_frcp:
|
|
|
|
case nir_op_frsq:
|
2020-07-27 19:51:31 +01:00
|
|
|
case nir_op_iabs:
|
2020-10-28 12:27:07 +00:00
|
|
|
return BI_SPECIAL_ADD;
|
2020-03-10 01:20:20 +00:00
|
|
|
|
2020-03-10 01:10:41 +00:00
|
|
|
default:
|
|
|
|
unreachable("Unknown ALU op");
|
2020-03-10 00:19:51 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-21 22:12:31 +00:00
|
|
|
/* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
|
|
|
|
* return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
|
|
|
|
* optimizations). Otherwise it will bail (when used for primary code
|
|
|
|
* generation). */
|
|
|
|
|
2020-03-10 12:21:35 +00:00
|
|
|
static enum bi_cond
|
2020-03-21 22:12:31 +00:00
|
|
|
bi_cond_for_nir(nir_op op, bool soft)
|
2020-03-10 12:21:35 +00:00
|
|
|
{
|
|
|
|
switch (op) {
|
2020-03-21 21:37:47 +00:00
|
|
|
BI_CASE_CMP(nir_op_flt)
|
|
|
|
BI_CASE_CMP(nir_op_ilt)
|
2020-10-18 21:19:15 +01:00
|
|
|
BI_CASE_CMP(nir_op_ult)
|
2020-03-10 12:21:35 +00:00
|
|
|
return BI_COND_LT;
|
2020-03-21 21:37:47 +00:00
|
|
|
|
|
|
|
BI_CASE_CMP(nir_op_fge)
|
|
|
|
BI_CASE_CMP(nir_op_ige)
|
2020-07-26 20:41:17 +01:00
|
|
|
BI_CASE_CMP(nir_op_uge)
|
2020-03-10 12:21:35 +00:00
|
|
|
return BI_COND_GE;
|
2020-03-21 21:37:47 +00:00
|
|
|
|
|
|
|
BI_CASE_CMP(nir_op_feq)
|
|
|
|
BI_CASE_CMP(nir_op_ieq)
|
2020-03-10 12:21:35 +00:00
|
|
|
return BI_COND_EQ;
|
2020-03-21 21:37:47 +00:00
|
|
|
|
2020-08-18 18:51:57 +01:00
|
|
|
BI_CASE_CMP(nir_op_fneu)
|
2020-03-21 21:37:47 +00:00
|
|
|
BI_CASE_CMP(nir_op_ine)
|
2020-03-10 12:21:35 +00:00
|
|
|
return BI_COND_NE;
|
|
|
|
default:
|
2020-03-21 22:12:31 +00:00
|
|
|
if (soft)
|
|
|
|
return BI_COND_ALWAYS;
|
|
|
|
else
|
|
|
|
unreachable("Invalid compare");
|
2020-03-10 12:21:35 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-21 22:13:49 +00:00
|
|
|
static void
|
|
|
|
bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
|
2020-11-05 14:13:28 +00:00
|
|
|
unsigned *constants_left, unsigned *constant_shift)
|
2020-03-21 22:13:49 +00:00
|
|
|
{
|
|
|
|
unsigned bits = nir_src_bit_size(instr->src[i].src);
|
|
|
|
unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
|
|
|
|
|
|
|
|
alu->src_types[to] = nir_op_infos[instr->op].input_types[i]
|
|
|
|
| bits;
|
|
|
|
|
|
|
|
/* Try to inline a constant */
|
|
|
|
if (nir_src_is_const(instr->src[i].src) && *constants_left && (dest_bits == bits)) {
|
2020-04-15 15:39:42 +01:00
|
|
|
uint64_t mask = (1ull << dest_bits) - 1;
|
|
|
|
uint64_t cons = nir_src_as_uint(instr->src[i].src);
|
|
|
|
|
|
|
|
/* Try to reuse a constant */
|
|
|
|
for (unsigned i = 0; i < (*constant_shift); i += dest_bits) {
|
|
|
|
if (((alu->constant.u64 >> i) & mask) == cons) {
|
|
|
|
alu->src[to] = BIR_INDEX_CONSTANT | i;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
2020-03-21 22:13:49 +00:00
|
|
|
|
2020-04-15 15:39:42 +01:00
|
|
|
alu->constant.u64 |= cons << *constant_shift;
|
2020-03-21 22:13:49 +00:00
|
|
|
alu->src[to] = BIR_INDEX_CONSTANT | (*constant_shift);
|
|
|
|
--(*constants_left);
|
2020-04-17 20:52:03 +01:00
|
|
|
(*constant_shift) += MAX2(dest_bits, 32); /* lo/hi */
|
2020-03-21 22:13:49 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-04-27 21:04:05 +01:00
|
|
|
alu->src[to] = pan_src_index(&instr->src[i].src);
|
2020-03-21 22:13:49 +00:00
|
|
|
|
2020-04-24 22:20:28 +01:00
|
|
|
/* Copy swizzle for all vectored components, replicating last component
|
|
|
|
* to fill undersized */
|
|
|
|
|
|
|
|
unsigned vec = alu->type == BI_COMBINE ? 1 :
|
2020-11-05 14:13:28 +00:00
|
|
|
MAX2(1, 32 / bits);
|
2020-04-24 22:20:28 +01:00
|
|
|
|
2020-11-05 14:13:28 +00:00
|
|
|
unsigned comps = nir_ssa_alu_instr_src_components(instr, i);
|
2020-04-24 22:20:28 +01:00
|
|
|
for (unsigned j = 0; j < vec; ++j)
|
|
|
|
alu->swizzle[to][j] = instr->src[i].swizzle[MIN2(j, comps - 1)];
|
2020-03-21 22:13:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2020-05-01 23:31:22 +01:00
|
|
|
bi_fuse_cond(bi_instruction *csel, nir_alu_src cond,
|
|
|
|
unsigned *constants_left, unsigned *constant_shift,
|
|
|
|
unsigned comps, bool float_only)
|
2020-03-21 22:13:49 +00:00
|
|
|
{
|
|
|
|
/* Bail for vector weirdness */
|
|
|
|
if (cond.swizzle[0] != 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!cond.src.is_ssa)
|
|
|
|
return;
|
|
|
|
|
|
|
|
nir_ssa_def *def = cond.src.ssa;
|
|
|
|
nir_instr *parent = def->parent_instr;
|
|
|
|
|
|
|
|
if (parent->type != nir_instr_type_alu)
|
|
|
|
return;
|
|
|
|
|
|
|
|
nir_alu_instr *alu = nir_instr_as_alu(parent);
|
|
|
|
|
|
|
|
/* Try to match a condition */
|
|
|
|
enum bi_cond bcond = bi_cond_for_nir(alu->op, true);
|
|
|
|
|
|
|
|
if (bcond == BI_COND_ALWAYS)
|
|
|
|
return;
|
|
|
|
|
2020-05-01 23:31:22 +01:00
|
|
|
/* Some instructions can't compare ints */
|
|
|
|
if (float_only) {
|
|
|
|
nir_alu_type T = nir_op_infos[alu->op].input_types[0];
|
|
|
|
T = nir_alu_type_get_base_type(T);
|
|
|
|
|
|
|
|
if (T != nir_type_float)
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-03-21 22:13:49 +00:00
|
|
|
/* We found one, let's fuse it in */
|
2020-04-27 19:15:57 +01:00
|
|
|
csel->cond = bcond;
|
2020-11-05 14:13:28 +00:00
|
|
|
bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift);
|
|
|
|
bi_copy_src(csel, alu, 1, 1, constants_left, constant_shift);
|
2020-03-21 22:13:49 +00:00
|
|
|
}
|
|
|
|
|
2020-03-10 00:19:51 +00:00
|
|
|
static void
|
|
|
|
emit_alu(bi_context *ctx, nir_alu_instr *instr)
|
|
|
|
{
|
2020-04-14 23:52:21 +01:00
|
|
|
/* Try some special functions */
|
|
|
|
switch (instr->op) {
|
|
|
|
case nir_op_fexp2:
|
|
|
|
bi_emit_fexp2(ctx, instr);
|
|
|
|
return;
|
2020-04-15 00:50:24 +01:00
|
|
|
case nir_op_flog2:
|
|
|
|
bi_emit_flog2(ctx, instr);
|
|
|
|
return;
|
2020-04-14 23:52:21 +01:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Otherwise, assume it's something we can handle normally */
|
2020-03-10 00:19:51 +00:00
|
|
|
bi_instruction alu = {
|
|
|
|
.type = bi_class_for_nir_alu(instr->op),
|
2020-04-27 21:04:05 +01:00
|
|
|
.dest = pan_dest_index(&instr->dest.dest),
|
2020-03-10 00:19:51 +00:00
|
|
|
.dest_type = nir_op_infos[instr->op].output_type
|
|
|
|
| nir_dest_bit_size(instr->dest.dest),
|
|
|
|
};
|
|
|
|
|
2020-03-10 01:20:20 +00:00
|
|
|
/* TODO: Implement lowering of special functions for older Bifrost */
|
2020-10-28 12:27:07 +00:00
|
|
|
assert(alu.type != BI_SPECIAL_ADD || !(ctx->quirks & BIFROST_NO_FAST_OP));
|
2020-03-10 01:20:20 +00:00
|
|
|
|
2020-04-24 22:20:28 +01:00
|
|
|
unsigned comps = nir_dest_num_components(instr->dest.dest);
|
2020-10-02 20:49:55 +01:00
|
|
|
bool vector = comps > MAX2(1, 32 / nir_dest_bit_size(instr->dest.dest));
|
|
|
|
assert(!vector || alu.type == BI_COMBINE || alu.type == BI_MOV);
|
2020-03-10 00:19:51 +00:00
|
|
|
|
2020-04-24 22:20:28 +01:00
|
|
|
if (!instr->dest.dest.is_ssa) {
|
|
|
|
for (unsigned i = 0; i < comps; ++i)
|
|
|
|
assert(instr->dest.write_mask);
|
2020-03-10 00:19:51 +00:00
|
|
|
}
|
|
|
|
|
2020-03-10 00:32:00 +00:00
|
|
|
/* We inline constants as we go. This tracks how many constants have
|
|
|
|
* been inlined, since we're limited to 64-bits of constants per
|
|
|
|
* instruction */
|
|
|
|
|
|
|
|
unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
|
|
|
|
unsigned constants_left = (64 / dest_bits);
|
|
|
|
unsigned constant_shift = 0;
|
|
|
|
|
2020-03-31 01:54:51 +01:00
|
|
|
if (alu.type == BI_COMBINE)
|
|
|
|
constants_left = 0;
|
|
|
|
|
2020-03-10 00:19:51 +00:00
|
|
|
/* Copy sources */
|
|
|
|
|
|
|
|
unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
|
|
|
|
assert(num_inputs <= ARRAY_SIZE(alu.src));
|
|
|
|
|
2020-04-06 00:22:01 +01:00
|
|
|
for (unsigned i = 0; i < num_inputs; ++i) {
|
|
|
|
unsigned f = 0;
|
|
|
|
|
|
|
|
if (i && alu.type == BI_CSEL)
|
|
|
|
f++;
|
|
|
|
|
2020-11-05 14:13:28 +00:00
|
|
|
bi_copy_src(&alu, instr, i, i + f, &constants_left, &constant_shift);
|
2020-04-06 00:22:01 +01:00
|
|
|
}
|
2020-03-10 00:19:51 +00:00
|
|
|
|
|
|
|
/* Op-specific fixup */
|
|
|
|
switch (instr->op) {
|
|
|
|
case nir_op_fmul:
|
|
|
|
alu.src[2] = BIR_INDEX_ZERO; /* FMA */
|
2020-03-27 19:53:12 +00:00
|
|
|
alu.src_types[2] = alu.src_types[1];
|
2020-03-10 00:19:51 +00:00
|
|
|
break;
|
2020-03-10 01:02:51 +00:00
|
|
|
case nir_op_fsat:
|
2020-03-19 20:58:48 +00:00
|
|
|
alu.outmod = BIFROST_SAT; /* FMOV */
|
2020-03-10 01:02:51 +00:00
|
|
|
break;
|
2020-03-10 11:52:24 +00:00
|
|
|
case nir_op_fneg:
|
2020-03-19 20:58:48 +00:00
|
|
|
alu.src_neg[0] = true; /* FMOV */
|
2020-03-10 11:52:24 +00:00
|
|
|
break;
|
|
|
|
case nir_op_fabs:
|
2020-03-19 20:58:48 +00:00
|
|
|
alu.src_abs[0] = true; /* FMOV */
|
2020-03-10 11:52:24 +00:00
|
|
|
break;
|
2020-03-10 11:56:14 +00:00
|
|
|
case nir_op_fsub:
|
2020-03-19 20:58:48 +00:00
|
|
|
alu.src_neg[1] = true; /* FADD */
|
2020-03-10 11:56:14 +00:00
|
|
|
break;
|
2020-05-04 19:04:35 +01:00
|
|
|
case nir_op_iadd:
|
|
|
|
alu.op.imath = BI_IMATH_ADD;
|
2020-07-31 21:47:05 +01:00
|
|
|
/* Carry */
|
|
|
|
alu.src[2] = BIR_INDEX_ZERO;
|
2020-05-04 19:04:35 +01:00
|
|
|
break;
|
|
|
|
case nir_op_isub:
|
|
|
|
alu.op.imath = BI_IMATH_SUB;
|
2020-07-31 21:47:05 +01:00
|
|
|
/* Borrow */
|
|
|
|
alu.src[2] = BIR_INDEX_ZERO;
|
2020-05-04 19:04:35 +01:00
|
|
|
break;
|
2020-07-27 19:51:31 +01:00
|
|
|
case nir_op_iabs:
|
|
|
|
alu.op.special = BI_SPECIAL_IABS;
|
|
|
|
break;
|
2020-07-26 19:37:42 +01:00
|
|
|
case nir_op_inot:
|
2020-09-09 22:46:58 +01:00
|
|
|
/* no dedicated bitwise not, but we can invert sources. convert to ~(a | 0) */
|
2020-07-26 19:37:42 +01:00
|
|
|
alu.op.bitwise = BI_BITWISE_OR;
|
2020-09-09 22:46:58 +01:00
|
|
|
alu.bitwise.dest_invert = true;
|
2020-07-26 19:37:42 +01:00
|
|
|
alu.src[1] = BIR_INDEX_ZERO;
|
2020-07-26 20:18:54 +01:00
|
|
|
/* zero shift */
|
|
|
|
alu.src[2] = BIR_INDEX_ZERO;
|
2020-09-09 22:40:22 +01:00
|
|
|
alu.src_types[2] = nir_type_uint8;
|
2020-07-26 20:18:54 +01:00
|
|
|
break;
|
|
|
|
case nir_op_ishl:
|
|
|
|
alu.op.bitwise = BI_BITWISE_OR;
|
|
|
|
/* move src1 to src2 and replace with zero. underlying op is (src0 << src2) | src1 */
|
|
|
|
alu.src[2] = alu.src[1];
|
2020-09-09 22:40:22 +01:00
|
|
|
alu.src_types[2] = nir_type_uint8;
|
2020-07-26 20:18:54 +01:00
|
|
|
alu.src[1] = BIR_INDEX_ZERO;
|
2020-07-26 19:37:42 +01:00
|
|
|
break;
|
2020-07-26 23:54:14 +01:00
|
|
|
case nir_op_imul:
|
|
|
|
alu.op.imul = BI_IMUL_IMUL;
|
|
|
|
break;
|
2020-03-10 01:10:41 +00:00
|
|
|
case nir_op_fmax:
|
|
|
|
case nir_op_imax:
|
|
|
|
case nir_op_umax:
|
|
|
|
alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
|
|
|
|
break;
|
2020-03-10 01:20:20 +00:00
|
|
|
case nir_op_frcp:
|
|
|
|
alu.op.special = BI_SPECIAL_FRCP;
|
|
|
|
break;
|
|
|
|
case nir_op_frsq:
|
|
|
|
alu.op.special = BI_SPECIAL_FRSQ;
|
|
|
|
break;
|
2020-03-21 21:37:47 +00:00
|
|
|
BI_CASE_CMP(nir_op_flt)
|
|
|
|
BI_CASE_CMP(nir_op_ilt)
|
|
|
|
BI_CASE_CMP(nir_op_fge)
|
|
|
|
BI_CASE_CMP(nir_op_ige)
|
|
|
|
BI_CASE_CMP(nir_op_feq)
|
|
|
|
BI_CASE_CMP(nir_op_ieq)
|
2020-08-18 18:51:57 +01:00
|
|
|
BI_CASE_CMP(nir_op_fneu)
|
2020-03-21 21:37:47 +00:00
|
|
|
BI_CASE_CMP(nir_op_ine)
|
2020-07-26 20:41:17 +01:00
|
|
|
BI_CASE_CMP(nir_op_uge)
|
2020-10-18 21:19:15 +01:00
|
|
|
BI_CASE_CMP(nir_op_ult)
|
2020-04-27 19:15:57 +01:00
|
|
|
alu.cond = bi_cond_for_nir(instr->op, false);
|
2020-03-10 12:21:35 +00:00
|
|
|
break;
|
2020-03-28 00:28:09 +00:00
|
|
|
case nir_op_fround_even:
|
|
|
|
alu.roundmode = BIFROST_RTE;
|
|
|
|
break;
|
|
|
|
case nir_op_fceil:
|
|
|
|
alu.roundmode = BIFROST_RTP;
|
|
|
|
break;
|
|
|
|
case nir_op_ffloor:
|
|
|
|
alu.roundmode = BIFROST_RTN;
|
|
|
|
break;
|
|
|
|
case nir_op_ftrunc:
|
|
|
|
alu.roundmode = BIFROST_RTZ;
|
|
|
|
break;
|
2020-04-28 19:36:17 +01:00
|
|
|
case nir_op_iand:
|
|
|
|
alu.op.bitwise = BI_BITWISE_AND;
|
2020-07-26 20:18:54 +01:00
|
|
|
/* zero shift */
|
|
|
|
alu.src[2] = BIR_INDEX_ZERO;
|
2020-09-09 22:40:22 +01:00
|
|
|
alu.src_types[2] = nir_type_uint8;
|
2020-04-28 19:36:17 +01:00
|
|
|
break;
|
|
|
|
case nir_op_ior:
|
|
|
|
alu.op.bitwise = BI_BITWISE_OR;
|
2020-07-26 20:18:54 +01:00
|
|
|
/* zero shift */
|
|
|
|
alu.src[2] = BIR_INDEX_ZERO;
|
2020-09-09 22:40:22 +01:00
|
|
|
alu.src_types[2] = nir_type_uint8;
|
2020-04-28 19:36:17 +01:00
|
|
|
break;
|
|
|
|
case nir_op_ixor:
|
|
|
|
alu.op.bitwise = BI_BITWISE_XOR;
|
2020-07-26 20:18:54 +01:00
|
|
|
/* zero shift */
|
|
|
|
alu.src[2] = BIR_INDEX_ZERO;
|
2020-09-09 22:40:22 +01:00
|
|
|
alu.src_types[2] = nir_type_uint8;
|
2020-04-28 19:36:17 +01:00
|
|
|
break;
|
2020-07-04 23:26:42 +01:00
|
|
|
case nir_op_f2i32:
|
|
|
|
alu.roundmode = BIFROST_RTZ;
|
|
|
|
break;
|
2020-06-03 00:29:25 +01:00
|
|
|
|
|
|
|
case nir_op_f2f16:
|
|
|
|
case nir_op_i2i16:
|
|
|
|
case nir_op_u2u16: {
|
|
|
|
if (nir_src_bit_size(instr->src[0].src) != 32)
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Should have been const folded */
|
|
|
|
assert(!nir_src_is_const(instr->src[0].src));
|
|
|
|
|
|
|
|
alu.src_types[1] = alu.src_types[0];
|
|
|
|
alu.src[1] = alu.src[0];
|
|
|
|
|
|
|
|
unsigned last = nir_dest_num_components(instr->dest.dest) - 1;
|
|
|
|
assert(last <= 1);
|
|
|
|
|
|
|
|
alu.swizzle[1][0] = instr->src[0].swizzle[last];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2020-03-10 00:19:51 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2020-10-02 20:49:55 +01:00
|
|
|
if (alu.type == BI_MOV && vector) {
|
|
|
|
alu.type = BI_COMBINE;
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < comps; ++i) {
|
|
|
|
alu.src[i] = alu.src[0];
|
|
|
|
alu.swizzle[i][0] = instr->src[0].swizzle[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-21 22:13:49 +00:00
|
|
|
if (alu.type == BI_CSEL) {
|
2020-03-22 01:19:14 +00:00
|
|
|
/* Default to csel3 */
|
2020-04-27 19:15:57 +01:00
|
|
|
alu.cond = BI_COND_NE;
|
2020-04-06 00:22:01 +01:00
|
|
|
alu.src[1] = BIR_INDEX_ZERO;
|
|
|
|
alu.src_types[1] = alu.src_types[0];
|
2020-03-22 01:19:14 +00:00
|
|
|
|
2020-05-01 22:34:47 +01:00
|
|
|
/* TODO: Reenable cond fusing when we can split up registers
|
|
|
|
* when scheduling */
|
|
|
|
#if 0
|
2020-05-01 23:31:22 +01:00
|
|
|
bi_fuse_cond(&alu, instr->src[0],
|
|
|
|
&constants_left, &constant_shift, comps, false);
|
2020-05-01 22:34:47 +01:00
|
|
|
#endif
|
2020-03-21 22:13:49 +00:00
|
|
|
}
|
|
|
|
|
2020-03-10 00:19:51 +00:00
|
|
|
bi_emit(ctx, alu);
|
|
|
|
}
|
|
|
|
|
2020-10-06 15:31:04 +01:00
|
|
|
/* TEXS instructions assume normal 2D f32 operation but are more
|
2020-04-21 17:15:29 +01:00
|
|
|
* space-efficient and with simpler RA/scheduling requirements*/
|
|
|
|
|
|
|
|
static void
|
2020-10-06 15:40:16 +01:00
|
|
|
emit_texs(bi_context *ctx, nir_tex_instr *instr)
|
2020-04-21 17:15:29 +01:00
|
|
|
{
|
2020-04-21 18:00:44 +01:00
|
|
|
bi_instruction tex = {
|
2020-10-06 15:31:04 +01:00
|
|
|
.type = BI_TEXS,
|
2020-04-30 21:10:55 +01:00
|
|
|
.texture = {
|
|
|
|
.texture_index = instr->texture_index,
|
|
|
|
.sampler_index = instr->sampler_index,
|
2020-08-03 17:47:57 +01:00
|
|
|
.compute_lod = instr->op == nir_texop_tex,
|
2020-04-30 21:10:55 +01:00
|
|
|
},
|
2020-04-27 21:04:05 +01:00
|
|
|
.dest = pan_dest_index(&instr->dest),
|
2020-04-21 18:00:44 +01:00
|
|
|
.dest_type = instr->dest_type,
|
|
|
|
.src_types = { nir_type_float32, nir_type_float32 },
|
2020-04-24 22:20:28 +01:00
|
|
|
.vector_channels = 4
|
2020-04-21 18:00:44 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < instr->num_srcs; ++i) {
|
2020-04-27 21:04:05 +01:00
|
|
|
int index = pan_src_index(&instr->src[i].src);
|
2020-05-27 16:43:37 +01:00
|
|
|
|
|
|
|
/* We were checked ahead-of-time */
|
|
|
|
if (instr->src[i].src_type == nir_tex_src_lod)
|
|
|
|
continue;
|
|
|
|
|
2020-04-21 18:00:44 +01:00
|
|
|
assert (instr->src[i].src_type == nir_tex_src_coord);
|
|
|
|
|
|
|
|
tex.src[0] = index;
|
|
|
|
tex.src[1] = index;
|
|
|
|
tex.swizzle[0][0] = 0;
|
|
|
|
tex.swizzle[1][0] = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
bi_emit(ctx, tex);
|
2020-04-21 17:15:29 +01:00
|
|
|
}
|
|
|
|
|
2020-10-06 16:18:16 +01:00
|
|
|
/* Returns dimension with 0 special casing cubemaps. Shamelessly copied from Midgard */
|
|
|
|
static unsigned
|
|
|
|
bifrost_tex_format(enum glsl_sampler_dim dim)
|
|
|
|
{
|
|
|
|
switch (dim) {
|
|
|
|
case GLSL_SAMPLER_DIM_1D:
|
|
|
|
case GLSL_SAMPLER_DIM_BUF:
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
case GLSL_SAMPLER_DIM_2D:
|
|
|
|
case GLSL_SAMPLER_DIM_MS:
|
|
|
|
case GLSL_SAMPLER_DIM_EXTERNAL:
|
|
|
|
case GLSL_SAMPLER_DIM_RECT:
|
|
|
|
return 2;
|
|
|
|
|
|
|
|
case GLSL_SAMPLER_DIM_3D:
|
|
|
|
return 3;
|
|
|
|
|
|
|
|
case GLSL_SAMPLER_DIM_CUBE:
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
default:
|
|
|
|
DBG("Unknown sampler dim type\n");
|
|
|
|
assert(0);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static enum bifrost_texture_format_full
|
|
|
|
bi_texture_format(nir_alu_type T, enum bifrost_outmod outmod)
|
|
|
|
{
|
|
|
|
switch (T) {
|
|
|
|
case nir_type_float16: return BIFROST_TEXTURE_FORMAT_F16 + outmod;
|
|
|
|
case nir_type_float32: return BIFROST_TEXTURE_FORMAT_F32 + outmod;
|
|
|
|
case nir_type_uint16: return BIFROST_TEXTURE_FORMAT_U16;
|
|
|
|
case nir_type_int16: return BIFROST_TEXTURE_FORMAT_S16;
|
|
|
|
case nir_type_uint32: return BIFROST_TEXTURE_FORMAT_U32;
|
|
|
|
case nir_type_int32: return BIFROST_TEXTURE_FORMAT_S32;
|
|
|
|
default: unreachable("Invalid type for texturing");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-11-03 13:22:42 +00:00
|
|
|
/* Array indices are specified as 32-bit uints, need to convert. In .z component from NIR */
|
|
|
|
static unsigned
|
|
|
|
bi_emit_array_index(bi_context *ctx, unsigned idx, nir_alu_type T, unsigned *c)
|
|
|
|
{
|
|
|
|
/* For (u)int we can just passthrough */
|
|
|
|
nir_alu_type base = nir_alu_type_get_base_type(T);
|
|
|
|
if (base == nir_type_int || base == nir_type_uint) {
|
|
|
|
*c = 2;
|
|
|
|
return idx;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Otherwise we convert */
|
|
|
|
assert(T == nir_type_float16 || T == nir_type_float32);
|
|
|
|
|
|
|
|
/* OpenGL ES 3.2 specification section 8.14.2 ("Coordinate Wrapping and
|
|
|
|
* Texel Selection") defines the layer to be taken from clamp(RNE(r),
|
|
|
|
* 0, dt - 1). So we use roundmode RTE, clamping is handled at the data
|
|
|
|
* structure level */
|
|
|
|
bi_instruction f2i = {
|
|
|
|
.type = BI_CONVERT,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.src = { idx },
|
|
|
|
.src_types = { T },
|
|
|
|
.swizzle = { { 2 } },
|
|
|
|
.roundmode = BIFROST_RTE
|
|
|
|
};
|
|
|
|
|
|
|
|
*c = 0;
|
|
|
|
bi_emit(ctx, f2i);
|
|
|
|
return f2i.dest;
|
|
|
|
}
|
|
|
|
|
2020-10-06 16:46:50 +01:00
|
|
|
/* TEXC's explicit and bias LOD modes requires the LOD to be transformed to a
|
|
|
|
* 16-bit 8:8 fixed-point format. We lower as:
|
|
|
|
*
|
|
|
|
* F32_TO_S32(clamp(x, -16.0, +16.0) * 256.0) & 0xFFFF =
|
|
|
|
* MKVEC(F32_TO_S32(clamp(x * 1.0/16.0, -1.0, 1.0) * (16.0 * 256.0)), #0)
|
|
|
|
*/
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
bi_emit_lod_88(bi_context *ctx, unsigned lod, bool fp16)
|
|
|
|
{
|
|
|
|
nir_alu_type T = fp16 ? nir_type_float16 : nir_type_float32;
|
|
|
|
|
|
|
|
/* Sort of arbitrary. Must be less than 128.0, greater than or equal to
|
|
|
|
* the max LOD (16 since we cap at 2^16 texture dimensions), and
|
|
|
|
* preferably small to minimize precision loss */
|
|
|
|
const float max_lod = 16.0;
|
|
|
|
|
|
|
|
/* FMA.f16/f32.sat_signed, saturated, lod, #1.0/max_lod, #0 */
|
|
|
|
bi_instruction fsat = {
|
|
|
|
.type = BI_FMA,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_float32,
|
|
|
|
.src = { lod, BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
|
|
|
|
.src_types = { T, nir_type_float32, nir_type_float32 },
|
|
|
|
.outmod = BIFROST_SAT_SIGNED,
|
|
|
|
.roundmode = BIFROST_RTE,
|
|
|
|
.constant = {
|
|
|
|
.u64 = fui(1.0 / max_lod)
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* FMA.f32 scaled, saturated, lod, #(max_lod * 256.0), #0 */
|
|
|
|
bi_instruction fmul = {
|
|
|
|
.type = BI_FMA,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = T,
|
|
|
|
.src = { fsat.dest, BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
|
|
|
|
.src_types = { nir_type_float32, nir_type_float32, nir_type_float32 },
|
|
|
|
.roundmode = BIFROST_RTE,
|
|
|
|
.constant = {
|
|
|
|
.u64 = fui(max_lod * 256.0)
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* F32_TO_S32 s32, scaled */
|
|
|
|
bi_instruction f2i = {
|
|
|
|
.type = BI_CONVERT,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_int32,
|
|
|
|
.src = { fmul.dest },
|
|
|
|
.src_types = { T },
|
|
|
|
.roundmode = BIFROST_RTZ
|
|
|
|
};
|
|
|
|
|
|
|
|
/* MKVEC.v2i16 s32.h0, #0 */
|
|
|
|
bi_instruction mkvec = {
|
|
|
|
.type = BI_SELECT,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_int16,
|
|
|
|
.src = { f2i.dest, BIR_INDEX_ZERO },
|
|
|
|
.src_types = { nir_type_int16, nir_type_int16 },
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, fsat);
|
|
|
|
bi_emit(ctx, fmul);
|
|
|
|
bi_emit(ctx, f2i);
|
|
|
|
bi_emit(ctx, mkvec);
|
|
|
|
|
2020-10-09 00:31:41 +01:00
|
|
|
return mkvec.dest;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* FETCH takes a 32-bit staging register containing the LOD as an integer in
|
|
|
|
* the bottom 16-bits and (if present) the cube face index in the top 16-bits.
|
|
|
|
* TODO: Cube face.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
bi_emit_lod_cube(bi_context *ctx, unsigned lod)
|
|
|
|
{
|
|
|
|
/* MKVEC.v2i16 out, lod.h0, #0 */
|
|
|
|
bi_instruction mkvec = {
|
|
|
|
.type = BI_SELECT,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_int16,
|
|
|
|
.src = { lod, BIR_INDEX_ZERO },
|
|
|
|
.src_types = { nir_type_int16, nir_type_int16 },
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, mkvec);
|
|
|
|
|
2020-10-06 16:46:50 +01:00
|
|
|
return mkvec.dest;
|
|
|
|
}
|
|
|
|
|
2020-10-17 10:32:41 +01:00
|
|
|
/* The hardware specifies texel offsets and multisample indices together as a
|
|
|
|
* u8vec4 <offset, ms index>. By default all are zero, so if have either a
|
|
|
|
* nonzero texel offset or a nonzero multisample index, we build a u8vec4 with
|
|
|
|
* the bits we need and return that to be passed as a staging register. Else we
|
|
|
|
* return 0 to avoid allocating a data register when everything is zero. */
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
bi_emit_tex_offset_ms_index(bi_context *ctx, nir_tex_instr *instr)
|
|
|
|
{
|
|
|
|
unsigned dest = 0;
|
|
|
|
|
|
|
|
/* TODO: offsets */
|
|
|
|
assert(nir_tex_instr_src_index(instr, nir_tex_src_offset) < 0);
|
|
|
|
|
2020-10-26 08:24:32 +00:00
|
|
|
int ms_idx = nir_tex_instr_src_index(instr, nir_tex_src_ms_index);
|
2020-10-17 10:32:41 +01:00
|
|
|
if (ms_idx >= 0 &&
|
|
|
|
(!nir_src_is_const(instr->src[ms_idx].src) ||
|
|
|
|
nir_src_as_uint(instr->src[ms_idx].src) != 0)) {
|
|
|
|
bi_instruction shl = {
|
|
|
|
.type = BI_BITWISE,
|
|
|
|
.op.bitwise = BI_BITWISE_OR,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.src = {
|
|
|
|
pan_src_index(&instr->src[ms_idx].src),
|
|
|
|
BIR_INDEX_ZERO,
|
|
|
|
BIR_INDEX_CONSTANT | 0,
|
|
|
|
},
|
|
|
|
.src_types = {
|
|
|
|
nir_type_uint32,
|
|
|
|
nir_type_uint32,
|
|
|
|
nir_type_uint8,
|
|
|
|
},
|
|
|
|
.constant.u8[0] = 24,
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, shl);
|
|
|
|
dest = shl.dest;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dest;
|
|
|
|
}
|
|
|
|
|
2020-11-02 18:33:55 +00:00
|
|
|
static void
|
|
|
|
bi_lower_cube_coord(bi_context *ctx, unsigned coord,
|
|
|
|
unsigned *face, unsigned *s, unsigned *t)
|
|
|
|
{
|
|
|
|
/* Compute max { |x|, |y|, |z| } */
|
|
|
|
bi_instruction cubeface1 = {
|
|
|
|
.type = BI_SPECIAL_FMA,
|
|
|
|
.op.special = BI_SPECIAL_CUBEFACE1,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_float32,
|
|
|
|
.src = { coord, coord, coord },
|
|
|
|
.src_types = { nir_type_float32, nir_type_float32, nir_type_float32 },
|
|
|
|
.swizzle = { {0}, {1}, {2} }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Calculate packed exponent / face / infinity. In reality this reads
|
|
|
|
* the destination from cubeface1 but that's handled by lowering */
|
|
|
|
bi_instruction cubeface2 = {
|
|
|
|
.type = BI_SPECIAL_ADD,
|
|
|
|
.op.special = BI_SPECIAL_CUBEFACE2,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.src = { coord, coord, coord },
|
|
|
|
.src_types = { nir_type_float32, nir_type_float32, nir_type_float32 },
|
|
|
|
.swizzle = { {0}, {1}, {2} }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Select S coordinate */
|
|
|
|
bi_instruction cube_ssel = {
|
|
|
|
.type = BI_SPECIAL_ADD,
|
|
|
|
.op.special = BI_SPECIAL_CUBE_SSEL,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_float32,
|
|
|
|
.src = { coord, coord, cubeface2.dest },
|
|
|
|
.src_types = { nir_type_float32, nir_type_float32, nir_type_uint32 },
|
|
|
|
.swizzle = { {2}, {0} }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Select T coordinate */
|
|
|
|
bi_instruction cube_tsel = {
|
|
|
|
.type = BI_SPECIAL_ADD,
|
|
|
|
.op.special = BI_SPECIAL_CUBE_TSEL,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_float32,
|
|
|
|
.src = { coord, coord, cubeface2.dest },
|
|
|
|
.src_types = { nir_type_float32, nir_type_float32, nir_type_uint32 },
|
|
|
|
.swizzle = { {1}, {2} }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* The OpenGL ES specification requires us to transform an input vector
|
|
|
|
* (x, y, z) to the coordinate, given the selected S/T:
|
|
|
|
*
|
|
|
|
* (1/2 ((s / max{x,y,z}) + 1), 1/2 ((t / max{x, y, z}) + 1))
|
|
|
|
*
|
|
|
|
* We implement (s shown, t similar) in a form friendlier to FMA
|
|
|
|
* instructions, and clamp coordinates at the end for correct
|
|
|
|
* NaN/infinity handling:
|
|
|
|
*
|
|
|
|
* fsat(s * (0.5 * (1 / max{x, y, z})) + 0.5)
|
|
|
|
*
|
|
|
|
* Take the reciprocal of max{x, y, z}
|
|
|
|
*/
|
|
|
|
|
|
|
|
bi_instruction frcp = {
|
|
|
|
.type = BI_SPECIAL_ADD,
|
|
|
|
.op.special = BI_SPECIAL_FRCP,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_float32,
|
|
|
|
.src = { cubeface1.dest },
|
|
|
|
.src_types = { nir_type_float32 },
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Calculate 0.5 * (1.0 / max{x, y, z}) */
|
|
|
|
bi_instruction fma1 = {
|
|
|
|
.type = BI_FMA,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_float32,
|
|
|
|
.src = { frcp.dest, BIR_INDEX_CONSTANT | 0, BIR_INDEX_ZERO },
|
|
|
|
.src_types = { nir_type_float32, nir_type_float32, nir_type_float32 },
|
|
|
|
.constant.u64 = 0x3f000000, /* 0.5f */
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Transform the s coordinate */
|
|
|
|
bi_instruction fma2 = {
|
|
|
|
.type = BI_FMA,
|
|
|
|
.outmod = BIFROST_SAT,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_float32,
|
|
|
|
.src = { fma1.dest, cube_ssel.dest, BIR_INDEX_CONSTANT | 0 },
|
|
|
|
.src_types = { nir_type_float32, nir_type_float32, nir_type_float32 },
|
|
|
|
.constant.u64 = 0x3f000000, /* 0.5f */
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Transform the t coordinate */
|
|
|
|
bi_instruction fma3 = {
|
|
|
|
.type = BI_FMA,
|
|
|
|
.outmod = BIFROST_SAT,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_float32,
|
|
|
|
.src = { fma1.dest, cube_tsel.dest, BIR_INDEX_CONSTANT | 0 },
|
|
|
|
.src_types = { nir_type_float32, nir_type_float32, nir_type_float32 },
|
|
|
|
.constant.u64 = 0x3f000000, /* 0.5f */
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, cubeface1);
|
|
|
|
bi_emit(ctx, cubeface2);
|
|
|
|
bi_emit(ctx, cube_ssel);
|
|
|
|
bi_emit(ctx, cube_tsel);
|
|
|
|
bi_emit(ctx, frcp);
|
|
|
|
bi_emit(ctx, fma1);
|
|
|
|
bi_emit(ctx, fma2);
|
|
|
|
bi_emit(ctx, fma3);
|
|
|
|
|
|
|
|
/* Cube face is stored in bit[29:31], we don't apply the shift here
|
|
|
|
* because the TEXS_CUBE and TEXC instructions expect the face index to
|
|
|
|
* be at this position.
|
|
|
|
*/
|
|
|
|
*face = cubeface2.dest;
|
|
|
|
*s = fma2.dest;
|
|
|
|
*t = fma3.dest;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
texc_pack_cube_coord(bi_context *ctx, unsigned coord,
|
|
|
|
unsigned *face_s, unsigned *t)
|
|
|
|
{
|
|
|
|
unsigned face, s;
|
|
|
|
|
|
|
|
bi_lower_cube_coord(ctx, coord, &face, &s, t);
|
|
|
|
|
|
|
|
bi_instruction and1 = {
|
|
|
|
.type = BI_BITWISE,
|
|
|
|
.op.bitwise = BI_BITWISE_AND,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.src = { face, BIR_INDEX_CONSTANT | 0, BIR_INDEX_ZERO },
|
|
|
|
.src_types = { nir_type_uint32, nir_type_uint32, nir_type_uint8 },
|
|
|
|
.constant.u64 = 0xe0000000,
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_instruction and2 = {
|
|
|
|
.type = BI_BITWISE,
|
|
|
|
.op.bitwise = BI_BITWISE_AND,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.src = { s, BIR_INDEX_CONSTANT | 0, BIR_INDEX_ZERO },
|
|
|
|
.src_types = { nir_type_uint32, nir_type_uint32, nir_type_uint8 },
|
|
|
|
.constant.u64 = 0x1fffffff,
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_instruction or = {
|
|
|
|
.type = BI_BITWISE,
|
|
|
|
.op.bitwise = BI_BITWISE_OR,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.src = { and1.dest, and2.dest, BIR_INDEX_ZERO },
|
|
|
|
.src_types = { nir_type_uint32, nir_type_uint32, nir_type_uint8 },
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, and1);
|
|
|
|
bi_emit(ctx, and2);
|
|
|
|
bi_emit(ctx, or);
|
|
|
|
|
|
|
|
/* packed cube-face + s */
|
|
|
|
*face_s = or.dest;
|
|
|
|
}
|
|
|
|
|
2020-10-09 00:01:29 +01:00
|
|
|
/* Map to the main texture op used. Some of these (txd in particular) will
|
|
|
|
* lower to multiple texture ops with different opcodes (GRDESC_DER + TEX in
|
|
|
|
* sequence). We assume that lowering is handled elsewhere.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static enum bifrost_tex_op
|
|
|
|
bi_tex_op(nir_texop op)
|
|
|
|
{
|
|
|
|
switch (op) {
|
|
|
|
case nir_texop_tex:
|
|
|
|
case nir_texop_txb:
|
|
|
|
case nir_texop_txl:
|
|
|
|
case nir_texop_txd:
|
|
|
|
case nir_texop_tex_prefetch:
|
|
|
|
return BIFROST_TEX_OP_TEX;
|
|
|
|
case nir_texop_txf:
|
|
|
|
case nir_texop_txf_ms:
|
|
|
|
case nir_texop_txf_ms_fb:
|
|
|
|
case nir_texop_txf_ms_mcs:
|
|
|
|
case nir_texop_tg4:
|
|
|
|
return BIFROST_TEX_OP_FETCH;
|
|
|
|
case nir_texop_txs:
|
|
|
|
case nir_texop_lod:
|
|
|
|
case nir_texop_query_levels:
|
|
|
|
case nir_texop_texture_samples:
|
|
|
|
case nir_texop_samples_identical:
|
|
|
|
unreachable("should've been lowered");
|
|
|
|
default:
|
|
|
|
unreachable("unsupported tex op");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-10-06 16:32:55 +01:00
|
|
|
/* Data registers required by texturing in the order they appear. All are
|
|
|
|
* optional, the texture operation descriptor determines which are present.
|
|
|
|
* Note since 3D arrays are not permitted at an API level, Z_COORD and
|
|
|
|
* ARRAY/SHADOW are exlusive, so TEXC in practice reads at most 8 registers */
|
|
|
|
|
|
|
|
enum bifrost_tex_dreg {
|
|
|
|
BIFROST_TEX_DREG_Z_COORD = 0,
|
|
|
|
BIFROST_TEX_DREG_Y_DELTAS = 1,
|
|
|
|
BIFROST_TEX_DREG_LOD = 2,
|
|
|
|
BIFROST_TEX_DREG_GRDESC_HI = 3,
|
|
|
|
BIFROST_TEX_DREG_SHADOW = 4,
|
|
|
|
BIFROST_TEX_DREG_ARRAY = 5,
|
|
|
|
BIFROST_TEX_DREG_OFFSETMS = 6,
|
|
|
|
BIFROST_TEX_DREG_SAMPLER = 7,
|
|
|
|
BIFROST_TEX_DREG_TEXTURE = 8,
|
|
|
|
BIFROST_TEX_DREG_COUNT,
|
|
|
|
};
|
|
|
|
|
2020-04-21 17:15:29 +01:00
|
|
|
static void
|
2020-10-06 15:40:16 +01:00
|
|
|
emit_texc(bi_context *ctx, nir_tex_instr *instr)
|
2020-04-21 17:15:29 +01:00
|
|
|
{
|
2020-10-06 16:18:16 +01:00
|
|
|
/* TODO: support more with other encodings */
|
|
|
|
assert(instr->sampler_index < 16);
|
|
|
|
|
|
|
|
/* TODO: support more ops */
|
|
|
|
switch (instr->op) {
|
|
|
|
case nir_texop_tex:
|
|
|
|
case nir_texop_txl:
|
2020-10-07 23:32:32 +01:00
|
|
|
case nir_texop_txb:
|
2020-10-09 00:30:44 +01:00
|
|
|
case nir_texop_txf:
|
2020-10-17 10:32:41 +01:00
|
|
|
case nir_texop_txf_ms:
|
2020-10-06 16:18:16 +01:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("Unsupported texture op");
|
|
|
|
}
|
|
|
|
|
|
|
|
bi_instruction tex = {
|
|
|
|
.type = BI_TEXC,
|
|
|
|
.dest = pan_dest_index(&instr->dest),
|
|
|
|
.dest_type = instr->dest_type,
|
|
|
|
.src_types = {
|
|
|
|
/* Staging registers */
|
|
|
|
nir_type_uint32,
|
|
|
|
nir_type_float32, nir_type_float32,
|
|
|
|
nir_type_uint32
|
|
|
|
},
|
|
|
|
.vector_channels = 4
|
|
|
|
};
|
|
|
|
|
|
|
|
struct bifrost_texture_operation desc = {
|
|
|
|
.sampler_index_or_mode = instr->sampler_index,
|
|
|
|
.index = instr->texture_index,
|
|
|
|
.immediate_indices = 1, /* TODO */
|
2020-10-09 00:01:29 +01:00
|
|
|
.op = bi_tex_op(instr->op),
|
2020-10-06 16:18:16 +01:00
|
|
|
.offset_or_bias_disable = false, /* TODO */
|
|
|
|
.shadow_or_clamp_disable = instr->is_shadow,
|
2020-11-03 13:23:22 +00:00
|
|
|
.array = instr->is_array,
|
2020-10-06 16:18:16 +01:00
|
|
|
.dimension = bifrost_tex_format(instr->sampler_dim),
|
2020-10-09 00:30:44 +01:00
|
|
|
.format = bi_texture_format(instr->dest_type, BIFROST_NONE), /* TODO */
|
2020-10-06 16:18:16 +01:00
|
|
|
.mask = (1 << tex.vector_channels) - 1
|
|
|
|
};
|
|
|
|
|
2020-10-09 00:30:44 +01:00
|
|
|
switch (desc.op) {
|
|
|
|
case BIFROST_TEX_OP_TEX:
|
|
|
|
desc.lod_or_fetch = BIFROST_LOD_MODE_COMPUTE;
|
|
|
|
break;
|
|
|
|
case BIFROST_TEX_OP_FETCH:
|
|
|
|
/* TODO: gathers */
|
|
|
|
desc.lod_or_fetch = BIFROST_TEXTURE_FETCH_TEXEL;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("texture op unsupported");
|
|
|
|
}
|
|
|
|
|
2020-10-06 16:32:55 +01:00
|
|
|
/* 32-bit indices to be allocated as consecutive data registers. */
|
|
|
|
unsigned dregs[BIFROST_TEX_DREG_COUNT] = { 0 };
|
2020-11-03 13:23:01 +00:00
|
|
|
unsigned dregs_swiz[BIFROST_TEX_DREG_COUNT] = { 0 };
|
2020-10-06 16:32:55 +01:00
|
|
|
|
2020-10-06 16:18:16 +01:00
|
|
|
for (unsigned i = 0; i < instr->num_srcs; ++i) {
|
|
|
|
unsigned index = pan_src_index(&instr->src[i].src);
|
2020-10-06 16:46:50 +01:00
|
|
|
unsigned sz = nir_src_bit_size(instr->src[i].src);
|
|
|
|
ASSERTED nir_alu_type base = nir_tex_instr_src_type(instr, i);
|
2020-11-03 13:23:22 +00:00
|
|
|
nir_alu_type T = base | sz;
|
2020-10-06 16:18:16 +01:00
|
|
|
|
|
|
|
switch (instr->src[i].src_type) {
|
|
|
|
case nir_tex_src_coord:
|
2020-11-02 18:33:55 +00:00
|
|
|
if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
|
|
|
|
texc_pack_cube_coord(ctx, index,
|
|
|
|
&tex.src[1], &tex.src[2]);
|
|
|
|
} else {
|
|
|
|
tex.src[1] = index;
|
|
|
|
tex.src[2] = index;
|
|
|
|
tex.swizzle[1][0] = 0;
|
|
|
|
tex.swizzle[2][0] = 1;
|
2020-11-03 13:23:22 +00:00
|
|
|
|
|
|
|
unsigned components = nir_src_num_components(instr->src[i].src);
|
|
|
|
assert(components == 2 || components == 3);
|
|
|
|
|
|
|
|
if (components == 2) {
|
|
|
|
/* nothing to do */
|
|
|
|
} else if (desc.array) {
|
|
|
|
/* 2D array */
|
|
|
|
dregs[BIFROST_TEX_DREG_ARRAY] =
|
|
|
|
bi_emit_array_index(ctx, index, T,
|
|
|
|
&dregs_swiz[BIFROST_TEX_DREG_ARRAY]);
|
|
|
|
} else {
|
|
|
|
/* 3D */
|
|
|
|
dregs[BIFROST_TEX_DREG_Z_COORD] = index;
|
|
|
|
dregs_swiz[BIFROST_TEX_DREG_Z_COORD] = 2;
|
|
|
|
}
|
2020-11-02 18:33:55 +00:00
|
|
|
}
|
2020-10-06 16:18:16 +01:00
|
|
|
break;
|
2020-10-07 23:32:32 +01:00
|
|
|
|
2020-10-06 16:46:50 +01:00
|
|
|
case nir_tex_src_lod:
|
|
|
|
if (nir_src_is_const(instr->src[i].src) && nir_src_as_uint(instr->src[i].src) == 0) {
|
2020-10-09 00:30:44 +01:00
|
|
|
desc.lod_or_fetch = BIFROST_LOD_MODE_ZERO;
|
|
|
|
} else if (desc.op == BIFROST_TEX_OP_TEX) {
|
2020-10-06 16:46:50 +01:00
|
|
|
assert(base == nir_type_float);
|
2020-10-07 23:32:32 +01:00
|
|
|
|
2020-10-06 16:46:50 +01:00
|
|
|
assert(sz == 16 || sz == 32);
|
|
|
|
dregs[BIFROST_TEX_DREG_LOD] =
|
|
|
|
bi_emit_lod_88(ctx, index, sz == 16);
|
2020-10-09 00:30:44 +01:00
|
|
|
desc.lod_or_fetch = BIFROST_LOD_MODE_EXPLICIT;
|
|
|
|
} else {
|
|
|
|
assert(desc.op == BIFROST_TEX_OP_FETCH);
|
|
|
|
assert(base == nir_type_uint || base == nir_type_int);
|
|
|
|
assert(sz == 16 || sz == 32);
|
|
|
|
|
|
|
|
dregs[BIFROST_TEX_DREG_LOD] =
|
|
|
|
bi_emit_lod_cube(ctx, index);
|
2020-10-06 16:46:50 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
2020-10-07 23:32:32 +01:00
|
|
|
|
|
|
|
case nir_tex_src_bias:
|
|
|
|
/* Upper 16-bits interpreted as a clamp, leave zero */
|
2020-10-09 00:30:44 +01:00
|
|
|
assert(desc.op == BIFROST_TEX_OP_TEX);
|
2020-10-07 23:32:32 +01:00
|
|
|
assert(base == nir_type_float);
|
|
|
|
assert(sz == 16 || sz == 32);
|
|
|
|
dregs[BIFROST_TEX_DREG_LOD] =
|
|
|
|
bi_emit_lod_88(ctx, index, sz == 16);
|
2020-10-09 00:30:44 +01:00
|
|
|
desc.lod_or_fetch = BIFROST_LOD_MODE_BIAS;
|
2020-10-07 23:32:32 +01:00
|
|
|
break;
|
|
|
|
|
2020-10-17 10:32:41 +01:00
|
|
|
case nir_tex_src_ms_index:
|
|
|
|
case nir_tex_src_offset:
|
|
|
|
if (desc.offset_or_bias_disable)
|
|
|
|
break;
|
|
|
|
|
|
|
|
dregs[BIFROST_TEX_DREG_OFFSETMS] =
|
|
|
|
bi_emit_tex_offset_ms_index(ctx, instr);
|
|
|
|
if (dregs[BIFROST_TEX_DREG_OFFSETMS])
|
|
|
|
desc.offset_or_bias_disable = true;
|
|
|
|
break;
|
|
|
|
|
2020-10-06 16:18:16 +01:00
|
|
|
default:
|
|
|
|
unreachable("Unhandled src type in texc emit");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-10-06 16:32:55 +01:00
|
|
|
/* Allocate data registers contiguously */
|
|
|
|
bi_instruction combine = {
|
|
|
|
.type = BI_COMBINE,
|
|
|
|
.dest_type = nir_type_uint32,
|
|
|
|
.dest = bi_make_temp(ctx),
|
|
|
|
.src_types = {
|
|
|
|
nir_type_uint32, nir_type_uint32,
|
|
|
|
nir_type_uint32, nir_type_uint32,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
unsigned dreg_index = 0;
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < ARRAY_SIZE(dregs); ++i) {
|
|
|
|
assert(dreg_index < 4);
|
|
|
|
|
2020-11-03 13:23:01 +00:00
|
|
|
if (dregs[i]) {
|
|
|
|
combine.swizzle[dreg_index][0] = dregs_swiz[i];
|
2020-10-06 16:32:55 +01:00
|
|
|
combine.src[dreg_index++] = dregs[i];
|
2020-11-03 13:23:01 +00:00
|
|
|
}
|
2020-10-06 16:32:55 +01:00
|
|
|
}
|
|
|
|
|
2020-10-17 10:30:05 +01:00
|
|
|
if (dreg_index > 1) {
|
|
|
|
/* Pass combined data registers together */
|
2020-10-06 16:32:55 +01:00
|
|
|
tex.src[0] = combine.dest;
|
|
|
|
bi_emit(ctx, combine);
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < dreg_index; ++i)
|
|
|
|
tex.swizzle[0][i] = i;
|
2020-10-17 10:30:05 +01:00
|
|
|
} else if (dreg_index == 1) {
|
|
|
|
tex.src[0] = combine.src[0];
|
2020-11-03 13:23:01 +00:00
|
|
|
tex.swizzle[0][0] = combine.swizzle[0][0];
|
2020-10-17 10:30:05 +01:00
|
|
|
} else {
|
|
|
|
tex.src[0] = tex.dest;
|
2020-10-06 16:32:55 +01:00
|
|
|
}
|
|
|
|
|
2020-10-06 16:18:16 +01:00
|
|
|
/* Pass the texture operation descriptor in src2 */
|
|
|
|
tex.src[3] = BIR_INDEX_CONSTANT;
|
|
|
|
memcpy(&tex.constant.u64, &desc, sizeof(desc));
|
|
|
|
|
|
|
|
bi_emit(ctx, tex);
|
2020-04-21 17:15:29 +01:00
|
|
|
}
|
|
|
|
|
2020-11-03 13:23:32 +00:00
|
|
|
/* Simple textures ops correspond to NIR tex or txl with LOD = 0 on 2D (or cube
|
|
|
|
* map, TODO) textures. Anything else needs a complete texture op. */
|
2020-05-27 16:41:42 +01:00
|
|
|
|
|
|
|
static bool
|
|
|
|
bi_is_normal_tex(gl_shader_stage stage, nir_tex_instr *instr)
|
|
|
|
{
|
2020-10-06 15:24:56 +01:00
|
|
|
if (instr->op == nir_texop_tex)
|
|
|
|
return true;
|
2020-05-27 16:41:42 +01:00
|
|
|
|
|
|
|
if (instr->op != nir_texop_txl)
|
|
|
|
return false;
|
|
|
|
|
2020-10-06 15:24:56 +01:00
|
|
|
int lod_idx = nir_tex_instr_src_index(instr, nir_tex_src_lod);
|
|
|
|
if (lod_idx < 0)
|
|
|
|
return true;
|
2020-05-27 16:41:42 +01:00
|
|
|
|
2020-10-06 15:24:56 +01:00
|
|
|
nir_src lod = instr->src[lod_idx].src;
|
|
|
|
return nir_src_is_const(lod) && nir_src_as_uint(lod) == 0;
|
2020-05-27 16:41:42 +01:00
|
|
|
}
|
|
|
|
|
2020-04-21 17:15:29 +01:00
|
|
|
static void
|
|
|
|
emit_tex(bi_context *ctx, nir_tex_instr *instr)
|
|
|
|
{
|
|
|
|
nir_alu_type base = nir_alu_type_get_base_type(instr->dest_type);
|
|
|
|
unsigned sz = nir_dest_bit_size(instr->dest);
|
|
|
|
instr->dest_type = base | sz;
|
|
|
|
|
2020-05-27 16:41:42 +01:00
|
|
|
bool is_normal = bi_is_normal_tex(ctx->stage, instr);
|
2020-04-21 17:15:29 +01:00
|
|
|
bool is_2d = instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
|
|
|
|
instr->sampler_dim == GLSL_SAMPLER_DIM_EXTERNAL;
|
|
|
|
bool is_f = base == nir_type_float && (sz == 16 || sz == 32);
|
|
|
|
|
2020-11-03 13:23:32 +00:00
|
|
|
if (is_normal && is_2d && is_f && !instr->is_shadow && !instr->is_array)
|
2020-10-06 15:40:16 +01:00
|
|
|
emit_texs(ctx, instr);
|
2020-04-21 17:15:29 +01:00
|
|
|
else
|
2020-10-06 15:40:16 +01:00
|
|
|
emit_texc(ctx, instr);
|
2020-04-21 17:15:29 +01:00
|
|
|
}
|
|
|
|
|
2020-03-05 22:10:46 +00:00
|
|
|
static void
|
|
|
|
emit_instr(bi_context *ctx, struct nir_instr *instr)
|
|
|
|
{
|
|
|
|
switch (instr->type) {
|
|
|
|
case nir_instr_type_load_const:
|
|
|
|
emit_load_const(ctx, nir_instr_as_load_const(instr));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_instr_type_intrinsic:
|
|
|
|
emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_instr_type_alu:
|
|
|
|
emit_alu(ctx, nir_instr_as_alu(instr));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_instr_type_tex:
|
|
|
|
emit_tex(ctx, nir_instr_as_tex(instr));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_instr_type_jump:
|
|
|
|
emit_jump(ctx, nir_instr_as_jump(instr));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_instr_type_ssa_undef:
|
2020-10-15 13:47:40 +01:00
|
|
|
unreachable("should've been lowered");
|
2020-03-05 22:10:46 +00:00
|
|
|
|
|
|
|
default:
|
2020-04-21 17:15:29 +01:00
|
|
|
unreachable("Unhandled instruction type");
|
2020-03-05 22:10:46 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2020-03-05 15:25:19 +00:00
|
|
|
|
|
|
|
static bi_block *
|
|
|
|
create_empty_block(bi_context *ctx)
|
|
|
|
{
|
|
|
|
bi_block *blk = rzalloc(ctx, bi_block);
|
|
|
|
|
2020-03-11 18:35:38 +00:00
|
|
|
blk->base.predecessors = _mesa_set_create(blk,
|
2020-03-05 15:25:19 +00:00
|
|
|
_mesa_hash_pointer,
|
|
|
|
_mesa_key_pointer_equal);
|
|
|
|
|
|
|
|
return blk;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bi_block *
|
|
|
|
emit_block(bi_context *ctx, nir_block *block)
|
|
|
|
{
|
2020-03-05 21:45:16 +00:00
|
|
|
if (ctx->after_block) {
|
|
|
|
ctx->current_block = ctx->after_block;
|
|
|
|
ctx->after_block = NULL;
|
|
|
|
} else {
|
|
|
|
ctx->current_block = create_empty_block(ctx);
|
|
|
|
}
|
|
|
|
|
2020-03-11 18:35:38 +00:00
|
|
|
list_addtail(&ctx->current_block->base.link, &ctx->blocks);
|
|
|
|
list_inithead(&ctx->current_block->base.instructions);
|
2020-03-05 15:25:19 +00:00
|
|
|
|
|
|
|
nir_foreach_instr(instr, block) {
|
2020-03-05 22:10:46 +00:00
|
|
|
emit_instr(ctx, instr);
|
2020-03-05 15:25:19 +00:00
|
|
|
++ctx->instruction_count;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ctx->current_block;
|
|
|
|
}
|
|
|
|
|
2020-03-05 21:45:16 +00:00
|
|
|
/* Emits an unconditional branch to the end of the current block, returning a
|
|
|
|
* pointer so the user can fill in details */
|
|
|
|
|
|
|
|
static bi_instruction *
|
|
|
|
bi_emit_branch(bi_context *ctx)
|
|
|
|
{
|
|
|
|
bi_instruction branch = {
|
|
|
|
.type = BI_BRANCH,
|
2020-05-01 23:13:54 +01:00
|
|
|
.cond = BI_COND_ALWAYS
|
2020-03-05 21:45:16 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
return bi_emit(ctx, branch);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Sets a condition for a branch by examing the NIR condition. If we're
|
|
|
|
* familiar with the condition, we unwrap it to fold it into the branch
|
|
|
|
* instruction. Otherwise, we consume the condition directly. We
|
|
|
|
* generally use 1-bit booleans which allows us to use small types for
|
|
|
|
* the conditions.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void
|
|
|
|
bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
|
|
|
|
{
|
|
|
|
/* TODO: Try to unwrap instead of always bailing */
|
2020-04-27 21:04:05 +01:00
|
|
|
branch->src[0] = pan_src_index(cond);
|
2020-03-05 21:45:16 +00:00
|
|
|
branch->src[1] = BIR_INDEX_ZERO;
|
2020-05-28 17:39:14 +01:00
|
|
|
branch->src_types[0] = branch->src_types[1] = nir_type_uint |
|
|
|
|
nir_src_bit_size(*cond);
|
2020-05-01 23:13:54 +01:00
|
|
|
branch->cond = invert ? BI_COND_EQ : BI_COND_NE;
|
2020-03-05 21:45:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
emit_if(bi_context *ctx, nir_if *nif)
|
|
|
|
{
|
|
|
|
bi_block *before_block = ctx->current_block;
|
|
|
|
|
|
|
|
/* Speculatively emit the branch, but we can't fill it in until later */
|
|
|
|
bi_instruction *then_branch = bi_emit_branch(ctx);
|
|
|
|
bi_set_branch_cond(then_branch, &nif->condition, true);
|
|
|
|
|
|
|
|
/* Emit the two subblocks. */
|
|
|
|
bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
|
|
|
|
bi_block *end_then_block = ctx->current_block;
|
|
|
|
|
|
|
|
/* Emit a jump from the end of the then block to the end of the else */
|
|
|
|
bi_instruction *then_exit = bi_emit_branch(ctx);
|
|
|
|
|
|
|
|
/* Emit second block, and check if it's empty */
|
|
|
|
|
|
|
|
int count_in = ctx->instruction_count;
|
|
|
|
bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
|
|
|
|
bi_block *end_else_block = ctx->current_block;
|
|
|
|
ctx->after_block = create_empty_block(ctx);
|
|
|
|
|
|
|
|
/* Now that we have the subblocks emitted, fix up the branches */
|
|
|
|
|
|
|
|
assert(then_block);
|
|
|
|
assert(else_block);
|
|
|
|
|
|
|
|
if (ctx->instruction_count == count_in) {
|
|
|
|
/* The else block is empty, so don't emit an exit jump */
|
|
|
|
bi_remove_instruction(then_exit);
|
2020-05-01 23:13:54 +01:00
|
|
|
then_branch->branch_target = ctx->after_block;
|
2020-05-27 23:27:08 +01:00
|
|
|
pan_block_add_successor(&end_then_block->base, &ctx->after_block->base); /* fallthrough */
|
2020-03-05 21:45:16 +00:00
|
|
|
} else {
|
2020-05-01 23:13:54 +01:00
|
|
|
then_branch->branch_target = else_block;
|
|
|
|
then_exit->branch_target = ctx->after_block;
|
|
|
|
pan_block_add_successor(&end_then_block->base, &then_exit->branch_target->base);
|
2020-05-27 23:27:08 +01:00
|
|
|
pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
|
2020-03-05 21:45:16 +00:00
|
|
|
}
|
|
|
|
|
2020-05-01 23:13:54 +01:00
|
|
|
pan_block_add_successor(&before_block->base, &then_branch->branch_target->base); /* then_branch */
|
2020-03-11 18:35:38 +00:00
|
|
|
pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
|
2020-03-05 21:45:16 +00:00
|
|
|
}
|
|
|
|
|
2020-03-05 22:03:53 +00:00
|
|
|
static void
|
|
|
|
emit_loop(bi_context *ctx, nir_loop *nloop)
|
|
|
|
{
|
|
|
|
/* Remember where we are */
|
|
|
|
bi_block *start_block = ctx->current_block;
|
|
|
|
|
|
|
|
bi_block *saved_break = ctx->break_block;
|
|
|
|
bi_block *saved_continue = ctx->continue_block;
|
|
|
|
|
|
|
|
ctx->continue_block = create_empty_block(ctx);
|
|
|
|
ctx->break_block = create_empty_block(ctx);
|
|
|
|
ctx->after_block = ctx->continue_block;
|
|
|
|
|
|
|
|
/* Emit the body itself */
|
|
|
|
emit_cf_list(ctx, &nloop->body);
|
|
|
|
|
|
|
|
/* Branch back to loop back */
|
|
|
|
bi_instruction *br_back = bi_emit_branch(ctx);
|
2020-05-01 23:13:54 +01:00
|
|
|
br_back->branch_target = ctx->continue_block;
|
2020-03-11 18:35:38 +00:00
|
|
|
pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
|
|
|
|
pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
|
2020-03-05 22:03:53 +00:00
|
|
|
|
|
|
|
ctx->after_block = ctx->break_block;
|
|
|
|
|
|
|
|
/* Pop off */
|
|
|
|
ctx->break_block = saved_break;
|
|
|
|
ctx->continue_block = saved_continue;
|
|
|
|
++ctx->loop_count;
|
|
|
|
}
|
|
|
|
|
2020-03-05 15:25:19 +00:00
|
|
|
static bi_block *
|
|
|
|
emit_cf_list(bi_context *ctx, struct exec_list *list)
|
|
|
|
{
|
|
|
|
bi_block *start_block = NULL;
|
|
|
|
|
|
|
|
foreach_list_typed(nir_cf_node, node, node, list) {
|
|
|
|
switch (node->type) {
|
|
|
|
case nir_cf_node_block: {
|
|
|
|
bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
|
|
|
|
|
|
|
|
if (!start_block)
|
|
|
|
start_block = block;
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case nir_cf_node_if:
|
|
|
|
emit_if(ctx, nir_cf_node_as_if(node));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_cf_node_loop:
|
|
|
|
emit_loop(ctx, nir_cf_node_as_loop(node));
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
unreachable("Unknown control flow");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return start_block;
|
|
|
|
}
|
2020-03-03 00:47:11 +00:00
|
|
|
|
2020-03-05 15:11:39 +00:00
|
|
|
static int
|
|
|
|
glsl_type_size(const struct glsl_type *type, bool bindless)
|
|
|
|
{
|
|
|
|
return glsl_count_attribute_slots(type, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bi_optimize_nir(nir_shader *nir)
|
|
|
|
{
|
|
|
|
bool progress;
|
|
|
|
unsigned lower_flrp = 16 | 32 | 64;
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
|
|
|
|
NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
|
|
|
|
|
|
|
|
nir_lower_tex_options lower_tex_options = {
|
|
|
|
.lower_txs_lod = true,
|
|
|
|
.lower_txp = ~0,
|
|
|
|
.lower_tex_without_implicit_lod = true,
|
|
|
|
.lower_txd = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
|
2020-03-06 21:29:35 +00:00
|
|
|
NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
|
|
|
|
NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
|
2020-03-05 15:11:39 +00:00
|
|
|
|
|
|
|
do {
|
|
|
|
progress = false;
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_lower_var_copies);
|
|
|
|
NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_copy_prop);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_remove_phis);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_dce);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_dead_cf);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_cse);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_algebraic);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_constant_folding);
|
|
|
|
|
|
|
|
if (lower_flrp != 0) {
|
|
|
|
bool lower_flrp_progress = false;
|
|
|
|
NIR_PASS(lower_flrp_progress,
|
|
|
|
nir,
|
|
|
|
nir_lower_flrp,
|
|
|
|
lower_flrp,
|
2020-07-23 03:13:16 +01:00
|
|
|
false /* always_precise */);
|
2020-03-05 15:11:39 +00:00
|
|
|
if (lower_flrp_progress) {
|
|
|
|
NIR_PASS(progress, nir,
|
|
|
|
nir_opt_constant_folding);
|
|
|
|
progress = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Nothing should rematerialize any flrps, so we only
|
|
|
|
* need to do this lowering once.
|
|
|
|
*/
|
|
|
|
lower_flrp = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_opt_undef);
|
2020-10-15 13:47:40 +01:00
|
|
|
NIR_PASS(progress, nir, nir_undef_to_zero);
|
|
|
|
|
2020-03-05 15:11:39 +00:00
|
|
|
NIR_PASS(progress, nir, nir_opt_loop_unroll,
|
|
|
|
nir_var_shader_in |
|
|
|
|
nir_var_shader_out |
|
|
|
|
nir_var_function_temp);
|
|
|
|
} while (progress);
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_opt_algebraic_late);
|
2020-03-21 21:37:47 +00:00
|
|
|
NIR_PASS(progress, nir, nir_lower_bool_to_int32);
|
2020-03-10 12:20:59 +00:00
|
|
|
NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
|
2020-03-06 21:29:35 +00:00
|
|
|
NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
|
|
|
|
NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
|
2020-03-05 15:11:39 +00:00
|
|
|
|
|
|
|
/* Take us out of SSA */
|
|
|
|
NIR_PASS(progress, nir, nir_lower_locals_to_regs);
|
2020-03-09 23:56:35 +00:00
|
|
|
NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
|
2020-03-22 21:31:23 +00:00
|
|
|
NIR_PASS(progress, nir, nir_convert_from_ssa, true);
|
2020-03-19 21:21:49 +00:00
|
|
|
}
|
|
|
|
|
2020-10-17 11:08:17 +01:00
|
|
|
panfrost_program *
|
|
|
|
bifrost_compile_shader_nir(void *mem_ctx, nir_shader *nir,
|
2020-10-08 09:09:56 +01:00
|
|
|
const struct panfrost_compile_inputs *inputs)
|
2020-03-03 00:47:11 +00:00
|
|
|
{
|
2020-10-17 11:08:17 +01:00
|
|
|
panfrost_program *program = rzalloc(mem_ctx, panfrost_program);
|
|
|
|
|
2020-04-30 08:29:10 +01:00
|
|
|
bifrost_debug = debug_get_option_bifrost_debug();
|
|
|
|
|
2020-03-03 00:47:11 +00:00
|
|
|
bi_context *ctx = rzalloc(NULL, bi_context);
|
|
|
|
ctx->nir = nir;
|
2020-03-05 15:11:39 +00:00
|
|
|
ctx->stage = nir->info.stage;
|
2020-10-08 09:09:56 +01:00
|
|
|
ctx->quirks = bifrost_get_quirks(inputs->gpu_id);
|
2020-10-12 14:00:02 +01:00
|
|
|
ctx->is_blend = inputs->is_blend;
|
|
|
|
ctx->blend_desc = inputs->blend.bifrost_blend_desc;
|
|
|
|
memcpy(ctx->blend_constants, inputs->blend.constants, sizeof(ctx->blend_constants));
|
2020-03-05 15:25:19 +00:00
|
|
|
list_inithead(&ctx->blocks);
|
2020-03-03 00:47:11 +00:00
|
|
|
|
2020-03-05 15:11:39 +00:00
|
|
|
/* Lower gl_Position pre-optimisation, but after lowering vars to ssa
|
|
|
|
* (so we don't accidentally duplicate the epilogue since mesa/st has
|
|
|
|
* messed with our I/O quite a bit already) */
|
|
|
|
|
|
|
|
NIR_PASS_V(nir, nir_lower_vars_to_ssa);
|
|
|
|
|
|
|
|
if (ctx->stage == MESA_SHADER_VERTEX) {
|
|
|
|
NIR_PASS_V(nir, nir_lower_viewport_transform);
|
|
|
|
NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
|
|
|
|
}
|
|
|
|
|
|
|
|
NIR_PASS_V(nir, nir_split_var_copies);
|
|
|
|
NIR_PASS_V(nir, nir_lower_global_vars_to_local);
|
|
|
|
NIR_PASS_V(nir, nir_lower_var_copies);
|
|
|
|
NIR_PASS_V(nir, nir_lower_vars_to_ssa);
|
2020-06-10 23:54:25 +01:00
|
|
|
NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
|
|
|
|
glsl_type_size, 0);
|
2020-03-05 15:11:39 +00:00
|
|
|
NIR_PASS_V(nir, nir_lower_ssbo);
|
2020-11-04 14:05:57 +00:00
|
|
|
NIR_PASS_V(nir, pan_nir_lower_zs_store);
|
2020-10-09 15:45:44 +01:00
|
|
|
// TODO: re-enable when fp16 is flipped on
|
|
|
|
// NIR_PASS_V(nir, nir_lower_mediump_outputs);
|
2020-03-05 15:11:39 +00:00
|
|
|
|
|
|
|
bi_optimize_nir(nir);
|
2020-04-30 08:29:10 +01:00
|
|
|
|
2020-11-04 14:05:57 +00:00
|
|
|
NIR_PASS_V(nir, pan_nir_reorder_writeout);
|
|
|
|
|
2020-11-02 18:41:13 +00:00
|
|
|
if (bifrost_debug & BIFROST_DBG_SHADERS && !nir->info.internal) {
|
2020-04-30 08:29:10 +01:00
|
|
|
nir_print_shader(nir, stdout);
|
|
|
|
}
|
2020-03-03 00:47:11 +00:00
|
|
|
|
2020-08-18 13:31:42 +01:00
|
|
|
panfrost_nir_assign_sysvals(&ctx->sysvals, ctx, nir);
|
2020-03-10 20:20:18 +00:00
|
|
|
program->sysval_count = ctx->sysvals.sysval_count;
|
|
|
|
memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
|
2020-04-24 00:26:01 +01:00
|
|
|
ctx->blend_types = program->blend_types;
|
2020-03-10 20:20:18 +00:00
|
|
|
|
2020-03-05 15:25:19 +00:00
|
|
|
nir_foreach_function(func, nir) {
|
|
|
|
if (!func->impl)
|
|
|
|
continue;
|
|
|
|
|
2020-03-06 14:43:43 +00:00
|
|
|
ctx->impl = func->impl;
|
2020-03-05 15:25:19 +00:00
|
|
|
emit_cf_list(ctx, &func->impl->body);
|
|
|
|
break; /* TODO: Multi-function shaders */
|
|
|
|
}
|
|
|
|
|
2020-05-28 19:44:33 +01:00
|
|
|
unsigned block_source_count = 0;
|
|
|
|
|
2020-03-19 21:21:49 +00:00
|
|
|
bi_foreach_block(ctx, _block) {
|
|
|
|
bi_block *block = (bi_block *) _block;
|
2020-05-28 19:44:33 +01:00
|
|
|
|
|
|
|
/* Name blocks now that we're done emitting so the order is
|
|
|
|
* consistent */
|
|
|
|
block->base.name = block_source_count++;
|
|
|
|
|
2020-03-22 21:31:23 +00:00
|
|
|
bi_lower_combine(ctx, block);
|
2020-03-19 21:21:49 +00:00
|
|
|
}
|
|
|
|
|
2020-03-11 19:10:32 +00:00
|
|
|
bool progress = false;
|
|
|
|
|
|
|
|
do {
|
|
|
|
progress = false;
|
|
|
|
|
|
|
|
bi_foreach_block(ctx, _block) {
|
|
|
|
bi_block *block = (bi_block *) _block;
|
|
|
|
progress |= bi_opt_dead_code_eliminate(ctx, block);
|
|
|
|
}
|
|
|
|
} while(progress);
|
|
|
|
|
2020-11-02 18:41:13 +00:00
|
|
|
if (bifrost_debug & BIFROST_DBG_SHADERS && !nir->info.internal)
|
2020-04-30 08:29:10 +01:00
|
|
|
bi_print_shader(ctx, stdout);
|
2020-03-07 00:25:00 +00:00
|
|
|
bi_schedule(ctx);
|
2020-03-12 00:39:36 +00:00
|
|
|
bi_register_allocate(ctx);
|
2020-11-02 18:41:13 +00:00
|
|
|
if (bifrost_debug & BIFROST_DBG_SHADERS && !nir->info.internal)
|
2020-04-30 08:29:10 +01:00
|
|
|
bi_print_shader(ctx, stdout);
|
2020-10-17 11:08:17 +01:00
|
|
|
|
|
|
|
util_dynarray_init(&program->compiled, NULL);
|
2020-03-12 18:16:22 +00:00
|
|
|
bi_pack(ctx, &program->compiled);
|
2020-04-30 08:29:10 +01:00
|
|
|
|
2020-10-13 11:26:11 +01:00
|
|
|
memcpy(program->blend_ret_offsets, ctx->blend_ret_offsets, sizeof(program->blend_ret_offsets));
|
|
|
|
|
2020-11-02 18:41:13 +00:00
|
|
|
if (bifrost_debug & BIFROST_DBG_SHADERS && !nir->info.internal)
|
2020-04-30 08:29:10 +01:00
|
|
|
disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
|
2020-03-05 15:11:39 +00:00
|
|
|
|
2020-10-15 01:48:08 +01:00
|
|
|
program->tls_size = ctx->tls_size;
|
|
|
|
|
2020-03-03 00:47:11 +00:00
|
|
|
ralloc_free(ctx);
|
2020-10-17 11:08:17 +01:00
|
|
|
|
|
|
|
return program;
|
2020-03-03 00:47:11 +00:00
|
|
|
}
|