pan/bi: Add preliminary LOAD_UNIFORM implementation

Lots of things are missing (indirect access, UBOs) but we have this
stubbed out for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
This commit is contained in:
Alyssa Rosenzweig 2020-03-06 09:52:09 -05:00 committed by Marge Bot
parent 48910e8388
commit 1ead0d3488
4 changed files with 30 additions and 4 deletions

View File

@ -122,6 +122,7 @@ bi_class_name(enum bi_class cl)
case BI_FMA: return "fma";
case BI_FREXP: return "frexp";
case BI_LOAD: return "load";
case BI_LOAD_UNIFORM: return "load_uniform";
case BI_LOAD_ATTR: return "load_attr";
case BI_LOAD_VAR: return "load_var";
case BI_LOAD_VAR_ADDRESS: return "load_var_address";
@ -290,7 +291,7 @@ bi_print_instruction(bi_instruction *ins, FILE *fp)
if (ins->type == BI_MINMAX)
fprintf(fp, "%s", bi_minmax_mode_name(ins->minmax));
else if (ins->type == BI_LOAD_ATTR || ins->type == BI_LOAD_VAR_ADDRESS)
else if (ins->type == BI_LOAD_ATTR || ins->type == BI_LOAD_VAR_ADDRESS || ins->type == BI_LOAD_UNIFORM)
bi_print_load(&ins->load, fp);
else if (ins->type == BI_LOAD_VAR)
bi_print_load_vary(&ins->load_vary, fp);

View File

@ -39,6 +39,7 @@ unsigned bi_class_props[BI_NUM_CLASSES] = {
[BI_FMA] = BI_ROUNDMODE | BI_SCHED_FMA,
[BI_FREXP] = BI_SCHED_ALL,
[BI_LOAD] = BI_SCHED_HI_LATENCY,
[BI_LOAD_UNIFORM] = BI_SCHED_HI_LATENCY,
[BI_LOAD_ATTR] = BI_SCHED_HI_LATENCY,
[BI_LOAD_VAR] = BI_SCHED_HI_LATENCY,
[BI_LOAD_VAR_ADDRESS] = BI_SCHED_HI_LATENCY,

View File

@ -165,6 +165,24 @@ bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
bi_emit(ctx, st);
}
static void
bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
{
/* TODO: Indirect access */
bi_instruction ld = {
.type = BI_LOAD_UNIFORM,
.load = bi_direct_load_for_instr(instr),
.dest = bir_dest_index(&instr->dest),
.dest_type = nir_intrinsic_type(instr),
.src = {
BIR_INDEX_ZERO /* TODO: UBOs */
}
};
bi_emit(ctx, ld);
}
static void
emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
{
@ -192,6 +210,11 @@ emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
else
unreachable("Unsupported shader stage");
break;
case nir_intrinsic_load_uniform:
bi_emit_ld_uniform(ctx, instr);
break;
default:
/* todo */
break;

View File

@ -59,6 +59,7 @@ enum bi_class {
BI_FMA,
BI_FREXP,
BI_LOAD,
BI_LOAD_UNIFORM,
BI_LOAD_ATTR,
BI_LOAD_VAR,
BI_LOAD_VAR_ADDRESS,
@ -112,12 +113,12 @@ extern unsigned bi_class_props[BI_NUM_CLASSES];
/* It can't get any worse than csel4... can it? */
#define BIR_SRC_COUNT 4
/* Class-specific data for BI_LD_ATTR, BI_LD_VAR_ADDR */
/* Class-specific data for BI_LOAD, BI_LD_ATTR, BI_LD_VAR_ADDR */
struct bi_load {
/* Note: no indirects here */
/* Note: LD_ATTR does not support indirects */
unsigned location;
/* Only for BI_LD_ATTR. But number of vector channels */
/* Number of vector channels */
unsigned channels;
};