2020-03-03 00:47:11 +00:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2020 Collabora Ltd.
|
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
|
|
* to deal in the Software without restriction, including without limitation
|
|
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice (including the next
|
|
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
|
|
* Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
|
|
|
* SOFTWARE.
|
|
|
|
*
|
|
|
|
* Authors (Collabora):
|
|
|
|
* Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "main/mtypes.h"
|
|
|
|
#include "compiler/glsl/glsl_to_nir.h"
|
|
|
|
#include "compiler/nir_types.h"
|
|
|
|
#include "compiler/nir/nir_builder.h"
|
|
|
|
|
|
|
|
#include "disassemble.h"
|
|
|
|
#include "bifrost_compile.h"
|
2020-03-10 12:20:59 +00:00
|
|
|
#include "bifrost_nir.h"
|
2020-03-03 00:47:11 +00:00
|
|
|
#include "compiler.h"
|
2020-03-03 19:27:05 +00:00
|
|
|
#include "bi_quirks.h"
|
2020-03-05 15:25:19 +00:00
|
|
|
#include "bi_print.h"
|
|
|
|
|
|
|
|
static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
|
2020-03-05 22:10:46 +00:00
|
|
|
static bi_instruction *bi_emit_branch(bi_context *ctx);
|
2020-03-06 14:26:20 +00:00
|
|
|
static void bi_schedule_barrier(bi_context *ctx);
|
2020-03-05 22:10:46 +00:00
|
|
|
|
|
|
|
static void
|
|
|
|
emit_jump(bi_context *ctx, nir_jump_instr *instr)
|
|
|
|
{
|
|
|
|
bi_instruction *branch = bi_emit_branch(ctx);
|
|
|
|
|
|
|
|
switch (instr->type) {
|
|
|
|
case nir_jump_break:
|
|
|
|
branch->branch.target = ctx->break_block;
|
|
|
|
break;
|
|
|
|
case nir_jump_continue:
|
|
|
|
branch->branch.target = ctx->continue_block;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("Unhandled jump type");
|
|
|
|
}
|
|
|
|
|
2020-03-11 18:35:38 +00:00
|
|
|
pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
|
2020-03-05 22:10:46 +00:00
|
|
|
}
|
|
|
|
|
2020-03-09 23:52:56 +00:00
|
|
|
static bi_instruction
|
|
|
|
bi_load(enum bi_class T, nir_intrinsic_instr *instr)
|
2020-03-05 22:50:18 +00:00
|
|
|
{
|
2020-03-09 23:52:56 +00:00
|
|
|
bi_instruction load = {
|
|
|
|
.type = T,
|
2020-04-24 22:20:28 +01:00
|
|
|
.vector_channels = instr->num_components,
|
2020-03-09 23:52:56 +00:00
|
|
|
.src = { BIR_INDEX_CONSTANT },
|
2020-04-15 01:09:00 +01:00
|
|
|
.src_types = { nir_type_uint32 },
|
2020-03-09 23:52:56 +00:00
|
|
|
.constant = { .u64 = nir_intrinsic_base(instr) },
|
2020-03-05 22:50:18 +00:00
|
|
|
};
|
|
|
|
|
2020-03-09 23:52:56 +00:00
|
|
|
const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
|
|
|
|
|
|
|
|
if (info->has_dest)
|
|
|
|
load.dest = bir_dest_index(&instr->dest);
|
|
|
|
|
|
|
|
if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
|
|
|
|
load.dest_type = nir_intrinsic_type(instr);
|
|
|
|
|
2020-03-05 22:50:18 +00:00
|
|
|
nir_src *offset = nir_get_io_offset_src(instr);
|
|
|
|
|
|
|
|
if (nir_src_is_const(*offset))
|
2020-03-09 23:52:56 +00:00
|
|
|
load.constant.u64 += nir_src_as_uint(*offset);
|
2020-03-05 22:50:18 +00:00
|
|
|
else
|
2020-03-09 23:52:56 +00:00
|
|
|
load.src[0] = bir_src_index(offset);
|
2020-03-05 22:50:18 +00:00
|
|
|
|
2020-03-09 23:52:56 +00:00
|
|
|
return load;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
|
|
|
|
ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
|
|
|
|
ins.load_vary.reuse = false; /* TODO */
|
|
|
|
ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
|
2020-03-18 15:55:10 +00:00
|
|
|
ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
|
|
|
|
|
|
|
|
if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
|
|
|
|
/* Zero it out for direct */
|
|
|
|
ins.src[1] = BIR_INDEX_ZERO;
|
|
|
|
} else {
|
|
|
|
/* R61 contains sample mask stuff, TODO RA XXX */
|
|
|
|
ins.src[1] = BIR_INDEX_REGISTER | 61;
|
|
|
|
}
|
|
|
|
|
2020-03-05 22:50:18 +00:00
|
|
|
bi_emit(ctx, ins);
|
|
|
|
}
|
|
|
|
|
2020-03-06 14:26:44 +00:00
|
|
|
static void
|
|
|
|
bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
if (!ctx->emitted_atest) {
|
|
|
|
bi_instruction ins = {
|
2020-03-19 03:02:12 +00:00
|
|
|
.type = BI_ATEST,
|
|
|
|
.src = {
|
|
|
|
BIR_INDEX_REGISTER | 60 /* TODO: RA */,
|
|
|
|
bir_src_index(&instr->src[0])
|
|
|
|
},
|
|
|
|
.src_types = {
|
|
|
|
nir_type_uint32,
|
2020-04-24 00:03:44 +01:00
|
|
|
nir_intrinsic_type(instr)
|
2020-03-19 03:02:12 +00:00
|
|
|
},
|
|
|
|
.swizzle = {
|
|
|
|
{ 0 },
|
|
|
|
{ 3, 0 } /* swizzle out the alpha */
|
|
|
|
},
|
|
|
|
.dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
|
|
|
|
.dest_type = nir_type_uint32,
|
2020-03-06 14:26:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, ins);
|
|
|
|
bi_schedule_barrier(ctx);
|
|
|
|
ctx->emitted_atest = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bi_instruction blend = {
|
|
|
|
.type = BI_BLEND,
|
|
|
|
.blend_location = nir_intrinsic_base(instr),
|
|
|
|
.src = {
|
2020-04-10 04:04:41 +01:00
|
|
|
bir_src_index(&instr->src[0]),
|
2020-03-19 03:12:23 +00:00
|
|
|
BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
|
2020-03-09 18:09:04 +00:00
|
|
|
},
|
2020-03-12 01:45:32 +00:00
|
|
|
.src_types = {
|
2020-04-24 00:03:44 +01:00
|
|
|
nir_intrinsic_type(instr),
|
2020-04-10 04:04:41 +01:00
|
|
|
nir_type_uint32
|
2020-03-12 01:45:32 +00:00
|
|
|
},
|
2020-03-09 18:09:04 +00:00
|
|
|
.swizzle = {
|
2020-04-10 04:04:41 +01:00
|
|
|
{ 0, 1, 2, 3 },
|
|
|
|
{ 0 }
|
2020-03-19 03:12:23 +00:00
|
|
|
},
|
|
|
|
.dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
|
|
|
|
.dest_type = nir_type_uint32,
|
2020-04-24 22:20:28 +01:00
|
|
|
.vector_channels = 4
|
2020-03-06 14:26:44 +00:00
|
|
|
};
|
|
|
|
|
2020-04-24 00:26:01 +01:00
|
|
|
assert(blend.blend_location < 8);
|
|
|
|
assert(ctx->blend_types);
|
|
|
|
ctx->blend_types[blend.blend_location] = blend.src_types[0];
|
|
|
|
|
2020-03-06 14:26:44 +00:00
|
|
|
bi_emit(ctx, blend);
|
|
|
|
bi_schedule_barrier(ctx);
|
|
|
|
}
|
|
|
|
|
2020-03-21 19:25:54 +00:00
|
|
|
static bi_instruction
|
|
|
|
bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
bi_instruction ld = bi_load(T, instr);
|
|
|
|
ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
|
|
|
|
ld.src[2] = BIR_INDEX_REGISTER | 62;
|
|
|
|
ld.src[3] = 0;
|
|
|
|
ld.src_types[1] = nir_type_uint32;
|
|
|
|
ld.src_types[2] = nir_type_uint32;
|
|
|
|
ld.src_types[3] = nir_intrinsic_type(instr);
|
|
|
|
return ld;
|
|
|
|
}
|
|
|
|
|
2020-03-06 14:44:19 +00:00
|
|
|
static void
|
|
|
|
bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
2020-03-21 19:25:54 +00:00
|
|
|
bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
|
2020-03-09 23:52:56 +00:00
|
|
|
address.dest = bi_make_temp(ctx);
|
2020-03-20 16:25:08 +00:00
|
|
|
address.dest_type = nir_type_uint32;
|
2020-04-24 22:20:28 +01:00
|
|
|
address.vector_channels = 3;
|
2020-03-06 14:44:19 +00:00
|
|
|
|
2020-04-15 01:20:37 +01:00
|
|
|
unsigned nr = nir_intrinsic_src_components(instr, 0);
|
|
|
|
assert(nir_intrinsic_write_mask(instr) == ((1 << nr) - 1));
|
|
|
|
|
2020-03-06 14:44:19 +00:00
|
|
|
bi_instruction st = {
|
|
|
|
.type = BI_STORE_VAR,
|
|
|
|
.src = {
|
2020-03-20 16:25:08 +00:00
|
|
|
bir_src_index(&instr->src[0]),
|
|
|
|
address.dest, address.dest, address.dest,
|
2020-03-09 18:09:04 +00:00
|
|
|
},
|
2020-03-12 01:45:32 +00:00
|
|
|
.src_types = {
|
2020-03-20 16:25:08 +00:00
|
|
|
nir_type_uint32,
|
|
|
|
nir_type_uint32, nir_type_uint32, nir_type_uint32,
|
2020-03-12 01:45:32 +00:00
|
|
|
},
|
2020-03-09 18:09:04 +00:00
|
|
|
.swizzle = {
|
2020-04-15 01:20:37 +01:00
|
|
|
{ 0 },
|
2020-03-20 16:25:08 +00:00
|
|
|
{ 0 }, { 1 }, { 2}
|
2020-03-20 16:38:53 +00:00
|
|
|
},
|
2020-04-24 22:20:28 +01:00
|
|
|
.vector_channels = nr,
|
2020-03-06 14:44:19 +00:00
|
|
|
};
|
|
|
|
|
2020-04-15 01:20:37 +01:00
|
|
|
for (unsigned i = 0; i < nr; ++i)
|
|
|
|
st.swizzle[0][i] = i;
|
|
|
|
|
2020-03-06 14:44:19 +00:00
|
|
|
bi_emit(ctx, address);
|
|
|
|
bi_emit(ctx, st);
|
|
|
|
}
|
|
|
|
|
2020-03-06 14:52:09 +00:00
|
|
|
static void
|
|
|
|
bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
2020-03-09 23:52:56 +00:00
|
|
|
bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
|
|
|
|
ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
|
2020-03-10 20:20:18 +00:00
|
|
|
|
|
|
|
/* TODO: Indirect access, since we need to multiply by the element
|
|
|
|
* size. I believe we can get this lowering automatically via
|
|
|
|
* nir_lower_io (as mul instructions) with the proper options, but this
|
|
|
|
* is TODO */
|
|
|
|
assert(ld.src[0] & BIR_INDEX_CONSTANT);
|
|
|
|
ld.constant.u64 += ctx->sysvals.sysval_count;
|
|
|
|
ld.constant.u64 *= 16;
|
|
|
|
|
2020-03-06 14:52:09 +00:00
|
|
|
bi_emit(ctx, ld);
|
|
|
|
}
|
|
|
|
|
2020-03-10 20:20:18 +00:00
|
|
|
static void
|
|
|
|
bi_emit_sysval(bi_context *ctx, nir_instr *instr,
|
|
|
|
unsigned nr_components, unsigned offset)
|
|
|
|
{
|
|
|
|
nir_dest nir_dest;
|
|
|
|
|
|
|
|
/* Figure out which uniform this is */
|
|
|
|
int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
|
|
|
|
void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
|
|
|
|
|
|
|
|
/* Sysvals are prefix uniforms */
|
|
|
|
unsigned uniform = ((uintptr_t) val) - 1;
|
|
|
|
|
|
|
|
/* Emit the read itself -- this is never indirect */
|
|
|
|
|
|
|
|
bi_instruction load = {
|
|
|
|
.type = BI_LOAD_UNIFORM,
|
2020-04-24 22:20:28 +01:00
|
|
|
.vector_channels = nr_components,
|
2020-03-20 15:38:21 +00:00
|
|
|
.src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
|
2020-04-15 01:09:00 +01:00
|
|
|
.src_types = { nir_type_uint32, nir_type_uint32 },
|
2020-03-10 20:20:18 +00:00
|
|
|
.constant = { (uniform * 16) + offset },
|
|
|
|
.dest = bir_dest_index(&nir_dest),
|
|
|
|
.dest_type = nir_type_uint32, /* TODO */
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, load);
|
|
|
|
}
|
|
|
|
|
2020-03-05 22:50:18 +00:00
|
|
|
static void
|
|
|
|
emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
|
|
|
|
{
|
|
|
|
|
|
|
|
switch (instr->intrinsic) {
|
|
|
|
case nir_intrinsic_load_barycentric_pixel:
|
|
|
|
/* stub */
|
|
|
|
break;
|
|
|
|
case nir_intrinsic_load_interpolated_input:
|
2020-03-06 14:33:52 +00:00
|
|
|
case nir_intrinsic_load_input:
|
|
|
|
if (ctx->stage == MESA_SHADER_FRAGMENT)
|
|
|
|
bi_emit_ld_vary(ctx, instr);
|
|
|
|
else if (ctx->stage == MESA_SHADER_VERTEX)
|
2020-03-21 19:25:54 +00:00
|
|
|
bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
|
2020-03-06 14:33:52 +00:00
|
|
|
else {
|
|
|
|
unreachable("Unsupported shader stage");
|
|
|
|
}
|
2020-03-05 22:50:18 +00:00
|
|
|
break;
|
2020-03-06 14:33:52 +00:00
|
|
|
|
2020-03-06 14:26:44 +00:00
|
|
|
case nir_intrinsic_store_output:
|
|
|
|
if (ctx->stage == MESA_SHADER_FRAGMENT)
|
|
|
|
bi_emit_frag_out(ctx, instr);
|
2020-03-06 14:44:19 +00:00
|
|
|
else if (ctx->stage == MESA_SHADER_VERTEX)
|
|
|
|
bi_emit_st_vary(ctx, instr);
|
|
|
|
else
|
|
|
|
unreachable("Unsupported shader stage");
|
2020-03-06 14:26:44 +00:00
|
|
|
break;
|
2020-03-06 14:52:09 +00:00
|
|
|
|
|
|
|
case nir_intrinsic_load_uniform:
|
|
|
|
bi_emit_ld_uniform(ctx, instr);
|
|
|
|
break;
|
|
|
|
|
2020-03-10 20:20:18 +00:00
|
|
|
case nir_intrinsic_load_ssbo_address:
|
|
|
|
bi_emit_sysval(ctx, &instr->instr, 1, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_intrinsic_get_buffer_size:
|
|
|
|
bi_emit_sysval(ctx, &instr->instr, 1, 8);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_intrinsic_load_viewport_scale:
|
|
|
|
case nir_intrinsic_load_viewport_offset:
|
|
|
|
case nir_intrinsic_load_num_work_groups:
|
|
|
|
case nir_intrinsic_load_sampler_lod_parameters_pan:
|
|
|
|
bi_emit_sysval(ctx, &instr->instr, 3, 0);
|
|
|
|
break;
|
|
|
|
|
2020-03-05 22:50:18 +00:00
|
|
|
default:
|
|
|
|
/* todo */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-06 21:29:35 +00:00
|
|
|
static void
|
|
|
|
emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
|
|
|
|
{
|
|
|
|
/* Make sure we've been lowered */
|
|
|
|
assert(instr->def.num_components == 1);
|
|
|
|
|
|
|
|
bi_instruction move = {
|
|
|
|
.type = BI_MOV,
|
|
|
|
.dest = bir_ssa_index(&instr->def),
|
|
|
|
.dest_type = instr->def.bit_size | nir_type_uint,
|
|
|
|
.src = {
|
|
|
|
BIR_INDEX_CONSTANT
|
|
|
|
},
|
2020-03-31 01:54:51 +01:00
|
|
|
.src_types = {
|
|
|
|
instr->def.bit_size | nir_type_uint,
|
|
|
|
},
|
2020-03-06 21:29:35 +00:00
|
|
|
.constant = {
|
|
|
|
.u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
bi_emit(ctx, move);
|
|
|
|
}
|
|
|
|
|
2020-03-21 21:37:47 +00:00
|
|
|
#define BI_CASE_CMP(op) \
|
|
|
|
case op##8: \
|
|
|
|
case op##16: \
|
|
|
|
case op##32: \
|
|
|
|
|
2020-03-10 00:19:51 +00:00
|
|
|
static enum bi_class
|
|
|
|
bi_class_for_nir_alu(nir_op op)
|
|
|
|
{
|
|
|
|
switch (op) {
|
2020-03-10 01:10:41 +00:00
|
|
|
case nir_op_iadd:
|
|
|
|
case nir_op_fadd:
|
2020-03-10 11:56:14 +00:00
|
|
|
case nir_op_fsub:
|
2020-03-10 01:10:41 +00:00
|
|
|
return BI_ADD;
|
2020-03-10 12:03:20 +00:00
|
|
|
case nir_op_isub:
|
|
|
|
return BI_ISUB;
|
2020-03-10 01:10:41 +00:00
|
|
|
|
2020-03-21 21:37:47 +00:00
|
|
|
BI_CASE_CMP(nir_op_flt)
|
|
|
|
BI_CASE_CMP(nir_op_fge)
|
|
|
|
BI_CASE_CMP(nir_op_feq)
|
|
|
|
BI_CASE_CMP(nir_op_fne)
|
|
|
|
BI_CASE_CMP(nir_op_ilt)
|
|
|
|
BI_CASE_CMP(nir_op_ige)
|
|
|
|
BI_CASE_CMP(nir_op_ieq)
|
|
|
|
BI_CASE_CMP(nir_op_ine)
|
2020-03-10 12:21:35 +00:00
|
|
|
return BI_CMP;
|
|
|
|
|
2020-03-21 21:37:47 +00:00
|
|
|
case nir_op_b8csel:
|
|
|
|
case nir_op_b16csel:
|
|
|
|
case nir_op_b32csel:
|
2020-03-10 12:32:56 +00:00
|
|
|
return BI_CSEL;
|
|
|
|
|
2020-03-10 01:10:41 +00:00
|
|
|
case nir_op_i2i8:
|
|
|
|
case nir_op_i2i16:
|
|
|
|
case nir_op_i2i32:
|
|
|
|
case nir_op_i2i64:
|
|
|
|
case nir_op_u2u8:
|
|
|
|
case nir_op_u2u16:
|
|
|
|
case nir_op_u2u32:
|
|
|
|
case nir_op_u2u64:
|
|
|
|
case nir_op_f2i16:
|
|
|
|
case nir_op_f2i32:
|
|
|
|
case nir_op_f2i64:
|
|
|
|
case nir_op_f2u16:
|
|
|
|
case nir_op_f2u32:
|
|
|
|
case nir_op_f2u64:
|
|
|
|
case nir_op_i2f16:
|
|
|
|
case nir_op_i2f32:
|
|
|
|
case nir_op_i2f64:
|
|
|
|
case nir_op_u2f16:
|
|
|
|
case nir_op_u2f32:
|
|
|
|
case nir_op_u2f64:
|
2020-03-27 18:40:04 +00:00
|
|
|
case nir_op_f2f16:
|
|
|
|
case nir_op_f2f32:
|
|
|
|
case nir_op_f2f64:
|
|
|
|
case nir_op_f2fmp:
|
2020-03-10 01:10:41 +00:00
|
|
|
return BI_CONVERT;
|
|
|
|
|
2020-03-22 21:31:23 +00:00
|
|
|
case nir_op_vec2:
|
|
|
|
case nir_op_vec3:
|
|
|
|
case nir_op_vec4:
|
|
|
|
return BI_COMBINE;
|
|
|
|
|
|
|
|
case nir_op_vec8:
|
|
|
|
case nir_op_vec16:
|
|
|
|
unreachable("should've been lowered");
|
|
|
|
|
2020-03-11 19:15:41 +00:00
|
|
|
case nir_op_ffma:
|
2020-03-10 01:10:41 +00:00
|
|
|
case nir_op_fmul:
|
|
|
|
return BI_FMA;
|
|
|
|
|
|
|
|
case nir_op_imin:
|
|
|
|
case nir_op_imax:
|
|
|
|
case nir_op_umin:
|
|
|
|
case nir_op_umax:
|
|
|
|
case nir_op_fmin:
|
|
|
|
case nir_op_fmax:
|
|
|
|
return BI_MINMAX;
|
|
|
|
|
2020-03-10 01:02:51 +00:00
|
|
|
case nir_op_fsat:
|
2020-03-10 11:52:24 +00:00
|
|
|
case nir_op_fneg:
|
|
|
|
case nir_op_fabs:
|
2020-03-19 20:58:48 +00:00
|
|
|
return BI_FMOV;
|
2020-03-10 01:10:41 +00:00
|
|
|
case nir_op_mov:
|
|
|
|
return BI_MOV;
|
|
|
|
|
2020-03-28 00:28:09 +00:00
|
|
|
case nir_op_fround_even:
|
|
|
|
case nir_op_fceil:
|
|
|
|
case nir_op_ffloor:
|
|
|
|
case nir_op_ftrunc:
|
|
|
|
return BI_ROUND;
|
|
|
|
|
2020-03-10 01:20:20 +00:00
|
|
|
case nir_op_frcp:
|
|
|
|
case nir_op_frsq:
|
|
|
|
return BI_SPECIAL;
|
|
|
|
|
2020-03-10 01:10:41 +00:00
|
|
|
default:
|
|
|
|
unreachable("Unknown ALU op");
|
2020-03-10 00:19:51 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-21 22:12:31 +00:00
|
|
|
/* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
|
|
|
|
* return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
|
|
|
|
* optimizations). Otherwise it will bail (when used for primary code
|
|
|
|
* generation). */
|
|
|
|
|
2020-03-10 12:21:35 +00:00
|
|
|
static enum bi_cond
|
2020-03-21 22:12:31 +00:00
|
|
|
bi_cond_for_nir(nir_op op, bool soft)
|
2020-03-10 12:21:35 +00:00
|
|
|
{
|
|
|
|
switch (op) {
|
2020-03-21 21:37:47 +00:00
|
|
|
BI_CASE_CMP(nir_op_flt)
|
|
|
|
BI_CASE_CMP(nir_op_ilt)
|
2020-03-10 12:21:35 +00:00
|
|
|
return BI_COND_LT;
|
2020-03-21 21:37:47 +00:00
|
|
|
|
|
|
|
BI_CASE_CMP(nir_op_fge)
|
|
|
|
BI_CASE_CMP(nir_op_ige)
|
2020-03-10 12:21:35 +00:00
|
|
|
return BI_COND_GE;
|
2020-03-21 21:37:47 +00:00
|
|
|
|
|
|
|
BI_CASE_CMP(nir_op_feq)
|
|
|
|
BI_CASE_CMP(nir_op_ieq)
|
2020-03-10 12:21:35 +00:00
|
|
|
return BI_COND_EQ;
|
2020-03-21 21:37:47 +00:00
|
|
|
|
|
|
|
BI_CASE_CMP(nir_op_fne)
|
|
|
|
BI_CASE_CMP(nir_op_ine)
|
2020-03-10 12:21:35 +00:00
|
|
|
return BI_COND_NE;
|
|
|
|
default:
|
2020-03-21 22:12:31 +00:00
|
|
|
if (soft)
|
|
|
|
return BI_COND_ALWAYS;
|
|
|
|
else
|
|
|
|
unreachable("Invalid compare");
|
2020-03-10 12:21:35 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-21 22:13:49 +00:00
|
|
|
static void
|
|
|
|
bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
|
2020-04-24 22:20:28 +01:00
|
|
|
unsigned *constants_left, unsigned *constant_shift, unsigned comps)
|
2020-03-21 22:13:49 +00:00
|
|
|
{
|
|
|
|
unsigned bits = nir_src_bit_size(instr->src[i].src);
|
|
|
|
unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
|
|
|
|
|
|
|
|
alu->src_types[to] = nir_op_infos[instr->op].input_types[i]
|
|
|
|
| bits;
|
|
|
|
|
|
|
|
/* Try to inline a constant */
|
|
|
|
if (nir_src_is_const(instr->src[i].src) && *constants_left && (dest_bits == bits)) {
|
2020-04-15 15:39:42 +01:00
|
|
|
uint64_t mask = (1ull << dest_bits) - 1;
|
|
|
|
uint64_t cons = nir_src_as_uint(instr->src[i].src);
|
|
|
|
|
|
|
|
/* Try to reuse a constant */
|
|
|
|
for (unsigned i = 0; i < (*constant_shift); i += dest_bits) {
|
|
|
|
if (((alu->constant.u64 >> i) & mask) == cons) {
|
|
|
|
alu->src[to] = BIR_INDEX_CONSTANT | i;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
2020-03-21 22:13:49 +00:00
|
|
|
|
2020-04-15 15:39:42 +01:00
|
|
|
alu->constant.u64 |= cons << *constant_shift;
|
2020-03-21 22:13:49 +00:00
|
|
|
alu->src[to] = BIR_INDEX_CONSTANT | (*constant_shift);
|
|
|
|
--(*constants_left);
|
2020-04-17 20:52:03 +01:00
|
|
|
(*constant_shift) += MAX2(dest_bits, 32); /* lo/hi */
|
2020-03-21 22:13:49 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
alu->src[to] = bir_src_index(&instr->src[i].src);
|
|
|
|
|
2020-04-24 22:20:28 +01:00
|
|
|
/* Copy swizzle for all vectored components, replicating last component
|
|
|
|
* to fill undersized */
|
|
|
|
|
|
|
|
unsigned vec = alu->type == BI_COMBINE ? 1 :
|
|
|
|
MAX2(1, 32 / dest_bits);
|
|
|
|
|
|
|
|
for (unsigned j = 0; j < vec; ++j)
|
|
|
|
alu->swizzle[to][j] = instr->src[i].swizzle[MIN2(j, comps - 1)];
|
2020-03-21 22:13:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bi_fuse_csel_cond(bi_instruction *csel, nir_alu_src cond,
|
2020-04-24 22:20:28 +01:00
|
|
|
unsigned *constants_left, unsigned *constant_shift, unsigned comps)
|
2020-03-21 22:13:49 +00:00
|
|
|
{
|
|
|
|
/* Bail for vector weirdness */
|
|
|
|
if (cond.swizzle[0] != 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!cond.src.is_ssa)
|
|
|
|
return;
|
|
|
|
|
|
|
|
nir_ssa_def *def = cond.src.ssa;
|
|
|
|
nir_instr *parent = def->parent_instr;
|
|
|
|
|
|
|
|
if (parent->type != nir_instr_type_alu)
|
|
|
|
return;
|
|
|
|
|
|
|
|
nir_alu_instr *alu = nir_instr_as_alu(parent);
|
|
|
|
|
|
|
|
/* Try to match a condition */
|
|
|
|
enum bi_cond bcond = bi_cond_for_nir(alu->op, true);
|
|
|
|
|
|
|
|
if (bcond == BI_COND_ALWAYS)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* We found one, let's fuse it in */
|
|
|
|
csel->csel_cond = bcond;
|
2020-04-24 22:20:28 +01:00
|
|
|
bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift, comps);
|
|
|
|
bi_copy_src(csel, alu, 1, 1, constants_left, constant_shift, comps);
|
2020-03-21 22:13:49 +00:00
|
|
|
}
|
|
|
|
|
2020-03-10 00:19:51 +00:00
|
|
|
static void
|
|
|
|
emit_alu(bi_context *ctx, nir_alu_instr *instr)
|
|
|
|
{
|
2020-04-14 23:52:21 +01:00
|
|
|
/* Try some special functions */
|
|
|
|
switch (instr->op) {
|
|
|
|
case nir_op_fexp2:
|
|
|
|
bi_emit_fexp2(ctx, instr);
|
|
|
|
return;
|
2020-04-15 00:50:24 +01:00
|
|
|
case nir_op_flog2:
|
|
|
|
bi_emit_flog2(ctx, instr);
|
|
|
|
return;
|
2020-04-14 23:52:21 +01:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Otherwise, assume it's something we can handle normally */
|
2020-03-10 00:19:51 +00:00
|
|
|
bi_instruction alu = {
|
|
|
|
.type = bi_class_for_nir_alu(instr->op),
|
|
|
|
.dest = bir_dest_index(&instr->dest.dest),
|
|
|
|
.dest_type = nir_op_infos[instr->op].output_type
|
|
|
|
| nir_dest_bit_size(instr->dest.dest),
|
|
|
|
};
|
|
|
|
|
2020-03-10 01:20:20 +00:00
|
|
|
/* TODO: Implement lowering of special functions for older Bifrost */
|
|
|
|
assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
|
|
|
|
|
2020-04-24 22:20:28 +01:00
|
|
|
unsigned comps = nir_dest_num_components(instr->dest.dest);
|
2020-03-22 21:31:23 +00:00
|
|
|
|
2020-04-24 22:20:28 +01:00
|
|
|
if (alu.type != BI_COMBINE)
|
|
|
|
assert(comps <= MAX2(1, 32 / comps));
|
2020-03-10 00:19:51 +00:00
|
|
|
|
2020-04-24 22:20:28 +01:00
|
|
|
if (!instr->dest.dest.is_ssa) {
|
|
|
|
for (unsigned i = 0; i < comps; ++i)
|
|
|
|
assert(instr->dest.write_mask);
|
2020-03-10 00:19:51 +00:00
|
|
|
}
|
|
|
|
|
2020-03-10 00:32:00 +00:00
|
|
|
/* We inline constants as we go. This tracks how many constants have
|
|
|
|
* been inlined, since we're limited to 64-bits of constants per
|
|
|
|
* instruction */
|
|
|
|
|
|
|
|
unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
|
|
|
|
unsigned constants_left = (64 / dest_bits);
|
|
|
|
unsigned constant_shift = 0;
|
|
|
|
|
2020-03-31 01:54:51 +01:00
|
|
|
if (alu.type == BI_COMBINE)
|
|
|
|
constants_left = 0;
|
|
|
|
|
2020-03-10 00:19:51 +00:00
|
|
|
/* Copy sources */
|
|
|
|
|
|
|
|
unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
|
|
|
|
assert(num_inputs <= ARRAY_SIZE(alu.src));
|
|
|
|
|
2020-04-06 00:22:01 +01:00
|
|
|
for (unsigned i = 0; i < num_inputs; ++i) {
|
|
|
|
unsigned f = 0;
|
|
|
|
|
|
|
|
if (i && alu.type == BI_CSEL)
|
|
|
|
f++;
|
|
|
|
|
2020-04-24 22:20:28 +01:00
|
|
|
bi_copy_src(&alu, instr, i, i + f, &constants_left, &constant_shift, comps);
|
2020-04-06 00:22:01 +01:00
|
|
|
}
|
2020-03-10 00:19:51 +00:00
|
|
|
|
|
|
|
/* Op-specific fixup */
|
|
|
|
switch (instr->op) {
|
|
|
|
case nir_op_fmul:
|
|
|
|
alu.src[2] = BIR_INDEX_ZERO; /* FMA */
|
2020-03-27 19:53:12 +00:00
|
|
|
alu.src_types[2] = alu.src_types[1];
|
2020-03-10 00:19:51 +00:00
|
|
|
break;
|
2020-03-10 01:02:51 +00:00
|
|
|
case nir_op_fsat:
|
2020-03-19 20:58:48 +00:00
|
|
|
alu.outmod = BIFROST_SAT; /* FMOV */
|
2020-03-10 01:02:51 +00:00
|
|
|
break;
|
2020-03-10 11:52:24 +00:00
|
|
|
case nir_op_fneg:
|
2020-03-19 20:58:48 +00:00
|
|
|
alu.src_neg[0] = true; /* FMOV */
|
2020-03-10 11:52:24 +00:00
|
|
|
break;
|
|
|
|
case nir_op_fabs:
|
2020-03-19 20:58:48 +00:00
|
|
|
alu.src_abs[0] = true; /* FMOV */
|
2020-03-10 11:52:24 +00:00
|
|
|
break;
|
2020-03-10 11:56:14 +00:00
|
|
|
case nir_op_fsub:
|
2020-03-19 20:58:48 +00:00
|
|
|
alu.src_neg[1] = true; /* FADD */
|
2020-03-10 11:56:14 +00:00
|
|
|
break;
|
2020-03-10 01:10:41 +00:00
|
|
|
case nir_op_fmax:
|
|
|
|
case nir_op_imax:
|
|
|
|
case nir_op_umax:
|
|
|
|
alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
|
|
|
|
break;
|
2020-03-10 01:20:20 +00:00
|
|
|
case nir_op_frcp:
|
|
|
|
alu.op.special = BI_SPECIAL_FRCP;
|
|
|
|
break;
|
|
|
|
case nir_op_frsq:
|
|
|
|
alu.op.special = BI_SPECIAL_FRSQ;
|
|
|
|
break;
|
2020-03-21 21:37:47 +00:00
|
|
|
BI_CASE_CMP(nir_op_flt)
|
|
|
|
BI_CASE_CMP(nir_op_ilt)
|
|
|
|
BI_CASE_CMP(nir_op_fge)
|
|
|
|
BI_CASE_CMP(nir_op_ige)
|
|
|
|
BI_CASE_CMP(nir_op_feq)
|
|
|
|
BI_CASE_CMP(nir_op_ieq)
|
|
|
|
BI_CASE_CMP(nir_op_fne)
|
|
|
|
BI_CASE_CMP(nir_op_ine)
|
2020-03-21 22:12:31 +00:00
|
|
|
alu.op.compare = bi_cond_for_nir(instr->op, false);
|
2020-03-10 12:21:35 +00:00
|
|
|
break;
|
2020-03-28 00:28:09 +00:00
|
|
|
case nir_op_fround_even:
|
|
|
|
alu.op.round = BI_ROUND_MODE;
|
|
|
|
alu.roundmode = BIFROST_RTE;
|
|
|
|
break;
|
|
|
|
case nir_op_fceil:
|
|
|
|
alu.op.round = BI_ROUND_MODE;
|
|
|
|
alu.roundmode = BIFROST_RTP;
|
|
|
|
break;
|
|
|
|
case nir_op_ffloor:
|
|
|
|
alu.op.round = BI_ROUND_MODE;
|
|
|
|
alu.roundmode = BIFROST_RTN;
|
|
|
|
break;
|
|
|
|
case nir_op_ftrunc:
|
|
|
|
alu.op.round = BI_ROUND_MODE;
|
|
|
|
alu.roundmode = BIFROST_RTZ;
|
|
|
|
break;
|
2020-03-10 00:19:51 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2020-03-21 22:13:49 +00:00
|
|
|
if (alu.type == BI_CSEL) {
|
2020-03-22 01:19:14 +00:00
|
|
|
/* Default to csel3 */
|
|
|
|
alu.csel_cond = BI_COND_NE;
|
2020-04-06 00:22:01 +01:00
|
|
|
alu.src[1] = BIR_INDEX_ZERO;
|
|
|
|
alu.src_types[1] = alu.src_types[0];
|
2020-03-22 01:19:14 +00:00
|
|
|
|
2020-03-21 22:13:49 +00:00
|
|
|
bi_fuse_csel_cond(&alu, instr->src[0],
|
2020-04-24 22:20:28 +01:00
|
|
|
&constants_left, &constant_shift, comps);
|
2020-03-21 22:13:49 +00:00
|
|
|
}
|
|
|
|
|
2020-03-10 00:19:51 +00:00
|
|
|
bi_emit(ctx, alu);
|
|
|
|
}
|
|
|
|
|
2020-04-21 17:15:29 +01:00
|
|
|
/* TEX_COMPACT instructions assume normal 2D f32 operation but are more
|
|
|
|
* space-efficient and with simpler RA/scheduling requirements*/
|
|
|
|
|
|
|
|
static void
|
|
|
|
emit_tex_compact(bi_context *ctx, nir_tex_instr *instr)
|
|
|
|
{
|
2020-04-22 00:35:01 +01:00
|
|
|
/* TODO: Pipe through indices */
|
|
|
|
assert(instr->texture_index == 0);
|
|
|
|
assert(instr->sampler_index == 0);
|
|
|
|
|
2020-04-21 18:00:44 +01:00
|
|
|
bi_instruction tex = {
|
|
|
|
.type = BI_TEX,
|
|
|
|
.op = { .texture = BI_TEX_COMPACT },
|
|
|
|
.dest = bir_dest_index(&instr->dest),
|
|
|
|
.dest_type = instr->dest_type,
|
|
|
|
.src_types = { nir_type_float32, nir_type_float32 },
|
2020-04-24 22:20:28 +01:00
|
|
|
.vector_channels = 4
|
2020-04-21 18:00:44 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < instr->num_srcs; ++i) {
|
|
|
|
int index = bir_src_index(&instr->src[i].src);
|
|
|
|
assert (instr->src[i].src_type == nir_tex_src_coord);
|
|
|
|
|
|
|
|
tex.src[0] = index;
|
|
|
|
tex.src[1] = index;
|
|
|
|
tex.swizzle[0][0] = 0;
|
|
|
|
tex.swizzle[1][0] = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
bi_emit(ctx, tex);
|
2020-04-21 17:15:29 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
emit_tex_full(bi_context *ctx, nir_tex_instr *instr)
|
|
|
|
{
|
|
|
|
unreachable("stub");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
emit_tex(bi_context *ctx, nir_tex_instr *instr)
|
|
|
|
{
|
|
|
|
nir_alu_type base = nir_alu_type_get_base_type(instr->dest_type);
|
|
|
|
unsigned sz = nir_dest_bit_size(instr->dest);
|
|
|
|
instr->dest_type = base | sz;
|
|
|
|
|
|
|
|
bool is_normal = instr->op == nir_texop_tex;
|
|
|
|
bool is_2d = instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
|
|
|
|
instr->sampler_dim == GLSL_SAMPLER_DIM_EXTERNAL;
|
|
|
|
bool is_f = base == nir_type_float && (sz == 16 || sz == 32);
|
|
|
|
|
|
|
|
bool is_compact = is_normal && is_2d && is_f && !instr->is_shadow;
|
|
|
|
|
|
|
|
if (is_compact)
|
|
|
|
emit_tex_compact(ctx, instr);
|
|
|
|
else
|
|
|
|
emit_tex_full(ctx, instr);
|
|
|
|
}
|
|
|
|
|
2020-03-05 22:10:46 +00:00
|
|
|
static void
|
|
|
|
emit_instr(bi_context *ctx, struct nir_instr *instr)
|
|
|
|
{
|
|
|
|
switch (instr->type) {
|
|
|
|
case nir_instr_type_load_const:
|
|
|
|
emit_load_const(ctx, nir_instr_as_load_const(instr));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_instr_type_intrinsic:
|
|
|
|
emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_instr_type_alu:
|
|
|
|
emit_alu(ctx, nir_instr_as_alu(instr));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_instr_type_tex:
|
|
|
|
emit_tex(ctx, nir_instr_as_tex(instr));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_instr_type_jump:
|
|
|
|
emit_jump(ctx, nir_instr_as_jump(instr));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_instr_type_ssa_undef:
|
|
|
|
/* Spurious */
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2020-04-21 17:15:29 +01:00
|
|
|
unreachable("Unhandled instruction type");
|
2020-03-05 22:10:46 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2020-03-05 15:25:19 +00:00
|
|
|
|
|
|
|
static bi_block *
|
|
|
|
create_empty_block(bi_context *ctx)
|
|
|
|
{
|
|
|
|
bi_block *blk = rzalloc(ctx, bi_block);
|
|
|
|
|
2020-03-11 18:35:38 +00:00
|
|
|
blk->base.predecessors = _mesa_set_create(blk,
|
2020-03-05 15:25:19 +00:00
|
|
|
_mesa_hash_pointer,
|
|
|
|
_mesa_key_pointer_equal);
|
|
|
|
|
2020-03-11 18:35:38 +00:00
|
|
|
blk->base.name = ctx->block_name_count++;
|
2020-03-05 15:25:19 +00:00
|
|
|
|
|
|
|
return blk;
|
|
|
|
}
|
|
|
|
|
2020-03-06 14:26:20 +00:00
|
|
|
static void
|
|
|
|
bi_schedule_barrier(bi_context *ctx)
|
|
|
|
{
|
|
|
|
bi_block *temp = ctx->after_block;
|
|
|
|
ctx->after_block = create_empty_block(ctx);
|
2020-03-11 18:35:38 +00:00
|
|
|
list_addtail(&ctx->after_block->base.link, &ctx->blocks);
|
|
|
|
list_inithead(&ctx->after_block->base.instructions);
|
|
|
|
pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
|
2020-03-06 14:26:20 +00:00
|
|
|
ctx->current_block = ctx->after_block;
|
|
|
|
ctx->after_block = temp;
|
|
|
|
}
|
|
|
|
|
2020-03-05 15:25:19 +00:00
|
|
|
static bi_block *
|
|
|
|
emit_block(bi_context *ctx, nir_block *block)
|
|
|
|
{
|
2020-03-05 21:45:16 +00:00
|
|
|
if (ctx->after_block) {
|
|
|
|
ctx->current_block = ctx->after_block;
|
|
|
|
ctx->after_block = NULL;
|
|
|
|
} else {
|
|
|
|
ctx->current_block = create_empty_block(ctx);
|
|
|
|
}
|
|
|
|
|
2020-03-11 18:35:38 +00:00
|
|
|
list_addtail(&ctx->current_block->base.link, &ctx->blocks);
|
|
|
|
list_inithead(&ctx->current_block->base.instructions);
|
2020-03-05 15:25:19 +00:00
|
|
|
|
|
|
|
nir_foreach_instr(instr, block) {
|
2020-03-05 22:10:46 +00:00
|
|
|
emit_instr(ctx, instr);
|
2020-03-05 15:25:19 +00:00
|
|
|
++ctx->instruction_count;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ctx->current_block;
|
|
|
|
}
|
|
|
|
|
2020-03-05 21:45:16 +00:00
|
|
|
/* Emits an unconditional branch to the end of the current block, returning a
|
|
|
|
* pointer so the user can fill in details */
|
|
|
|
|
|
|
|
static bi_instruction *
|
|
|
|
bi_emit_branch(bi_context *ctx)
|
|
|
|
{
|
|
|
|
bi_instruction branch = {
|
|
|
|
.type = BI_BRANCH,
|
|
|
|
.branch = {
|
|
|
|
.cond = BI_COND_ALWAYS
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
return bi_emit(ctx, branch);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Sets a condition for a branch by examing the NIR condition. If we're
|
|
|
|
* familiar with the condition, we unwrap it to fold it into the branch
|
|
|
|
* instruction. Otherwise, we consume the condition directly. We
|
|
|
|
* generally use 1-bit booleans which allows us to use small types for
|
|
|
|
* the conditions.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void
|
|
|
|
bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
|
|
|
|
{
|
|
|
|
/* TODO: Try to unwrap instead of always bailing */
|
|
|
|
branch->src[0] = bir_src_index(cond);
|
|
|
|
branch->src[1] = BIR_INDEX_ZERO;
|
|
|
|
branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
|
|
|
|
branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
emit_if(bi_context *ctx, nir_if *nif)
|
|
|
|
{
|
|
|
|
bi_block *before_block = ctx->current_block;
|
|
|
|
|
|
|
|
/* Speculatively emit the branch, but we can't fill it in until later */
|
|
|
|
bi_instruction *then_branch = bi_emit_branch(ctx);
|
|
|
|
bi_set_branch_cond(then_branch, &nif->condition, true);
|
|
|
|
|
|
|
|
/* Emit the two subblocks. */
|
|
|
|
bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
|
|
|
|
bi_block *end_then_block = ctx->current_block;
|
|
|
|
|
|
|
|
/* Emit a jump from the end of the then block to the end of the else */
|
|
|
|
bi_instruction *then_exit = bi_emit_branch(ctx);
|
|
|
|
|
|
|
|
/* Emit second block, and check if it's empty */
|
|
|
|
|
|
|
|
int count_in = ctx->instruction_count;
|
|
|
|
bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
|
|
|
|
bi_block *end_else_block = ctx->current_block;
|
|
|
|
ctx->after_block = create_empty_block(ctx);
|
|
|
|
|
|
|
|
/* Now that we have the subblocks emitted, fix up the branches */
|
|
|
|
|
|
|
|
assert(then_block);
|
|
|
|
assert(else_block);
|
|
|
|
|
|
|
|
if (ctx->instruction_count == count_in) {
|
|
|
|
/* The else block is empty, so don't emit an exit jump */
|
|
|
|
bi_remove_instruction(then_exit);
|
|
|
|
then_branch->branch.target = ctx->after_block;
|
|
|
|
} else {
|
|
|
|
then_branch->branch.target = else_block;
|
|
|
|
then_exit->branch.target = ctx->after_block;
|
2020-03-11 18:35:38 +00:00
|
|
|
pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
|
2020-03-05 21:45:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Wire up the successors */
|
|
|
|
|
2020-03-11 18:35:38 +00:00
|
|
|
pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
|
2020-03-05 21:45:16 +00:00
|
|
|
|
2020-03-11 18:35:38 +00:00
|
|
|
pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
|
|
|
|
pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
|
2020-03-05 21:45:16 +00:00
|
|
|
}
|
|
|
|
|
2020-03-05 22:03:53 +00:00
|
|
|
static void
|
|
|
|
emit_loop(bi_context *ctx, nir_loop *nloop)
|
|
|
|
{
|
|
|
|
/* Remember where we are */
|
|
|
|
bi_block *start_block = ctx->current_block;
|
|
|
|
|
|
|
|
bi_block *saved_break = ctx->break_block;
|
|
|
|
bi_block *saved_continue = ctx->continue_block;
|
|
|
|
|
|
|
|
ctx->continue_block = create_empty_block(ctx);
|
|
|
|
ctx->break_block = create_empty_block(ctx);
|
|
|
|
ctx->after_block = ctx->continue_block;
|
|
|
|
|
|
|
|
/* Emit the body itself */
|
|
|
|
emit_cf_list(ctx, &nloop->body);
|
|
|
|
|
|
|
|
/* Branch back to loop back */
|
|
|
|
bi_instruction *br_back = bi_emit_branch(ctx);
|
|
|
|
br_back->branch.target = ctx->continue_block;
|
2020-03-11 18:35:38 +00:00
|
|
|
pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
|
|
|
|
pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
|
2020-03-05 22:03:53 +00:00
|
|
|
|
|
|
|
ctx->after_block = ctx->break_block;
|
|
|
|
|
|
|
|
/* Pop off */
|
|
|
|
ctx->break_block = saved_break;
|
|
|
|
ctx->continue_block = saved_continue;
|
|
|
|
++ctx->loop_count;
|
|
|
|
}
|
|
|
|
|
2020-03-05 15:25:19 +00:00
|
|
|
static bi_block *
|
|
|
|
emit_cf_list(bi_context *ctx, struct exec_list *list)
|
|
|
|
{
|
|
|
|
bi_block *start_block = NULL;
|
|
|
|
|
|
|
|
foreach_list_typed(nir_cf_node, node, node, list) {
|
|
|
|
switch (node->type) {
|
|
|
|
case nir_cf_node_block: {
|
|
|
|
bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
|
|
|
|
|
|
|
|
if (!start_block)
|
|
|
|
start_block = block;
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case nir_cf_node_if:
|
|
|
|
emit_if(ctx, nir_cf_node_as_if(node));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case nir_cf_node_loop:
|
|
|
|
emit_loop(ctx, nir_cf_node_as_loop(node));
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
unreachable("Unknown control flow");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return start_block;
|
|
|
|
}
|
2020-03-03 00:47:11 +00:00
|
|
|
|
2020-03-05 15:11:39 +00:00
|
|
|
static int
|
|
|
|
glsl_type_size(const struct glsl_type *type, bool bindless)
|
|
|
|
{
|
|
|
|
return glsl_count_attribute_slots(type, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bi_optimize_nir(nir_shader *nir)
|
|
|
|
{
|
|
|
|
bool progress;
|
|
|
|
unsigned lower_flrp = 16 | 32 | 64;
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
|
|
|
|
NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
|
|
|
|
|
|
|
|
nir_lower_tex_options lower_tex_options = {
|
|
|
|
.lower_txs_lod = true,
|
|
|
|
.lower_txp = ~0,
|
|
|
|
.lower_tex_without_implicit_lod = true,
|
|
|
|
.lower_txd = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
|
2020-03-06 21:29:35 +00:00
|
|
|
NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
|
|
|
|
NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
|
2020-03-05 15:11:39 +00:00
|
|
|
|
|
|
|
do {
|
|
|
|
progress = false;
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_lower_var_copies);
|
|
|
|
NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_copy_prop);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_remove_phis);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_dce);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_dead_cf);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_cse);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_algebraic);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_constant_folding);
|
|
|
|
|
|
|
|
if (lower_flrp != 0) {
|
|
|
|
bool lower_flrp_progress = false;
|
|
|
|
NIR_PASS(lower_flrp_progress,
|
|
|
|
nir,
|
|
|
|
nir_lower_flrp,
|
|
|
|
lower_flrp,
|
|
|
|
false /* always_precise */,
|
|
|
|
nir->options->lower_ffma);
|
|
|
|
if (lower_flrp_progress) {
|
|
|
|
NIR_PASS(progress, nir,
|
|
|
|
nir_opt_constant_folding);
|
|
|
|
progress = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Nothing should rematerialize any flrps, so we only
|
|
|
|
* need to do this lowering once.
|
|
|
|
*/
|
|
|
|
lower_flrp = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_opt_undef);
|
|
|
|
NIR_PASS(progress, nir, nir_opt_loop_unroll,
|
|
|
|
nir_var_shader_in |
|
|
|
|
nir_var_shader_out |
|
|
|
|
nir_var_function_temp);
|
|
|
|
} while (progress);
|
|
|
|
|
|
|
|
NIR_PASS(progress, nir, nir_opt_algebraic_late);
|
2020-03-21 21:37:47 +00:00
|
|
|
NIR_PASS(progress, nir, nir_lower_bool_to_int32);
|
2020-03-10 12:20:59 +00:00
|
|
|
NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
|
2020-03-06 21:29:35 +00:00
|
|
|
NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
|
|
|
|
NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
|
2020-03-05 15:11:39 +00:00
|
|
|
|
|
|
|
/* Take us out of SSA */
|
|
|
|
NIR_PASS(progress, nir, nir_lower_locals_to_regs);
|
2020-03-09 23:56:35 +00:00
|
|
|
NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
|
2020-03-22 21:31:23 +00:00
|
|
|
NIR_PASS(progress, nir, nir_convert_from_ssa, true);
|
2020-03-19 21:21:49 +00:00
|
|
|
}
|
|
|
|
|
2020-03-03 00:47:11 +00:00
|
|
|
void
|
2020-03-10 20:09:44 +00:00
|
|
|
bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
|
2020-03-03 00:47:11 +00:00
|
|
|
{
|
|
|
|
bi_context *ctx = rzalloc(NULL, bi_context);
|
|
|
|
ctx->nir = nir;
|
2020-03-05 15:11:39 +00:00
|
|
|
ctx->stage = nir->info.stage;
|
2020-03-03 19:27:05 +00:00
|
|
|
ctx->quirks = bifrost_get_quirks(product_id);
|
2020-03-05 15:25:19 +00:00
|
|
|
list_inithead(&ctx->blocks);
|
2020-03-03 00:47:11 +00:00
|
|
|
|
2020-03-05 15:11:39 +00:00
|
|
|
/* Lower gl_Position pre-optimisation, but after lowering vars to ssa
|
|
|
|
* (so we don't accidentally duplicate the epilogue since mesa/st has
|
|
|
|
* messed with our I/O quite a bit already) */
|
|
|
|
|
|
|
|
NIR_PASS_V(nir, nir_lower_vars_to_ssa);
|
|
|
|
|
|
|
|
if (ctx->stage == MESA_SHADER_VERTEX) {
|
|
|
|
NIR_PASS_V(nir, nir_lower_viewport_transform);
|
|
|
|
NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
|
|
|
|
}
|
|
|
|
|
|
|
|
NIR_PASS_V(nir, nir_split_var_copies);
|
|
|
|
NIR_PASS_V(nir, nir_lower_global_vars_to_local);
|
|
|
|
NIR_PASS_V(nir, nir_lower_var_copies);
|
|
|
|
NIR_PASS_V(nir, nir_lower_vars_to_ssa);
|
|
|
|
NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
|
|
|
|
NIR_PASS_V(nir, nir_lower_ssbo);
|
|
|
|
|
|
|
|
bi_optimize_nir(nir);
|
2020-03-03 00:47:11 +00:00
|
|
|
nir_print_shader(nir, stdout);
|
|
|
|
|
2020-03-10 20:20:18 +00:00
|
|
|
panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
|
|
|
|
program->sysval_count = ctx->sysvals.sysval_count;
|
|
|
|
memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
|
2020-04-24 00:26:01 +01:00
|
|
|
ctx->blend_types = program->blend_types;
|
2020-03-10 20:20:18 +00:00
|
|
|
|
2020-03-05 15:25:19 +00:00
|
|
|
nir_foreach_function(func, nir) {
|
|
|
|
if (!func->impl)
|
|
|
|
continue;
|
|
|
|
|
2020-03-06 14:43:43 +00:00
|
|
|
ctx->impl = func->impl;
|
2020-03-05 15:25:19 +00:00
|
|
|
emit_cf_list(ctx, &func->impl->body);
|
|
|
|
break; /* TODO: Multi-function shaders */
|
|
|
|
}
|
|
|
|
|
2020-03-19 21:21:49 +00:00
|
|
|
bi_foreach_block(ctx, _block) {
|
|
|
|
bi_block *block = (bi_block *) _block;
|
2020-03-22 21:31:23 +00:00
|
|
|
bi_lower_combine(ctx, block);
|
2020-03-19 21:21:49 +00:00
|
|
|
}
|
|
|
|
|
2020-03-11 19:10:32 +00:00
|
|
|
bool progress = false;
|
|
|
|
|
|
|
|
do {
|
|
|
|
progress = false;
|
|
|
|
|
|
|
|
bi_foreach_block(ctx, _block) {
|
|
|
|
bi_block *block = (bi_block *) _block;
|
|
|
|
progress |= bi_opt_dead_code_eliminate(ctx, block);
|
|
|
|
}
|
|
|
|
} while(progress);
|
|
|
|
|
2020-03-07 00:25:00 +00:00
|
|
|
bi_print_shader(ctx, stdout);
|
|
|
|
bi_schedule(ctx);
|
2020-03-12 00:39:36 +00:00
|
|
|
bi_register_allocate(ctx);
|
2020-03-12 12:05:58 +00:00
|
|
|
bi_print_shader(ctx, stdout);
|
2020-03-12 18:16:22 +00:00
|
|
|
bi_pack(ctx, &program->compiled);
|
|
|
|
disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
|
2020-03-05 15:11:39 +00:00
|
|
|
|
2020-03-03 00:47:11 +00:00
|
|
|
ralloc_free(ctx);
|
|
|
|
}
|