mesa/src/freedreno/isa
Danylo Piliaiev 5d5b1fc472 freedreno/ir3: add a6xx global atomics and separate atomic opcodes
Separating atomic opcodes makes possible to express a6xx global
atomics which take iova in SRC1. They would be needed by
VK_KHR_buffer_device_address.
The change also makes easier to distiguish atomics in conditions.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8717>
2021-11-23 18:26:37 +00:00
..
encode.c freedreno/ir3: add a6xx global atomics and separate atomic opcodes 2021-11-23 18:26:37 +00:00
ir3-cat0.xml
ir3-cat1.xml freedreno/isa: Add immed reg accessors 2021-10-15 15:52:33 +00:00
ir3-cat2.xml ir3: Add support for (dis)assembling flat.b 2021-11-04 02:59:28 +00:00
ir3-cat3.xml freedreno/isa: Add immed reg accessors 2021-10-15 15:52:33 +00:00
ir3-cat4.xml freedreno/isa: Convert to srcs/dsts 2021-06-23 17:20:29 +00:00
ir3-cat5.xml freedreno: Fix the uniform/nonuniform handling for cat5 bindful modes. 2021-11-10 17:48:59 +00:00
ir3-cat6.xml freedreno/ir3: add a6xx global atomics and separate atomic opcodes 2021-11-23 18:26:37 +00:00
ir3-cat7.xml
ir3-common.xml freedreno/isa: Fix ldg/stg "halfness" 2021-10-19 16:04:42 +00:00
ir3-disasm.c freedreno/isa: decode: switch bitmask_t to BITSET_WORD's 2021-09-21 20:25:31 +00:00
ir3.xml freedreno/isa: Convert to srcs/dsts 2021-06-23 17:20:29 +00:00
isa.h freedreno/isa: decode: switch bitmask_t to BITSET_WORD's 2021-09-21 20:25:31 +00:00
meson.build freedreno/isa: move isaspec to a new home 2021-09-21 20:25:31 +00:00