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freedreno/isa: Fix ldg/stg "halfness" 

Whether the load dst or store src is a half reg is determined by the
type field, similar to cat5.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13426>
This commit is contained in:
Rob Clark 2021-10-18 16:15:26 -07:00 committed by Marge Bot
parent 834e8066c1
commit 22a203aa4c
3 changed files with 17 additions and 15 deletions
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10
src/freedreno/isa/ir3-cat5.xml
View File

@ -85,15 +85,7 @@ SOFTWARE.
<display>
{SY}{JP}{NAME}{3D}{A}{O}{P}{S} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SAMP}{TEX}
</display>
<derived name="DST_HALF" type="bool" display="h">
<expr>
({TYPE} == 0) /* f16 */ ||
({TYPE} == 2) /* u16 */ ||
({TYPE} == 4) /* s16 */ ||
({TYPE} == 6) /* u8 */ ||
({TYPE} == 7) /* s8 */
</expr>
</derived>
<derived name="DST_HALF" expr="#type-half" type="bool" display="h"/>
<field name="FULL" pos="0" type="bool"/>
<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
<field name="SRC1" low="1" high="8" type="#cat5-src1">

14
src/freedreno/isa/ir3-cat6.xml
View File

@ -32,6 +32,8 @@ SOFTWARE.
<field pos="59" name="JP" type="bool" display="(jp)"/>
<field pos="60" name="SY" type="bool" display="(sy)"/>
<pattern low="61" high="63">110</pattern> <!-- cat6 -->
<!-- is load dst / store src a half-reg? -->
<derived name="TYPE_HALF" expr="#type-half" type="bool" display="h"/>
<encode>
<map name="TYPE">src->cat6.type</map>
</encode>
@ -59,7 +61,7 @@ SOFTWARE.
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} {DST}, g[{SRC1}{OFF}], {SIZE}
{SY}{JP}{NAME}.{TYPE} {TYPE_HALF}{DST}, g[{SRC1}{OFF}], {SIZE}
</display>
<field low="1" high="13" name="OFF" type="offset"/>
@ -79,12 +81,12 @@ SOFTWARE.
<gen min="600"/>
<display>
{SY}{JP}{NAME}.{TYPE} {DST}, g[{SRC1}+({SRC2}{OFF})&lt;&lt;{SRC2_BYTE_SHIFT}], {SIZE}
{SY}{JP}{NAME}.{TYPE} {TYPE_HALF}{DST}, g[{SRC1}+({SRC2}{OFF})&lt;&lt;{SRC2_BYTE_SHIFT}], {SIZE}
</display>
<override>
<display>
{SY}{JP}{NAME}.{TYPE} {DST}, g[{SRC1}+{SRC2}&lt;&lt;{SRC2_BYTE_SHIFT}{OFF}&lt;&lt;2], {SIZE}
{SY}{JP}{NAME}.{TYPE} {TYPE_HALF}{DST}, g[{SRC1}+{SRC2}&lt;&lt;{SRC2_BYTE_SHIFT}{OFF}&lt;&lt;2], {SIZE}
</display>
<expr>{SRC2_ADD_DWORD_SHIFT} > 0</expr>
</override>
@ -129,7 +131,7 @@ SOFTWARE.
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} g[{SRC1}{OFF}], {SRC3}, {SIZE}
{SY}{JP}{NAME}.{TYPE} g[{SRC1}{OFF}], {TYPE_HALF}{SRC3}, {SIZE}
</display>
<derived name="OFF" width="13" type="offset">
@ -156,12 +158,12 @@ SOFTWARE.
<gen min="600"/>
<display>
{SY}{JP}{NAME}.{TYPE} g[{SRC1}+({SRC2}{OFF})&lt;&lt;{DST_BYTE_SHIFT}], {SRC3}, {SIZE}
{SY}{JP}{NAME}.{TYPE} g[{SRC1}+({SRC2}{OFF})&lt;&lt;{DST_BYTE_SHIFT}], {TYPE_HALF}{SRC3}, {SIZE}
</display>
<override>
<display>
{SY}{JP}{NAME}.{TYPE} g[{SRC1}+{SRC2}&lt;&lt;{DST_BYTE_SHIFT}{OFF}&lt;&lt;2], {SRC3}, {SIZE}
{SY}{JP}{NAME}.{TYPE} g[{SRC1}+{SRC2}&lt;&lt;{DST_BYTE_SHIFT}{OFF}&lt;&lt;2], {TYPE_HALF}{SRC3}, {SIZE}
</display>
<expr>{SRC2_ADD_DWORD_SHIFT} > 0</expr>
</override>

8
src/freedreno/isa/ir3-common.xml
View File

@ -308,6 +308,14 @@ SOFTWARE.
<value val="7" display="s8"/>
</enum>
<expr name="#type-half">
({TYPE} == 0) /* f16 */ ||
({TYPE} == 2) /* u16 */ ||
({TYPE} == 4) /* s16 */ ||
({TYPE} == 6) /* u8 */ ||
({TYPE} == 7) /* s8 */
</expr>
<enum name="#absneg">
<value val="0" display=""/>
<value val="1" display="(neg)"/>