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freedreno/isa: Convert to srcs/dsts 

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
This commit is contained in:
Connor Abbott 2021-06-18 16:11:52 +02:00 committed by Marge Bot
parent db7814ad56
commit bff83fc42b
9 changed files with 112 additions and 111 deletions
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17
src/freedreno/ir3/ir3.c
View File

@ -442,17 +442,18 @@ struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
new_instr->regs_count = 0;
new_instr->dsts_count = 0;
new_instr->srcs_count = 0;
for (i = 0; i < instr->regs_count; i++) {
struct ir3_register *reg = instr->regs[i];
struct ir3_register *new_reg;
if (reg->flags & IR3_REG_DEST)
new_reg = ir3_dst_create(new_instr, reg->num, reg->flags);
else
new_reg = ir3_src_create(new_instr, reg->num, reg->flags);
for (i = 0; i < instr->dsts_count; i++) {
struct ir3_register *reg = instr->dsts[i];
struct ir3_register *new_reg = ir3_dst_create(new_instr, reg->num, reg->flags);
*new_reg = *reg;
if ((new_reg->flags & IR3_REG_DEST) && new_reg->instr)
if (new_reg->instr)
new_reg->instr = new_instr;
}
for (i = 0; i < instr->srcs_count; i++) {
struct ir3_register *reg = instr->srcs[i];
struct ir3_register *new_reg = ir3_src_create(new_instr, reg->num, reg->flags);
*new_reg = *reg;
}
return new_instr;
}

20
src/freedreno/isa/encode.c
View File

@ -52,7 +52,7 @@ extract_SRC1_R(struct ir3_instruction *instr)
assert(!instr->repeat);
return instr->nop & 0x1;
}
return !!(instr->regs[1]->flags & IR3_REG_R);
return !!(instr->srcs[0]->flags & IR3_REG_R);
}
static inline bool
@ -63,8 +63,8 @@ extract_SRC2_R(struct ir3_instruction *instr)
return (instr->nop >> 1) & 0x1;
}
/* src2 does not appear in all cat2, but SRC2_R does (for nop encoding) */
if (instr->regs_count > 2)
return !!(instr->regs[2]->flags & IR3_REG_R);
if (instr->srcs_count > 1)
return !!(instr->srcs[1]->flags & IR3_REG_R);
return 0;
}
@ -97,7 +97,7 @@ __instruction_case(struct encode_state *s, struct ir3_instruction *instr)
return OPC_BRAX;
}
} else if (instr->opc == OPC_MOV) {
struct ir3_register *src = instr->regs[1];
struct ir3_register *src = instr->srcs[0];
if (src->flags & IR3_REG_IMMED) {
return OPC_MOV_IMMED;
} if (src->flags & IR3_REG_RELATIV) {
@ -157,15 +157,15 @@ extract_cat5_SRC(struct ir3_instruction *instr, unsigned n)
if (instr->flags & IR3_INSTR_S2EN) {
n++;
}
if (n < instr->regs_count)
return instr->regs[n];
if (n < instr->srcs_count)
return instr->srcs[n];
return NULL;
}
static inline bool
extract_cat5_FULL(struct ir3_instruction *instr)
{
struct ir3_register *reg = extract_cat5_SRC(instr, 1);
struct ir3_register *reg = extract_cat5_SRC(instr, 0);
/* some cat5 have zero src regs, in which case 'FULL' is false */
if (!reg)
return false;
@ -207,7 +207,7 @@ extract_cat5_DESC_MODE(struct ir3_instruction *instr)
static inline unsigned
extract_cat6_DESC_MODE(struct ir3_instruction *instr)
{
struct ir3_register *ssbo = instr->regs[1];
struct ir3_register *ssbo = instr->srcs[0];
if (ssbo->flags & IR3_REG_IMMED) {
return 0; // todo enum
} else if (instr->flags & IR3_INSTR_NONUNIF) {
@ -230,8 +230,8 @@ extract_cat6_SRC(struct ir3_instruction *instr, unsigned n)
if (instr->flags & IR3_INSTR_G) {
n++;
}
assert(n < instr->regs_count);
return instr->regs[n];
assert(n < instr->srcs_count);
return instr->srcs[n];
}
typedef enum {

32
src/freedreno/isa/ir3-cat1.xml
View File

@ -76,10 +76,10 @@ SOFTWARE.
<field name="SY" pos="60" type="bool" display="(sy)"/>
<pattern low="61" high="63">001</pattern> <!-- cat1 -->
<encode>
<map name="SRC">src->regs[1]</map>
<map name="SRC_R">!!(src->regs[1]->flags &amp; IR3_REG_R)</map>
<map name="SRC">src->srcs[0]</map>
<map name="SRC_R">!!(src->srcs[0]->flags &amp; IR3_REG_R)</map>
<map name="UL">!!(src->flags &amp; IR3_INSTR_UL)</map>
<map name="DST_REL">!!(src->regs[0]->flags &amp; IR3_REG_RELATIV)</map>
<map name="DST_REL">!!(src->dsts[0]->flags &amp; IR3_REG_RELATIV)</map>
<map name="ROUND">src->cat1.round</map>
</encode>
</bitset>
@ -354,7 +354,7 @@ SOFTWARE.
<pattern low="57" high="58">10</pattern> <!-- OPC -->
<encode>
<map name="DST0">src->regs[0]</map>
<map name="DST0">src->dsts[0]</map>
</encode>
</bitset>
@ -377,9 +377,9 @@ SOFTWARE.
<pattern low="40" high="41">00</pattern> <!-- SUB_OPC -->
<encode>
<map name="SRC0">src->regs[2]</map>
<map name="SRC1">src->regs[3]</map>
<map name="DST1">src->regs[1]</map>
<map name="SRC0">src->srcs[0]</map>
<map name="SRC1">src->srcs[1]</map>
<map name="DST1">src->dsts[1]</map>
</encode>
</bitset>
@ -402,10 +402,10 @@ SOFTWARE.
<pattern low="40" high="41">01</pattern> <!-- SUB_OPC -->
<encode>
<map name="SRC0">src->regs[1]</map>
<map name="SRC1">src->regs[2]</map>
<map name="SRC2">src->regs[3]</map>
<map name="SRC3">src->regs[4]</map>
<map name="SRC0">src->srcs[0]</map>
<map name="SRC1">src->srcs[1]</map>
<map name="SRC2">src->srcs[2]</map>
<map name="SRC3">src->srcs[3]</map>
</encode>
</bitset>
@ -428,10 +428,10 @@ SOFTWARE.
<pattern low="40" high="41">10</pattern> <!-- SUB_OPC -->
<encode>
<map name="SRC0">src->regs[4]</map>
<map name="DST1">src->regs[1]</map>
<map name="DST2">src->regs[2]</map>
<map name="DST3">src->regs[3]</map>
<map name="SRC0">src->srcs[0]</map>
<map name="DST1">src->dsts[1]</map>
<map name="DST2">src->dsts[2]</map>
<map name="DST3">src->dsts[3]</map>
</encode>
</bitset>
@ -463,7 +463,7 @@ SOFTWARE.
the existing stuff:
-->
<encode>
<map name="REPEAT">util_last_bit(src->regs[0]->wrmask) - 1</map>
<map name="REPEAT">util_last_bit(src->dsts[0]->wrmask) - 1</map>
</encode>
</bitset>

8
src/freedreno/isa/ir3-cat2.xml
View File

@ -60,11 +60,11 @@ SOFTWARE.
<encode>
<map name="SAT">!!(src->flags &amp; IR3_INSTR_SAT)</map>
<map name="DST_CONV">
((src->regs[0]->num >> 2) == 62) ? 0 :
!!((src->regs[1]->flags ^ src->regs[0]->flags) &amp; IR3_REG_HALF)
((src->dsts[0]->num >> 2) == 62) ? 0 :
!!((src->srcs[0]->flags ^ src->dsts[0]->flags) &amp; IR3_REG_HALF)
</map>
<map name="EI">!!(src->regs[0]->flags &amp; IR3_REG_EI)</map>
<map name="FULL">!(src->regs[1]->flags &amp; IR3_REG_HALF)</map>
<map name="EI">!!(src->dsts[0]->flags &amp; IR3_REG_EI)</map>
<map name="FULL">!(src->srcs[0]->flags &amp; IR3_REG_HALF)</map>
<map name="SRC1_R">extract_SRC1_R(src)</map>
<map name="SRC2_R">extract_SRC2_R(src)</map>
</encode>

14
src/freedreno/isa/ir3-cat3.xml
View File

@ -132,16 +132,16 @@ SOFTWARE.
<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
<derived name="DST_HALF" expr="#dest-half" type="bool" display="h"/>
<encode>
<map name="SRC1_NEG">!!(src->regs[1]->flags &amp; (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map>
<map name="SRC1_NEG">!!(src->srcs[0]->flags &amp; (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map>
<map name="SRC1_R">extract_SRC1_R(src)</map>
<map name="SRC2_R">extract_SRC2_R(src)</map>
<map name="SRC3_R">!!(src->regs[3]->flags &amp; IR3_REG_R)</map>
<map name="SRC2_NEG">!!(src->regs[2]->flags &amp; (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map>
<map name="SRC3_NEG">!!(src->regs[3]->flags &amp; (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map>
<map name="SRC1">src->regs[1]</map>
<map name="SRC3_R">!!(src->srcs[2]->flags &amp; IR3_REG_R)</map>
<map name="SRC2_NEG">!!(src->srcs[1]->flags &amp; (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map>
<map name="SRC3_NEG">!!(src->srcs[2]->flags &amp; (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map>
<map name="SRC1">src->srcs[0]</map>
<map name="DST_CONV">
((src->regs[0]->num >> 2) == 62) ? 0 :
!!((src->regs[1]->flags ^ src->regs[0]->flags) &amp; IR3_REG_HALF)
((src->dsts[0]->num >> 2) == 62) ? 0 :
!!((src->srcs[0]->flags ^ src->dsts[0]->flags) &amp; IR3_REG_HALF)
</map>
</encode>
</bitset>

10
src/freedreno/isa/ir3-cat4.xml
View File

@ -60,13 +60,13 @@ SOFTWARE.
<field name="SY" pos="60" type="bool" display="(sy)"/>
<pattern low="61" high="63">100</pattern> <!-- cat4 -->
<encode>
<map name="SRC">src->regs[1]</map>
<map name="SRC">src->srcs[0]</map>
<map name="DST_CONV">
((src->regs[0]->num >> 2) == 62) ? 0 :
!!((src->regs[1]->flags ^ src->regs[0]->flags) &amp; IR3_REG_HALF)
((src->dsts[0]->num >> 2) == 62) ? 0 :
!!((src->srcs[0]->flags ^ src->dsts[0]->flags) &amp; IR3_REG_HALF)
</map>
<map name="FULL">!(src->regs[1]->flags &amp; IR3_REG_HALF)</map>
<map name="SRC_R">!!(src->regs[1]->flags &amp; IR3_REG_R)</map>
<map name="FULL">!(src->srcs[0]->flags &amp; IR3_REG_HALF)</map>
<map name="SRC_R">!!(src->srcs[0]->flags &amp; IR3_REG_R)</map>
</encode>
</bitset>

10
src/freedreno/isa/ir3-cat5.xml
View File

@ -141,7 +141,7 @@ SOFTWARE.
<map name="FULL">extract_cat5_FULL(src)</map>
<map name="TEX">src</map>
<map name="SAMP">src</map>
<map name="WRMASK">src->regs[0]->wrmask</map>
<map name="WRMASK">src->dsts[0]->wrmask</map>
<map name="BASE">src</map>
<map name="TYPE">src</map>
<map name="BASE_HI">src->cat5.tex_base >> 1</map>
@ -153,12 +153,12 @@ SOFTWARE.
<map name="P">!!(src->flags &amp; IR3_INSTR_P)</map>
<map name="DESC_MODE">extract_cat5_DESC_MODE(src)</map>
<!--
TODO the src order is currently a bit messy due to ir3 using regs[1]
TODO the src order is currently a bit messy due to ir3 using srcs[0]
for s2en src in the s2en case
-->
<map name="SRC1">extract_cat5_SRC(src, 1)</map>
<map name="SRC2">extract_cat5_SRC(src, 2)</map>
<map name="SRC3">(src->regs_count > 1) ? src->regs[1] : NULL</map>
<map name="SRC1">extract_cat5_SRC(src, 0)</map>
<map name="SRC2">extract_cat5_SRC(src, 1)</map>
<map name="SRC3">(src->srcs_count > 0) ? src->srcs[0] : NULL</map>
</encode>
</bitset>

104
src/freedreno/isa/ir3-cat6.xml
View File

@ -70,10 +70,10 @@ SOFTWARE.
<pattern low="52" high="53">00</pattern>
<pattern low="54" high="58">00000</pattern> <!-- OPC -->
<encode>
<map name="SRC2_REG">!(src->regs[2]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">src->regs[2]</map>
<map name="OFF">src->regs[2]->iim_val</map>
<map name="SIZE">src->regs[3]->uim_val</map>
<map name="SRC2_REG">!(src->srcs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">src->srcs[1]</map>
<map name="OFF">src->srcs[1]->iim_val</map>
<map name="SIZE">src->srcs[2]->uim_val</map>
</encode>
</bitset>
@ -110,11 +110,11 @@ SOFTWARE.
<pattern pos="53" >x</pattern>
<pattern low="54" high="58">00011</pattern> <!-- OPC -->
<encode>
<map name="SIZE">src->regs[3]->uim_val</map>
<map name="SRC2">src->regs[4]</map>
<map name="SIZE">src->srcs[2]->uim_val</map>
<map name="SRC2">src->srcs[3]</map>
<map name="DST_OFF" force="true">1</map>
<map name="SRC3">src->regs[2]</map>
<map name="G">(src->flags &amp; IR3_INSTR_G) &amp;&amp; !(src->regs[4]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC3">src->srcs[1]</map>
<map name="G">(src->flags &amp; IR3_INSTR_G) &amp;&amp; !(src->srcs[3]->flags &amp; IR3_REG_IMMED)</map>
<map name="OFF_LO">src->cat6.dst_offset</map>
<map name="OFF_HI">src->cat6.dst_offset >> 8</map>
</encode>
@ -132,9 +132,9 @@ SOFTWARE.
<pattern low="40" high="48">xxxxxxxxx</pattern>
<pattern low="52" high="53">xx</pattern>
<encode>
<map name="OFF">src->regs[2]->uim_val</map>
<map name="SRC">src->regs[1]</map>
<map name="SIZE">src->regs[3]->uim_val</map>
<map name="OFF">src->srcs[1]->uim_val</map>
<map name="SRC">src->srcs[0]</map>
<map name="SIZE">src->srcs[2]->uim_val</map>
</encode>
</bitset>
@ -185,8 +185,8 @@ SOFTWARE.
<pattern low="52" high="53">xx</pattern>
<pattern low="54" high="58">11111</pattern> <!-- OPC -->
<encode>
<map name="SIZE">src->regs[2]->uim_val</map>
<map name="OFF">src->regs[1]->uim_val</map>
<map name="SIZE">src->srcs[1]->uim_val</map>
<map name="OFF">src->srcs[0]->uim_val</map>
</encode>
</bitset>
@ -212,9 +212,9 @@ SOFTWARE.
-->
<map name="OFF_HI">src->cat6.dst_offset >> 8</map>
<map name="OFF_LO">src->cat6.dst_offset &amp; 0xff</map>
<map name="SRC">src->regs[2]</map>
<map name="DST">src->regs[1]</map>"
<map name="SIZE">src->regs[3]->uim_val</map>
<map name="SRC">src->srcs[1]</map>
<map name="DST">src->srcs[0]</map>"
<map name="SIZE">src->srcs[2]->uim_val</map>
</encode>
</bitset>
@ -279,8 +279,8 @@ SOFTWARE.
<pattern low="52" high="53">xx</pattern>
<pattern low="54" high="58">11100</pattern> <!-- OPC -->
<encode>
<map name="DST">src->regs[1]->uim_val</map>
<map name="SRC">src->regs[2]</map>
<map name="DST">src->srcs[0]->uim_val</map>
<map name="SRC">src->srcs[1]</map>
</encode>
</bitset>
@ -309,8 +309,8 @@ SOFTWARE.
<pattern low="54" high="58">01111</pattern> <!-- OPC -->
<encode>
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="SSBO">src->regs[1]</map>
<map name="SSBO_IM">!!(src->regs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="SSBO">src->srcs[0]</map>
<map name="SSBO_IM">!!(src->srcs[0]->flags &amp; IR3_REG_IMMED)</map>
</encode>
</bitset>
@ -349,12 +349,12 @@ SOFTWARE.
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="TYPED">src</map>
<map name="TYPE_SIZE_MINUS_ONE">src->cat6.iim_val - 1</map>
<map name="SSBO">src->regs[1]</map>
<map name="SSBO_IM">!!(src->regs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC1">src->regs[2]</map>
<map name="SRC1_IM">!!(src->regs[2]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">src->regs[3]</map>
<map name="SRC2_IM">!!(src->regs[3]->flags &amp; IR3_REG_IMMED)</map>
<map name="SSBO">src->srcs[0]</map>
<map name="SSBO_IM">!!(src->srcs[0]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC1">src->srcs[1]</map>
<map name="SRC1_IM">!!(src->srcs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">src->srcs[2]</map>
<map name="SRC2_IM">!!(src->srcs[2]->flags &amp; IR3_REG_IMMED)</map>
</encode>
</bitset>
@ -390,14 +390,14 @@ SOFTWARE.
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="TYPED">src</map>
<map name="TYPE_SIZE_MINUS_ONE">src->cat6.iim_val - 1</map>
<map name="SSBO">src->regs[1]</map>
<map name="SSBO_IM">!!(src->regs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC1">src->regs[2]</map>
<map name="SRC1_IM">!!(src->regs[2]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">src->regs[3]</map>
<map name="SRC2_IM">!!(src->regs[3]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC3">src->regs[4]</map>
<map name="SRC3_IM">!!(src->regs[4]->flags &amp; IR3_REG_IMMED)</map>
<map name="SSBO">src->srcs[0]</map>
<map name="SSBO_IM">!!(src->srcs[0]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC1">src->srcs[1]</map>
<map name="SRC1_IM">!!(src->srcs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">src->srcs[2]</map>
<map name="SRC2_IM">!!(src->srcs[2]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC3">src->srcs[3]</map>
<map name="SRC3_IM">!!(src->srcs[3]->flags &amp; IR3_REG_IMMED)</map>
</encode>
</bitset>
@ -459,14 +459,14 @@ SOFTWARE.
<map name="TYPED">src</map>
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="TYPE_SIZE_MINUS_ONE">src->cat6.iim_val - 1</map>
<map name="SSBO">src->regs[1]</map>
<map name="SSBO_IM">!!(src->regs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC1">extract_cat6_SRC(src, 1)</map>
<map name="SRC1_IM">!!(extract_cat6_SRC(src, 1)->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">extract_cat6_SRC(src, 2)</map>
<map name="SRC2_IM">!!(extract_cat6_SRC(src, 2)->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC3">extract_cat6_SRC(src, 3)</map>
<map name="SRC3_IM">!!(extract_cat6_SRC(src, 3)->flags &amp; IR3_REG_IMMED)</map>
<map name="SSBO">src->srcs[0]</map>
<map name="SSBO_IM">!!(src->srcs[0]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC1">extract_cat6_SRC(src, 0)</map>
<map name="SRC1_IM">!!(extract_cat6_SRC(src, 0)->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">extract_cat6_SRC(src, 1)</map>
<map name="SRC2_IM">!!(extract_cat6_SRC(src, 1)->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC3">extract_cat6_SRC(src, 2)</map>
<map name="SRC3_IM">!!(extract_cat6_SRC(src, 2)->flags &amp; IR3_REG_IMMED)</map>
</encode>
</bitset>
@ -591,10 +591,10 @@ SOFTWARE.
<pattern pos="53" >1</pattern>
<encode>
<map name="K">0</map> <!-- TODO.. once we figure out what this is -->
<map name="SRC1_IM">!!(src->regs[2]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC1_IM">!!(src->srcs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="OFFSET">src->cat6.d</map>
<map name="SRC1">src->regs[2]</map>
<map name="SRC2">src->regs[1]</map>
<map name="SRC1">src->srcs[1]</map>
<map name="SRC2">src->srcs[0]</map>
</encode>
</bitset>
@ -664,8 +664,8 @@ SOFTWARE.
<encode>
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="TYPED">src</map>
<map name="SSBO">src->regs[1]</map>
<map name="SRC1">src->regs[2]</map>
<map name="SSBO">src->srcs[0]</map>
<map name="SRC1">src->srcs[1]</map>
</encode>
</bitset>
@ -693,9 +693,9 @@ SOFTWARE.
<encode>
<map name="TYPED">src</map>
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="SSBO">src->regs[1]</map>
<map name="SRC1">src->regs[3]</map>
<map name="SRC2">src->regs[2]</map>
<map name="SSBO">src->srcs[0]</map>
<map name="SRC1">src->srcs[2]</map>
<map name="SRC2">src->srcs[1]</map>
</encode>
</bitset>
@ -716,7 +716,7 @@ SOFTWARE.
<pattern low="14" high="19">000110</pattern> <!-- OPC -->
<pattern low="52" high="53">10</pattern>
<encode>
<map name="SRC1">src->regs[0]</map>
<map name="SRC1">src->dsts[0]</map>
</encode>
</bitset>
@ -869,4 +869,4 @@ SOFTWARE.
</value>
</enum>
</isa>
</isa>

8
src/freedreno/isa/ir3.xml
View File

@ -64,10 +64,10 @@ TODO:
that are specific to a single instruction category,
mappings should be defined at that level instead.
-->
<map name="DST">src->regs[0]</map>
<map name="SRC1">src->regs[1]</map>
<map name="SRC2">src->regs[2]</map>
<map name="SRC3">src->regs[3]</map>
<map name="DST">src->dsts[0]</map>
<map name="SRC1">src->srcs[0]</map>
<map name="SRC2">src->srcs[1]</map>
<map name="SRC3">src->srcs[2]</map>
<map name="REPEAT">src->repeat</map>
<map name="SS">!!(src->flags &amp; IR3_INSTR_SS)</map>
<map name="JP">!!(src->flags &amp; IR3_INSTR_JP)</map>