Commit Graph

76301 Commits

Author SHA1 Message Date
Topi Pohjolainen f709a08457 i965: Add means for limiting color resolves
Until now there has been only one type of color buffer that needs
to resolved - namely single sampled fast clear. As even the
sampler engine in GPU doesn't understand the associated meta data,
the color values need to be always resolved prior to reading them.

From SKL onwards there is new scheme supported called the lossless
compression of single sampled color buffers. This is something that
is understood by the sampling engine and therefore resolving of
these types of buffers is not necessary before sampling.
This patch adds means to make the distinction when considering if
resolve is needed.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2016-02-13 09:50:24 +02:00
Topi Pohjolainen 7513c5c782 i965: Refactor resolving of auxiliary mode
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2016-02-13 09:30:36 +02:00
Topi Pohjolainen 9002bcdb35 i965: Don't try to create aux buffer for non-msrt aux-buffer
In addition to simply calling miptree_create() the higher level
call intel_miptree_create() also considers if the buffer should
be associated with an auxiliary buffer based on the given format.

Here we are allocating an auxiliary buffer which in turn has such
format that would mislead intel_miptree_create_layout() later on
to try to associate the auxiliary buffer with an auxiliary buffer.
To prevent this the actual buffer creation logic was split out
into its own function. Lets invoke that instead.

v2 (Ben): Do not signal msaa layout with explicit argument but
          using layout_flags instead.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2016-02-13 09:28:41 +02:00
Ben Widawsky 5743fd9571 i965: Rename optimizer debug 00 filename
This allows ls, and scripts to get the file names in the correct order of
optimization.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-02-12 20:52:28 -08:00
Kenneth Graunke c8b0020f2f i965: Make brw_clear_cache NULL out stale program pointers.
The L3 partitioning code tries to look at all programs - both render
programs (VS/TCS/TES/GS/FS) and compute (CS).

After calling brw_clear_cache, all prog_data pointers are invalid and
point to freed data.  The intention was that flagging the dirty bits for
all programs would cause the next draw call to re-run the atoms for each
program stage, uploading new programs and installing new, valid pointers.

However, this doesn't quite work in our new multi-pipeline world.  When
drawing or dispatching a compute workload, we only consider the programs
for the appropriate pipeline: drawing sets up VS/TCS/TES/GS/FS, but not
CS, and vice versa.  This leaves pointers dangling a bit longer than
intended.

The L3 configuration code tries to inspect the prog_data for all shader
stages, so that we avoid having to reconfigure it when swapping back and
forth between render and compute workloads.  So we can't have dangling
pointers.

The fix is simple: have brw_clear_cache NULL out stale prog_data
pointers, making it safe to inspect.  The next L3 configuration pass
will see either the render shaders or compute shader as missing for
one go around, but will pick them up when both pipelines have run.

In other words, we'll simply reconfigure L3 twice, which is safe,
if a tiny bit wasteful - but then again, we just threw every compiled
shader we had on the floor and started recompiling the from scratch,
which is massively more wasteful, so it's not much of a concern.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jordan Justen <jljusten@gmail.com>
2016-02-12 20:35:34 -08:00
Ilia Mirkin f56b5de877 mesa: avoid segfault in GetProgramPipelineInfoLog when no length
If there is no pipe info log, we would unconditionally deref length,
which was only optionally there. _mesa_copy_string handles the source
being null, as well as the length, so may as well just always call it.

Fixes a segfault in

dEQP-GLES31.functional.state_query.program_pipeline.info_log

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-12 18:22:50 -05:00
Ilia Mirkin f82ff6207c mesa: reset offset/size to 0 when removing atomic binding
Similar to commit dd9d2963d6 (mesa: AtomicBufferBindings should be
initialized to zero.), we should reset these to zero when unbinding.
This fixes a number of dEQP failures due to cross-test pollution. The
tests properly unbound everything, but when querying the values again,
the expectation was that they would be 0.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-02-12 18:22:49 -05:00
Ilia Mirkin b7e246d89a mesa: recognize enums GL_COLOR_ATTACHMENT8-31 as valid
Similar as for AUX1-3, these enums aren't invalid (i.e. -1) but also not
supported by mesa. Returning BUFFER_COUNT causes the proper error to be
returned by ReadBuffer and other functions. This resolves some failures
in

dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.read_buffer

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-12 18:22:49 -05:00
Ilia Mirkin a663aa2a37 mesa/clear: update ClearBufferfv error handling for GL 4.5 spec
This fixes

dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.clear_bufferfv

and brings the logic up to spec with GL 4.5

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-12 18:22:49 -05:00
Ilia Mirkin 3a0051bea9 mesa/clear: update ClearBufferuiv error handling for GL 4.5 spec
This fixes

dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.clear_bufferuiv

and brings the logic up to spec with GL 4.5

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-12 18:22:49 -05:00
Ilia Mirkin 758162923b mesa/clear: simplify ClearBufferiv error handling
Might as well handle everything in the same error call.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-12 18:22:49 -05:00
Ilia Mirkin 86fd9d6b8e mesa/clear: remove dead code handling ClearBufferiv(GL_DEPTH)
There's a hunk above which sets INVALID_ENUM for GL_DEPTH
unconditionally.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-12 18:22:48 -05:00
Ilia Mirkin d33ef19479 mesa: allow DEPTH_STENCIL_TEXTURE_MODE queries in GLES 3.1 contexts
This fixes

dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.depth_stencil_mode_integer

and a few related tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-02-12 18:22:48 -05:00
Kenneth Graunke 2a0fc82864 i915: include teximage.h
To get _mesa_num_tex_faces() prototype.
2016-02-12 15:20:29 -08:00
Brian Paul 320ccf710e i965: include teximage.h
To get _mesa_num_tex_faces() prototype.
2016-02-12 15:42:54 -07:00
Axel Davy cc0114f30b st/nine: Implement Managed vertex/index buffers
We were implementing those the same way than
the default pool, which is sub-optimal.

The buffer is supposed to return pointer to
a ram copy when user locks, and automatically
update the vram copy when needed.

v2: Rename NineBuffer9_Validate to NineBuffer9_Upload
Rename validate_buffers to update_managed_buffers
Initialize NineBuffer9 managed fields after the resource
is allocated. In case of allocation failure, when the dtor
is executed, This->base.pool is then rightfully set.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-02-12 23:26:36 +01:00
Axel Davy 77d6c11f8f st/nine: Align stack for entry points
For 32 bits, incoming stack is 4-byte aligned.
We need to realign the stack to 16-byte at some point,
or there are issues later (crash with SSE, llvm, etc).

This patch chooses to align the stack at API entry points.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-02-12 23:26:36 +01:00
Axel Davy d7a5468da9 st/nine: Drop path for ureg_NRM and ureg_CLAMP
using MIN/MAX is fine instead of CLAMP.
NRM doesn't exist anymore.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-12 23:26:36 +01:00
Axel Davy 6b43f5b1d4 st/nine: Remove usage of SQRT in ff code
SQRT is not supported everywhere, so replace
it by RSQ + MUL and handle case <= 0.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-02-12 23:26:36 +01:00
Axel Davy 17078d92ea st/nine: Fix stateblocks crashes with lights
We had several issues of crashes with it.
This should fix it.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-12 23:26:36 +01:00
Axel Davy 6cba347530 st/nine: SCRATCH does support all formats
Add new argument to d3d9_to_pipe_format_checked to
be able to bypass format support checks. This argument
is set to TRUE when the requested Pool is SCRATCH.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-12 23:26:36 +01:00
Axel Davy dbcb4f46ad st/nine: Add format checks to create_zs_or_rt_surface
Returns INVALIDCALL when trying to create a surface
of unsupported format.

In practice, apps are supposed to check for format
support before trying to create a render target
of that format. However some bad behaving apps
could just try to create the surface and deduce if
it failed that it wasn't supported.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-12 23:26:36 +01:00
Axel Davy 3a2e0c7784 st/nine: Support ATI1/ATI2 for CubeTexture
Texture and CubeTexture use common code,
and thus ATI1/ATI2 is already implemented
for CubeTexture.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-12 23:26:36 +01:00
Axel Davy 6c4774bbe4 st/nine: Clean pSharedHandle Texture ctors checks
Clarify the behaviour and clean the checks

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-12 23:26:36 +01:00
Axel Davy bb65b189f3 st/nine: Move texture creation checks
We were having checks at both Create*Texture functions
and in ctors.

Move all Create*Texture checks to ctors.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-12 23:26:36 +01:00
Axel Davy d973a525d3 st/nine: Clean useless code in texture9.c
This->base.base.resource is worth NULL
for SYSTEMMEM textures.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-12 23:26:36 +01:00
Axel Davy 36b4bb303c st/nine: Do not set SHARED flag for shared textures.
We do not support shared textures, thus no need to set
the shared flag.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-12 23:26:36 +01:00
Axel Davy 77a5871c1d st/nine: Do not set resource usage for SYSTEMMEM
We do not create a resource for SYSTEMMEM textures,
thus we do not need to set resource usage.

The only exception is vertexbuffer SYSTEMMEM, since
we do use a pipe resource for them.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-12 23:26:36 +01:00
Brian Paul 9675fb6c68 mesa: move _mesa_num_tex_faces() to teximage.h
So it's near the other cube map helper functions.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-02-12 15:11:38 -07:00
Brian Paul 6e09df24b5 mesa: simplify some code with new _mesa_cube_face_target() function
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-02-12 15:11:38 -07:00
Brian Paul 82db969ac0 mesa: add _mesa_cube_face_target() helper
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-02-12 15:11:24 -07:00
Brian Paul d73f5a3133 mesa: make _mesa_tex_target_to_face() an inline function
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-02-12 15:10:37 -07:00
Brian Paul 6a08673c5e mesa: remove _ARB suffix from cube map enums
Just minor clean-up so we're consistent everywhere.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-02-12 15:10:15 -07:00
Brian Paul ae70d0d68c docs: Visual Studio 2013 or later is now required 2016-02-12 15:08:35 -07:00
Timothy Arceri 4e59362d1b glsl: replace _strtoui64() with strtoull() for MSVC
Now that MSVC 2013 is required we can remove this.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-02-13 08:57:01 +11:00
Jose Fonseca 950da38164 mesa: Use _aligned_malloc/free for MinGW too.
We already use these for gallium in
src/gallium/auxiliary/os/os_memory_stdc.h and it's always better to
minimize divergences between MinGW and MSVC.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-12 14:51:28 +00:00
Jose Fonseca c69ef377c8 mesa: Remove support for MSVC2008.
Spotted by Emil Velikov.

Trivial.
2016-02-12 10:31:15 +00:00
Jose Fonseca 5bc8d34526 util/u_atomic: Remove MSVC 2008 support.
Spotted by Emil Velikov.

Trivial.
2016-02-12 10:31:15 +00:00
Topi Pohjolainen 30711d984f i965: Stop considering if msrt aux buffers need aux buffer
Auxiliary buffers are always created with sample number of zero
which effectively prevents intel_miptree_create_layout() from trying
to associate auxiliary buffers with auxiliary buffers.

Now that there is more direct path available lets start using it
instead and stop even checking for such (im)possibility.

v2 (Ben): Do not signal msaa layout with explicit argument but
          using layout_flags instead.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2016-02-12 09:17:29 +02:00
Topi Pohjolainen 422b1386d7 i965: Separate miptree creation from auxiliary buffer setup
Currently the logic allocating and setting up miptrees is closely
combined with decision making when to re-allocate buffers in
X-tiled layout and when to associate colors with auxiliary buffers.

These auxiliary buffers are in turn also represented as miptrees
and are created by the same miptree creation logic calling itself
recursively. This means considering in vain if the auxiliary buffers
should be represented in X-tiled layout or if they should be
associated with auxiliary buffers again.
While this is somewhat unnecessary, this doesn't impose any problems
currently. Miptrees for auxiliary buffers are created as simgle-sampled
fusing the consideration for multi-sampled compression auxiliary
buffers. The format in turn is such that is not applicable for
single-sampled fast clears (that would require accompaning auxiliary
buffer).
But once the driver starts to support lossless compression of color
buffers the auxiliary buffer will have a format that would itself
be applicable for lossless compression. This would be rather
difficult and ugly to detect in the current miptree creation logic,
and therefore this patch seeks to separate the association logic
from the general allocation and setup steps.

v2 (Ben):
   - Do not reconsider for X-tiling in intel_miptree_create()
     as it was just forced to Y-tiling in miptree_create().
   - Do not drop checks for allocation failures.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-02-12 09:13:07 +02:00
Topi Pohjolainen d089f2d932 i965: Isolate aligned dimensions for stencil only
This makes the logic a little more explicit and helps to keep
subsequent patches easier to read.

Suggested-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-02-12 09:13:07 +02:00
Topi Pohjolainen 0dcd9a09d1 i965: Restore vbo after color resolve during brw_try_draw_prims()
Part of brw_try_draw_prims() is a check to validate textures
(brw_validate_textures()). In case of textures that currently have
only level zero but are marked for mipmap generation, i965 driver
will decide to replace the underlying buffer with a larger one
capable of holding also the additional levels. This results into
blit from the original buffer to the newly allocated (see
intel_miptree_copy_teximage()). This blit is currently handled with
blitter engine and hence it won't effect the ongoing draw operation.
However, this blit in turn may trigger color resolve on the source
buffer. In principle, this should be possible with fast cleared
buffers but I only started hitting it when I enabled lossless
compression (that reguires similar resolve to fast cleared buffers).

Now, the color resolve is a meta operation and uses the same drawing
path we are already in middle of. After quite a bit of debugging I
realized that the resolve will modify the current vbo setup but it
won't restore it afterwards resulting in the original draw call
using wrong vertex data.
When brw_try_draw_prims() gets called, the vbo logic in the Mesa
core (see vbo_draw_arrays()) has just bound the vbo (see
vbo_bind_arrays() and recalculate_input_bindings()). Color resolve
operation will overwrite the vbo setup by calling vbo_bind_arrays()
against the resolve rectangle (see brw_draw_rectlist()). Once the
color resolve is done the vbo setup is left to the resolve rectangle
state and the original drawing call yields bogus results.

This patch aims to restore the original state after the color
resolve by calling vbo_bind_arrays() yet again after the vertex
array state in the core context have been restored.

Now having said all this, I'd also like to state that I'm quite
uncomfortable with the nested meta operations. Ths original draw
call in this case is in fact a meta operation itself. It is a blit
from level zero to level one when generating the additional mipmap
levels (see _mesa_meta_GenerateMipmap()). Imagine the complexity
if the blit in the middle from buffer to another would go to meta
path also instead of blitter.

I would very tempted to try to move all the resolves to happen
before a meta operation is started.
Additionally I still feel that work I did earlier in the spring/
summer time moving meta operations to use direct state upload
bypassing the core context would make sense.

v2: Force input recalculation by setting the flag explicitly

v3: Do not attempt to restore vbo for opengles1 which doesn't
    support vertex buffer objects.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-02-12 09:13:07 +02:00
Topi Pohjolainen 779429d063 i965: Validate textures before altering driver state
Validation may kick off copies and subsequently color resolves.
Color resolves (and the copies themselves if ending up in meta path)
will overwrite the internal driver state but are not prepared to
restore it. Instead of adding that capability the validation can be
simply performed before the state is updated.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-02-12 09:13:07 +02:00
Kenneth Graunke 76f6f59c6e i965: Make brw_clear_cache flag all the bits on both pipelines.
Setting brw->ctx.NewDriverState and brw->ctx.NewGLState affects
the dirty bits for the current pipeline.  But, we need to flag
everything dirty on *both* pipelines, so that when we switch
back, we'll realize our programs are stale and re-upload them.

To accomplish this, flag the saved state for both pipelines.
Only one of them should matter, but this way we don't have to
check which we need to set.  It's harmless to set the other.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-11 22:53:19 -08:00
Samuel Iglesias Gonsálvez 61ceb36ead glsl: Allow invariant qualifer in block members in desktop OpenGL.
Feedback from Khronos is that 'invariant' should be allowed on block
members for desktop OpenGL. Fix piglit regression added by fe1e89a0:
invariant-qualifier-in-out-block-01.vert

v2:
- Allow it for in/out blocks in OpenGL ES too, so when OES_shader_io_blocks
is supported we don't need to do any change (Timothy)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89330
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-02-12 07:20:47 +01:00
Kenneth Graunke e9644cb1f9 i965: Consider tessellation in get_pipeline_state_l3_weights.
I think this was just missed; Curro and I were probably writing
code simultaneously and forgot to combine them at the end.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-02-11 19:15:17 -08:00
Kenneth Graunke f275c61c30 i965: Split brw_upload_texture_surfaces into compute/render atoms.
When uploading state for the compute pipeline, we don't want to
look at VS/TCS/TES/GS/FS programs, as they might be stale, and
aren't relevant anyway.  Likewise, the render pipeline shouldn't
look at CS.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-02-11 19:15:08 -08:00
Marek Olšák f3943614ff radeonsi: fix build with LLVM 3.6
Broken by this cleanup: 3dc1cb0cc7

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-12 00:41:36 +01:00
Jason Ekstrand 9f8c01b03c i965/gs: Pass VerticesIn though prog_data
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-02-11 15:07:20 -08:00
Jason Ekstrand 56eb9c44ad i965/fs: Pass usage of depth, W, and sample mask through prog_data
We really need to stop pulling information directly out of shaders for
state setup.  For one thing, if we want any sort of an on-disk shader
cache, having all of this metadata in one place is going to be crucial.
Also, passing it all through prog_data cleans up the compiler <-> state
setup API substantially.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-02-11 15:07:20 -08:00