Commit Graph

43974 Commits

Author SHA1 Message Date
Eric Anholt f147599ef4 i965: Remove linear_color for GL_PERSPECTIVE_CORRECTION_HINT.
From the GL 2.1 spec:

   "Required perspective-correct interpolation for all fragment
    attributes except depth in sections 3.4.1 and 3.5.1, effectively
    making GL PERSPECTIVE CORRECT HINT a no-op."

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-26 10:07:38 -07:00
Eric Anholt c095335fa5 intel: Drop doubly irrelevant code in intelReadBuffers.
First, FBO read/draw == NULL validation happens in mesa core not
intelReadBuffers -> intel_draw_buffers.  Second, that condition is no
longer tested for in our driver since ARB_ES2_compatibility was added.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-05-26 08:54:29 -07:00
Eric Anholt 6d4b974e89 mesa: Flush vertices before updating drawbuffer computed state.
Otherwise, the driver is likely to draw the flushed vertices to the
new drawbuffer instead of the old one, missing the point of the flush.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-05-26 08:54:29 -07:00
Eric Anholt d3451f7f9c mesa: Allow NULL read/draw in complete FBOs in ARB_ES2_compatibility.
From the ARB_ES2_compatibility spec:

    "(8) How should we handle draw buffer completeness?

    RESOLVED: Remove draw/readbuffer completeness checks, and treat
    drawbuffers referring to missing attachments as if they were NONE."

Fixes arb_es2_compatibility-drawbuffers when the short-circuit for
ARB_ES2_compatibility in the previous commit is dropped.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-05-26 08:54:29 -07:00
Eric Anholt f73ff463a2 mesa: Trigger FBO validation on DrawBuffers change in non-ES2 mode.
glDrawBuffers pointing at an unattached buffer is supposed to be
incomplete without ARB_ES2_compatibility.  The testcase to catch the
bug of not implementing that bit of the spec was tricked by this
missing piece of state update.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-05-26 08:54:29 -07:00
Brian Paul 179a88d52c mesa: minor whitespace fixes 2011-05-25 21:07:50 -06:00
Brian Paul f84be846ca mesa: plug in sync object display list functions
Most just dispatch through to the immediate mode functions, except
for glWaitSync(), per the extension spec.
2011-05-25 21:06:51 -06:00
Brian Paul 95fa22c864 mesa: display list support for glProgramParameteriARB() 2011-05-25 20:44:35 -06:00
Brian Paul 001aa6c979 mesa: plug shader object functions into display list dispatch 2011-05-25 20:39:08 -06:00
Brian Paul 4535c98cdb mesa: plug in GL 3.0 ClearBuffer() display list functions 2011-05-25 20:27:44 -06:00
Brian Paul 8f7c815568 mesa: fill in missing sampler object display list functions 2011-05-25 20:20:22 -06:00
Brian Paul 3e06803c2c st/mesa: simplify some st_context(ctx)->pipe code 2011-05-25 18:16:03 -06:00
Brian Paul bf14ab417c st/mesa: fix incorrect texture level/face/slice accesses
If we use FBOs to access mipmap levels with glRead/Draw/CopyPixels()
we need to be sure to access the correct mipmap level/face/slice.
Before, we were just passing zero in quite a few places.

This fixes the new piglit fbo-mipmap-copypix test.

NOTE: This is a candidate for the 7.10 branch.
2011-05-25 18:07:35 -06:00
Jakob Bornecrantz 1697dac642 i915g: Bump texture sizes
Spotted and tested by Christopher Egert.

Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com>
2011-05-25 22:06:11 +02:00
Eric Anholt b5846865de i965: Warnings cleanup.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 11:16:36 -07:00
Eric Anholt fa42de5ad7 i965: Fix assertion failures in unused brw_reg setup by deleting it.
I was using undefined values to create an unused value.  Go me.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=37366
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 11:16:36 -07:00
Alex Deucher 5ed7a7b720 r600g: remove duplicate opcode in r600_opcodes.h
V_SQ_CF_WORD1_SQ_CF_INST_HALT is 0x1f on both
evergreen and cayman.

Reported-by: Gustaw Smolarczyk <wielkiegie@gmail.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-25 11:04:25 -04:00
Chad Versace e7bcfadc22 intel: Change FBO validation criteria to accomodate hiz and seprate stencil
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-05-25 07:41:32 -07:00
Chad Versace ce8fdf666f intel: Fix intel_draw_buffer() to accomodate hiz and separate stencil
The logic of intel_draw_buffers() expected that stencil buffers were
always combined depth/stencil.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-05-25 07:41:32 -07:00
Chad Versace c270f1a628 intel: Add hiz_region to intel_mipmap_tree
When a texture is attached to multiple FBO's, a separate renderbuffer
wrapper is created for each attachment. This necessitates storing the hiz
region for these renderbuffers in the texture itself instead of the
renderbuffer wrapper.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-05-25 07:41:32 -07:00
Chad Versace 6ed829fe50 intel: Refactor the wrapping of textures with renderbuffers
Before this commit, the renderbuffer's region was updated in
intel_renderbuffer_texture(). This commit moves the update into
intel_update_wrapper(), which is a more logical location for updates.

This is in preparation for the next commit, which allocates and
updates the texture's hiz region in intel_update_wrapper(). Having the two
region updates located in the same function makes good form.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-05-25 07:41:32 -07:00
Chad Versace 7c0e6d9bbc intel: Add hiz_region to intel_renderbuffer
A hiz surface must be supplied to the hardware when rendering to a depth
buffer with hiz. There are three potential places to store that surface:
    1. Allocate a larger intel_region for the depthbuffer, and let the
       region's tail be the hiz surface.
    2. Allocate a separate intel_region for hiz, and store it as
       brw_context state.
    3. Allocate a separate intel_region for hiz, and store it in
       intel_renderbuffer.

We choose method 3.

Method 1 has not been chosen due to future complications it might cause
when requesting a DRI drawable's depth buffer attachment from X.

Method 2 has not been chosen because storing the hiz region apart from
the depth region makes lazy hiz/depth resolves difficult to implement.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-05-25 07:41:32 -07:00
Chad Versace a9e6509785 intel: Add is_hiz_depth_format() to intel_contex.vtbl
Given a format, is_hiz_depth_format() indicates if HiZ can be enabled on
a depthbuffer of that format.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-05-25 07:41:32 -07:00
Chad Versace 1a1411e09b intel: Allocate region for separate stencil buffer
... in intel_alloc_renderbuffer_storage().  The stencil buffer has quirky
pitch requirements, so its region allocation is a special case.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-05-25 07:41:32 -07:00
Chad Versace b5c847c7ca intel: Change supported texture formats for separate stencil
When hardware supports separate stencil, enable support for separate
depth/stencil texture formats in the table
intel_context.ctx.TextureFormatsSupported. If the hardware must use
separate stencil, then disable support for combined depth/stencil formats.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-05-25 07:41:31 -07:00
Chad Versace 4e0654ec29 mesa: Add MESA_FORMAT_X8_Z24 to _mesa_choose_tex_format
Prefer MESA_FORMAT_X8_Z24 over MESA_FORMAT_S8_Z24 for textures with
internal format GL_DEPTH_COMPONENT*.

i965 needs MESA_FORMAT_X8_Z24 for HiZ and separate stencil.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-05-25 07:41:31 -07:00
Chad Versace 76f77cb07e intel: Add flags to intel_context for hiz and separate stencil
Add the following flags:
    intel_context.has_separate_stencil
    intel_context.must_use_separate_stencil
    intel_context.has_hiz

The flags are currently set to false, and will be enabled for a given
chipset once the feature is completely implemented.

Since it may be some time before these features are completed, their
values can be overridden with environment variables INTEL_HIZ and
INTEL_SEPARATE_STENCIL. Valid values for these environment variables are
"0" and "1".

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-05-25 07:41:31 -07:00
Adam Jackson a95ec18549 glx: Don't refer to the request buffer outside of {L,Unl}ockDisplay
... because that's not a safe thing to do.  The request buffer is shared
storage among all threads, and after UnlockDisplay the 'req' pointer may
point into someone else's request.

NOTE: This is a candidate for the 7.10 branch.

Signed-off-by: Adam Jackson <ajax@redhat.com>
2011-05-25 06:19:29 -04:00
Alex Deucher c44dad559a egl_dri2: add new cayman pci ids
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-25 01:27:34 -04:00
Alex Deucher 017cd5dcc3 r600g: fix eg/cayman scissor workaround
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-24 22:44:16 -04:00
Dave Airlie 868c04205c r600g: add workaround for buggy hw scissor on eg/cayman.
This is ported from the same fix to the DDX.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-25 11:50:17 +10:00
Dave Airlie 7779f6d1df r600g: add initial cayman acceleration support.
Cayman is the RadeonHD 69xx series of GPUs. This adds support for
3D acceleration to the r600g driver.

Major changes:
Some context registers moved around - mainly MSAA and clipping/guardband related.
GPR allocation is all dynamic
no vertex cache - all unified in texture cache.
5-wide to 4-wide shader engines (no scalar or trans slot)
	- some changes to how instructions are placed into slots
	- removal of END_OF_PROGRAM bit in favour of END flow control clause
	- no vertex fetch clause - TC accepts vertex or texture

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-25 11:42:45 +10:00
Dave Airlie d1b8f8e8b3 r600g: don't lookup a vs semantic for position/face.
These don't need one, and I was seeing 0xff being returned and set in
the GPU registers with some tests.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-25 10:01:25 +10:00
Dave Airlie ece871c038 r600g: flush the DB dest base as well.
If we do this for CB bases then we should do it for DB bases.

noticed while adding cayman support.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-25 09:37:33 +10:00
Adam Jackson 3869be74af glx: More comment cleanup
Signed-off-by: Adam Jackson <ajax@redhat.com>
2011-05-24 16:45:02 -04:00
Adam Jackson a3aecd190b glx: Remove some misleading comments
These functions have already been modified for direct rendering.

Signed-off-by: Adam Jackson <ajax@redhat.com>
2011-05-24 16:44:33 -04:00
Adam Jackson 5a6897ff0b drisw: Namespace better for ease of navigation
Signed-off-by: Adam Jackson <ajax@redhat.com>
2011-05-24 16:44:21 -04:00
Adam Jackson b24f291e42 drisw: dead store removal
Signed-off-by: Adam Jackson <ajax@redhat.com>
2011-05-24 16:43:53 -04:00
Mike Kaplinskiy d3b6e8a2b8 mesa: fix glGetTexImage for cases when srgb decode is skipped
See http://bugs.freedesktop.org/show_bug.cgi?id=37150

Signed-off-by: Brian Paul <brianp@vmware.com>
2011-05-24 09:06:04 -06:00
Brian Paul cd5417aac7 st/mesa: prefer formats without stencil for DEPTH_COMPONENT
for fast Z clears to be used more often.

Original patch by Marek Olšák.  Rebased to table-driven st_choose_format()
by Brian Paul.
2011-05-24 09:00:17 -06:00
Brian Paul d57e95f22a st/mesa: rewrite st_choose_format() to be table driven
Instead of using a giant switch statement with lots of code, use a
table to convert GL format enums to pipe formats.

Tested by running the old code next to the new and asserting that
the return value was the same for piglit tests.

We're doing a linear search, but if that ever appears to be too slow
the table could easily be sorted or hashed.
2011-05-24 08:49:01 -06:00
José Fonseca c3c1976f52 wgl: Don't hold on to user supplied HDC.
Certain applications (e.g., Bernina My Label, and the Windows
implementation of Processing language) destroy the device context used when
creating the frame-buffer, causing presents to fail because we were still
referring to the old device context internally.

This change ensures we always use the same HDC passed to the ICD
entry-points when available, or our own HDC when not available (necessary
only when flushing on single buffered visuals).
2011-05-24 13:12:39 +01:00
Thierry Reding 5af46e8360 mesa: Fix remap_table setup.
Since the SET_xxx and GET_xxx macros used to initialize the remap_table
have been replaced by inline functions, the missing late macro expansion
leads to driDispatchRemapTable not being redefined to remap_table, which
in turn causes the remap_table not to be setup properly.

This commit fixes the issue by moving the table redefinition after the
definition of driDispatchRemapTable but in front of the inline function
definitions.
2011-05-23 16:19:44 +01:00
Adam Jackson e8b1c6d6f5 mesa: Fix return type of _mesa_get_format_bytes() (#37351)
Despite that negative values aren't sensible here, making this unsigned
is dangerous.  Consider get_pointer_generic, which computes a value of
the form:

    void *base + (int x * int stride + int y) * unsigned bpp

The usual arithmetic conversions will coerce the (x*stride + y)
subexpression to unsigned.  Since stride can be negative, this is
disastrous.

Fixes at least the following piglit tests on Ironlake:

    fbo/fbo-blit-d24s8
    spec/ARB_depth_texture/fbo-clear-formats
    spec/EXT_packed_depth_stencil/fbo-clear-formats

NOTE: This is a candidate for the 7.10 branch.

Reviewed-by: Chad Versace <chad.versace@intel.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2011-05-23 11:07:34 -04:00
Kenneth Graunke d0c6d24a9e i965/gen7: Fix miptree layout for cube surfaces.
Volume 1a section 8.20.4.7.3 gives new equations which multiply by 12
instead of 11.

Fixes 8 piglit tests:
- fbo-cubemap
- texCube
- glsl-fs-texturecube
- glsl-fs-texturecube-2
- glsl-fs-texturecube-2-bias
- glsl-fs-texturecube-bias
- arb_seamless_cubemap
- cubemap

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-22 15:01:16 -07:00
Kenneth Graunke b522eb0717 i965: Remove comments about pre-965 hardware.
They're irrelevant for this driver.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-22 15:01:16 -07:00
pepp fd6f2d6e57 st/mesa: assign renderbuffer's format field when allocating storage
See http://bugs.freedesktop.org/show_bug.cgi?id=36173

NOTE: This is a candidate for the 7.10 branch.

Signed-off-by: Brian Paul <brianp@vmware.com>
2011-05-21 09:49:14 -06:00
Christian König 3c5e741862 r600g: fix "Fixed-Point Data Conversions"
According to OpenGL 3.1 chapter 2.1.5 the representation without zero
should only be used for vertex attribute values, but not for textures
or frame-buffers.
2011-05-21 16:40:20 +02:00
Kenneth Graunke 9be8524af7 i965: Fix sampling on Ivybridge after headerless change.
Fixes a regression since 90e922267a.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-20 16:33:43 -07:00
Kenneth Graunke 24de02acac i965: Remove "TXD" from justification of sampler message headers.
The coordinate offsets set in the m1 header are for textureOffset;
they have nothing to do with textureGrad (TXD).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-20 16:33:43 -07:00