Commit Graph

62965 Commits

Author SHA1 Message Date
Brian Paul ef6b6658f9 mesa: fix double-freeing of dispatch tables inside glBegin/End.
We allocate dispatch tables for BeginEnd and OutsideBeginEnd.  But
when we destroy the context we were freeing the BeginEnd and Exec
tables.  If Exec==BeginEnd we did a double-free.  This would happen
if the context was destroyed while inside a glBegin/End pair.  Now
free the BeginEnd and OutsideBeginEnd pointers.

Cc: "10.1", "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-16 07:14:57 -06:00
Matt Turner 730bc124c3 i965: Use binary literals counter select.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 23:31:27 -07:00
Michel Dänzer 2bab95973d glsl_to_tgsi: Make sure the 'shader' member is always initialized
Fixes the valgrind report below and random crashes with piglit on radeonsi.

==30005== Conditional jump or move depends on uninitialised value(s)
==30005==    at 0xB13584E: st_translate_program (st_glsl_to_tgsi.cpp:5100)
==30005==    by 0xB14698B: st_translate_fragment_program (st_program.c:747)
==30005==    by 0xB14777D: st_get_fp_variant (st_program.c:824)
==30005==    by 0xB11219C: get_color_fp_variant (st_cb_drawpixels.c:1042)
==30005==    by 0xB1131AE: st_DrawPixels (st_cb_drawpixels.c:1154)
==30005==    by 0xAFF8806: _mesa_DrawPixels (drawpix.c:162)
==30005==    by 0x4EB86DB: stub_glDrawPixels (generated_dispatch.c:6640)
==30005==    by 0x4F1DF08: piglit_visualize_image (piglit-util-gl.c:1574)
==30005==    by 0x40691D: draw_image_to_window_system_fb(int, bool) (draw-buffers-common.cpp:733)
==30005==    by 0x406C8B: draw_reference_image(bool, bool) (draw-buffers-common.cpp:854)
==30005==    by 0x40722A: piglit_display (alpha-to-coverage-dual-src-blend.cpp:117)
==30005==    by 0x4EA7168: run_test (piglit_fbo_framework.c:52)

Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-05-16 11:12:45 +09:00
Roland Scheidegger b416645387 gallivm: remove optimization workaround when not having sse 4.1
This workaround doesn't list any llvm version, but it was introduced
2010-06-10 (e277d5c1f6). It is unlikely
this bug is still present in llvm versions we support (3.1+).
There's no specific test listed, but I ran lp_test_arit (which uses
the mentioned functions) on llvm 3.1 and 3.3 with sse41 disabled and
this pass enabled without issues.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-05-16 01:09:34 +02:00
Roland Scheidegger 93731fbeec gallivm: remove workaround for reversing optimization pass order.
32bit code generation and llvm >= 2.7 used a different optimization pass
order - this code was initially introduced (2010-07-23) by
815e79e72c, apparently due to buggy code being
generated with then brand new llvm versions (which was llvm 2.7 plus pre 2.8
devel).
It seems very highly likely that whatever this bug was it has been fixed in
newer llvm versions, though there's no easy way to test this - the mentioned
piglit test has been removed years ago, and even if you'd build it I'm
sceptical the glsl compiler would still produce the required code to trigger
it.
I have no idea what a good order of passes is, but just remove the workaround
and use the same order everywhere.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-05-16 01:09:34 +02:00
Matt Turner 8a6f7dfc19 i965/gen8: Make disassembly function match brw's signature.
gen8_dump_compile will be called indirectly by code common used by
generations before and after the gen8 instruction format change.

Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 15:45:40 -07:00
Matt Turner 1ef52d6ab3 i965: Pass brw_context and assembly separately to brw_dump_compile.
brw_dump_compile will be called indirectly by code common used by
generations before and after the gen8 instruction format change.

Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 15:45:40 -07:00
Matt Turner 74b252d270 i965: Pull brw_compact_instructions() out of brw_get_program().
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 15:45:40 -07:00
Matt Turner cce3bea2a7 i965/disasm: Align send instruction meta-information with dst.
Has been misaligned since we added instruction offset prefixes.

Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 15:45:40 -07:00
Matt Turner e00fe451b8 i965/disasm: Disassemble the compaction control bit.
brw_disasm doesn't disassemble compacted instructions, so we uncompact
before disassembling them which would unset the compaction control bit.
Instead pass it as a separate argument.

Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 15:45:40 -07:00
Matt Turner 58bcf5996d i965/cfg: Embed exec_node in bblock_link.
In order to remove bblock_link's inheritance of exec_node. Also makes
linked list walk code much nicer.

Acked-by: Eric Anholt <eric@anholt.net>
2014-05-15 15:45:40 -07:00
Matt Turner a77023c992 i965/cfg: Make brw_cfg.h closer to C-includable.
Only bblock_link's inheritance left.

Acked-by: Eric Anholt <eric@anholt.net>
2014-05-15 15:45:40 -07:00
Matt Turner d4d843e02f i965/cfg: Protect brw_cfg.h from multiple inclusion.
Acked-by: Eric Anholt <eric@anholt.net>
2014-05-15 15:45:39 -07:00
Matt Turner 9b0108ddc1 glsl: Add C-callable fprint_ir function.
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 15:45:39 -07:00
Topi Pohjolainen d45fadf11a i965/fb: Use meta path for stencil up/downsampling
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-05-15 21:39:33 +03:00
Topi Pohjolainen 475216a4f0 i965/meta: Stencil blit for miptree updownsampling
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 21:39:33 +03:00
Topi Pohjolainen b18f6b9b86 i965/fb: Use meta path for stencil blits
This is effective only on gen8 for now as previous generations still
go through blorp.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 21:39:33 +03:00
Topi Pohjolainen d1829badf5 i965/meta: Stencil blits
v2: Create the intel renderbuffer with level hardcoded to zero instead
    of overriding it in the surface state configuration. Also moved the
    dimension adjustments for tiling, mip level, msaa into the render
    buffer creation. Finally prepares for another blit path needed for
    miptree updownsampling.
v3 (Ken): Dropped unnecessary memory context for "ralloc_asprintf()"

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-05-15 21:39:33 +03:00
Topi Pohjolainen 9d752c098c i965: Extend brw_get_rb_for_first_slice() for specified level/layer
v2: Configure stencil directly for final dimensions instead of
    adjusting bit by bit for tiling, mip level and msaa.
v3 (Ken): Used non-static constant for horizontal alignment

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 21:39:33 +03:00
Topi Pohjolainen 36caae48b2 i965/gen8: Surface state overriding for stencil
v2: Allow hardware to offset accesses to individual layers. Also leave
    the mip-level overriding for the creator of the intel renderbuffer
    to handle. Merged with "i965/gen8: Allow stencil buffers to be
    configured as single sampled"

Ken: I left the "_mesa_problem()" still in place. I think it is clearer
     to remove it in a separate patch.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 21:39:32 +03:00
Topi Pohjolainen 6aefaa4eb2 i965/wm: Surface state overrides for configuring w-tiled as y-tiled
v2: Use intel_mipmap_tree::total_width in order to get correct alignment
    automatically. Also use "mt->total_height / mt->physical_depth0" as
    surface height allowing hardware to offset to correct slice.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 21:39:32 +03:00
Jordan Justen 103057b2b7 i965 meta up/downsample: Fix renderbuffer _BaseFormat
mt->format is of type mesa_format, and therefore can't be
used with _mesa_base_fbo_format which requires a GLenum input.

On gen8, this fixes various piglit fbo-depthstencil tests with
samples > 1.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-15 10:49:05 -07:00
Matt Turner 255357f79b i965: Delete current_insn() function. 2014-05-15 10:35:55 -07:00
Matt Turner 006232bcde i965: Remove blorp unit tests.
They've served their purpose (in transitioning blorp to using
fs_generator) and now they just necessitate large amounts of manual
labor to regenerate if the disassembler changes.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-15 10:35:55 -07:00
Emil Velikov 39ae284a69 egl-static: include libradeonwinsys.la only once
With this and the previous patch, we no longer have multiple
definitions in the final egl_gallium.so.

v2: Drop duplicate libloader link.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Chia-I Wu <olv@lunarg.com> (v1)
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> (v1)
2014-05-15 17:32:31 +01:00
Emil Velikov d812c74582 gallium/radeon: link in libradeon.la at target level
It makes more sense to link the core and common parts of the driver as the
target is build. Additionally this will help us drop duplicating symbols
for targets that static link mulitple pipe-drivers. Only egl-static needs
that currently with more to come.

To simplify things a bit add HAVE_GALLIUM_RADEON_COMMON variable.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2014-05-15 17:32:30 +01:00
Emil Velikov 6fcc0b0ba5 gallium/radeon: build only a single common library libradeon
Just fold libllvmradeon in libradeon.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2014-05-15 17:32:30 +01:00
Rob Clark 670418740f freedreno/a3xx: fix write to bogus register
The loops for updating the multiple packed fields in SP_VS_OUT[] and
SP_VS_VPC_DST[] will zero out one register beyond the last that on
required.  Which is normally not a problem (and is kinda convenient
when looking at cmdstream dumps) unless we have maximum (16) varyings.

Fix loop termination condition so that this does not happen.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-14 21:26:35 -04:00
Rob Clark c37889b5ac freedreno/a3xx: account for special inputs/outputs
We need to size input/output tables big enough for special inputs/
outputs (gl_Position, gl_FrontFacing, etc) which, while they don't
count towards the hw limit of 16 attributes or 16 varyings, we do
still need to track them all the same.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-14 21:26:35 -04:00
Rob Clark 5dcf59e142 freedreno/a3xx: fix MAX_INPUTS shader cap
Hardware only supports 16.  Which fd3_shader_variant properly reflected,
but the pipe cap did not, leading to array overflow (and shaders that
could not possibly work).

Also a bunch of asserts to make problems like this easier to see.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-14 21:25:53 -04:00
Rob Clark e1896948da freedreno/a3xx: add debug flag to expose glsl130
We are starting to add integer support to the compiler, which does not
get exercised with glsl feature level 120 and without advertising
integer support.  But doing so breaks too many things right now.  So
for now use a debug flag to conditionally expose the functionality
while it is in development.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-14 21:20:29 -04:00
Ryan Houdek ac2a8e3c9d freedreno/a3xx/compiler: add KILL_IF
The KILL_IF opcode could potentially be merged in to the regular KILL
opcode function.  It was a pain to do so, so I've left is separated
for cleanliness.

Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-14 21:19:43 -04:00
Ryan Houdek a889049400 freedreno/a3xx/compiler: start adding integer support
Adds a large sum of TGSI opcodes to the a3xx compiler.

For integer opcodes we have 28 opcodes added.
Adds 4 floating point compare opcodes

If GLSL 1.30 is enabled, this allows the GLSL 1.30 piglits to have a
completion amount of 432/641.

Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-14 21:19:21 -04:00
Roland Scheidegger 8620730f8a draw: better llvm names for shaders for debugging.
All shaders had the same name.
We could probably use some identifier per shader too, but for now only use
the variant number.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-05-15 02:35:35 +02:00
Roland Scheidegger 65ad90bd1b llvmpipe: improve setup shader names (for debugging)
The setup shaders were composed of both a fs shader number and a variant
number. But since they aren't tied to a particular fragment shader, the
former was a fixed zero while the latter was also always zero because
it was never assigned. So, similar to what the fs code does, use a ever
increasing number to give it a more catchy name (unlike fragment shaders
though where this number is for each explicitly created shader, we just use
it for the implicitly created variants).
And while here, fix whitespace a bit.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-05-15 02:35:29 +02:00
Roland Scheidegger 1d28650b55 llvmpipe: kill off llvmpipe_variant_count
Unused except it was increased for both fs and setup shader variants created.
Probably some leftover from ages ago.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-05-15 02:35:26 +02:00
Roland Scheidegger 3e817e7e56 mesa/st: fix number of ubos being declared in a shader
Previously the code used the total number of ubos being declared in the
linked program (so the ubos of all shaders combined), use the number
from the particular shader instead.
This fixes an assertion failure with piglit arb_uniform_buffer_object-maxblocks
seen in llvmpipe since 8a9f5ecdb1 as it now emits
code for each declared buffer, not just the ones actually used.

CC: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-05-15 02:35:25 +02:00
Ben Skeggs 9c64cb80d2 nvc0: enable support for maxwell boards
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:54:54 +10:00
Ben Skeggs d548d47edf nvc0: add maxwell (sm50) compiler backend
The big missing part here is proper sched data calculations, but
hopefully the chosen placeholder will be sufficient for now.

Passes piglit as well as GK107 does.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:54:49 +10:00
Ben Skeggs 7b9475fa65 nvc0: maxwell isa has no per-instruction join modifier
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:54:46 +10:00
Ben Skeggs 07d3972b49 nvc0: replace immd 0 with $rLASTGPR for emit/restart opcodes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:54:42 +10:00
Ben Skeggs 3723ff5223 nvc0: move nvc0 lowering pass class definitions into header
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:54:39 +10:00
Ben Skeggs bede1bdb48 nvc0: bump sched data member to 32-bits
SM50 backend requires 21 bits per instruction, not 8.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:54:34 +10:00
Ben Skeggs c42d7556d3 nvc0: use vertex arrays for eng3d blit
Maxwell doesn't have immediate-mode.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:54:29 +10:00
Ben Skeggs edb1020ea5 nvc0: restrict "constant vbo" logic to fermi/kepler classes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:54:25 +10:00
Ben Skeggs 322460fdbc nvc0: replace some vb->stride checks with constant_vbo instead
Maxwell no longer has the methods to set constant attributes, and we'll
want to be treating stride 0 vtxbufs the same as for stride > 0.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:54:21 +10:00
Ben Skeggs 9306c3470f nvc0: add maxwell class
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:54:16 +10:00
Ben Skeggs 0079a375a5 nvc0: allow for easier modification of compiler library routines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:54:12 +10:00
Ben Skeggs 737477dac3 nvc0: properly distribute macros in source form
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-15 09:53:56 +10:00
Emil Velikov e48054d036 docs: Add a note about llvm-shared-libs and libxatracker
Both changes landed in 10.2, and for people not following the
development cycle these will come as a surprise. Note that the
pipe_* interface is not stable.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Rob Clark <robclark@freedesktop.org>
2014-05-14 23:44:08 +01:00