Commit Graph

92481 Commits

Author SHA1 Message Date
Rob Herring e8f82bfd52 Android: major/minor/makedev live in <sys/sysmacros.h>
sysmacros.h was getting implicitly included in types.h until recently in
AOSP master. Define MAJOR_IN_SYSMACROS to explicitly include sysmacros.h.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-05-31 16:35:25 -05:00
Chad Versace 22d6b08d2d egl/android: Drop unused 'format' param in get_back_bo()
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-05-31 10:45:57 -07:00
Chad Versace 0bcdcebc85 egl/android: Align channel masks in HAL_PIXEL_FORMAT table
Improves readability. No change in behavior.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-05-31 10:45:57 -07:00
Eric Engestrom 11da77e546 egl/drm: remove temporary fd variable
In all codepaths, this var ends up assigned to the struct, except one:
a cleanup codepath, where the `close()` was removed, leading to fd leaks.
Remove the temp fd and assign to the struct field directly instead.

CovID: 1213930
Fixes: 7ec07beedf ("egl/drm: make use of the
                              dri2_display_destroy() helper")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-05-31 18:09:27 +01:00
Samuel Pitoiset c222fa9ada mesa: throw an INVALID_OPERATION error in get_texobj_by_name()
Because get_texobj_by_name() can already throw a INVALID_ENUM
error, it makes more sense to add a check directly there.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-05-31 12:01:19 +02:00
Samuel Pitoiset b9c3ce529f mesa: add new 'name' parameter to get_texobj_by_name()
To display better function names when INVALID_OPERATION is
returned. Requested by Timothy.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-05-31 12:01:08 +02:00
Samuel Pitoiset 30a4e375f5 radeonsi: remove unused si_pm4_state::compute_pkt
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-31 09:20:57 +02:00
Samuel Pitoiset e4b05a50df radeonsi: remove chip_class define from si_pm4.h
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-31 09:20:55 +02:00
Samuel Pitoiset d90a6c2f23 radeonsi: merge si_pm4_free_state_simple() into si_pm4_free_state()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-31 09:20:53 +02:00
Samuel Pitoiset d8debc6aad mesa/util: fix arithmetic use of 'void *' in u_vector_foreach
u_vector_foreach is currently only used by the Intel Vulkan
driver but when this macro is used in mesa core, GCC reports
a compile-time error. Probably because some compiler options
are different.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-05-31 09:19:54 +02:00
Timothy Arceri 4e93da30f0 mesa: remove _mesa from static function names
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-05-31 11:18:17 +10:00
Timothy Arceri 42fea3622f mesa/st: indentation tidy-up
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-05-31 11:18:17 +10:00
Rob Clark 45e97c994b freedreno/a5xx: drop WFIs in emit_marker5()
Results in always having at least one WFI between draws, which was
slowing stk down by ~5% and ~10% in xonotic.

(also drop bogus assert while we're at it.)

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-30 20:40:58 -04:00
Rob Clark 76214b9919 freedreno/a5xx: timestamp / time-elapsed queries
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-30 20:40:58 -04:00
Rob Clark 5ed9e8fd5d freedreno/a5xx: rename query result struct
Going to want the same thing for timestamp queries.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-30 20:40:58 -04:00
Rob Clark 8c65f17c3b freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-30 20:40:58 -04:00
Kenneth Graunke 236ffbc442 i965: Delete dead old-school packing structs.
Trivial.
2017-05-30 16:22:33 -07:00
Tim Rowley c606edb578 swr/rast: code cleanup (no functional change)
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:22:18 -05:00
Tim Rowley b10c9507ce swr/rast: whitespace changes
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:22:12 -05:00
Tim Rowley ac9d7c3d33 swr/rast: code cleanup (no functional change)
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:22:08 -05:00
Tim Rowley e9e999ae32 swr/rast: allow early-z if shader uses depth value
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:22:02 -05:00
Tim Rowley 628fefc15c swr/rast: move wireframe/point triangle binning after culling
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:21:57 -05:00
Tim Rowley 3b76dea5d1 swr/rast: remove unused functions
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:21:52 -05:00
Tim Rowley d91402fefa swr/rast: code cleanup (no functional change)
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:21:47 -05:00
Tim Rowley 7e271a763e swr/rast: move binner utility functions to binner.h
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:21:41 -05:00
Tim Rowley 5ea9a30f50 swr/rast: SIMD16 FE - fix/use SIMD16 calcDeterminantIntVertical()
Stop double pumping the SIMD8 version.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:21:36 -05:00
Tim Rowley fb9f7bd717 swr/rast: add renderTargetArrayIndex to SWR_PS_CONTEXT
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:21:30 -05:00
Tim Rowley 2438932b7e swr/rast: make simd16 logicops avx512f safe
Express the simd16 logicops in terms of avx512f instructions.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:21:22 -05:00
Tim Rowley 7be26a2d35 swr/rast: SIMD16 FE - add SIMD16 types to jitter
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:21:18 -05:00
Tim Rowley e3c93d8ddf swr/rast: SIMD16 FE - fix PA_STATE_OP::Reset()
Fixes instanced GS.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:21:12 -05:00
Tim Rowley fd14c40734 swr/rast: SIMD16 FE - simplify/refactor StreamOut
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:21:07 -05:00
Tim Rowley a230af8b44 swr/rast: SIMD16 FE - fix conservative rasterization
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:21:02 -05:00
Tim Rowley f64aea0959 swr/rast: SIMD16 FE - interleaved simdvertex output in GS
Eliminates conversion copies on GS output from simdvertex to simd16vertex.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:20:56 -05:00
Tim Rowley cbd33e71f7 swr/rast: fix _simd16_movemask_(ps,pd) native AVX512 intrinsics
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:20:51 -05:00
Tim Rowley 9fd68be133 swr/rast: SIMD16 FE - primitive assembly simplification
Reduce/simplify vertex storage usage in PA_STATE_OPT, fix PA
GetNextVSOutput wrap-around behaviour and eliminate unnecessary
SIMDVERTEX copies/storage for tri fan in PA_STATE_OPT

Fixes the OpenGL tri fan test failure under SIMD16 -
triangle-rasterization-overdraw.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:20:44 -05:00
Tim Rowley 4c23523365 swr/rast: silence write of cfg graph
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:20:39 -05:00
Tim Rowley 7e35777624 swr/rast: add CreateDirectoryPath to recursively create directories
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:20:33 -05:00
Tim Rowley f094d582ec swr/rast: add support for DX1_RGB{_SRGB} formats
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:20:27 -05:00
Tim Rowley 42b4e7cb25 swr/rast: clean up whitespace
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:20:21 -05:00
Tim Rowley 5d542b3204 swr/rast: adjust BinPostSetupPoints* function signature
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:20:15 -05:00
Tim Rowley b714208415 swr/rast: remove extra pixel center adjustment in BinPostSetupPoints
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30 17:19:51 -05:00
Kenneth Graunke 56535959fd anv: Port over CACHE_MODE_1 optimization fix enables from brw.
Ben and I haven't observed these to help anything, but they enable
hardware optimizations for particular cases.  It's probably best to
enable them ahead of time, before we run into such a case.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-05-30 14:59:31 -07:00
Kenneth Graunke 53368b008e genxml: Add Gen9 CACHE_MODE_1 definitons.
These were already in gen8.xml but not gen9.xml.  There are a few new
fields and a couple that have changed.  These are all documented in the
Skylake PRM, Volume 2c Command Reference: Registers, Part 1.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-05-30 14:59:31 -07:00
Kenneth Graunke a8fde221a8 i965: Set the "Float Blend Optimization Enable" bit on Gen9+.
This is woefully undocumented.  It's some kind of optimization that
avoids unnecessary render target reads when blending with a floating
point render target, using independent alpha blending modes.

The internal documentation indicates that this bit exists on Cherryview
as well, but the other driver doesn't appear to set it on that platform.
There's also some confusing wording that indicates that it may exist on
Broadwell, but the documentation says it's reserved, so who knows.

I was not able to find any workload that benefited from setting this
bit, but it seems like a good idea to set it nonetheless.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-05-30 14:59:31 -07:00
Chad Versace 9601b41a33 i965: Fix type of brw_context::render_target_format[]
It's an array of isl_format, not uint32_t. This patch updates every
reference to render_target_format[] git-grep.

Trivial cleanup. No change in behavior.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-05-30 12:01:38 -07:00
Chad Versace 6e325f1203 i965: Move func to right comment block in brw_context.h
brw_init_surface_formats() is defined in brw_surface_formats.c, not
brw_wm_surface_state.c.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-05-30 12:01:38 -07:00
Chad Versace f5702230e0 i965: Document type of GLuint __DRIimage::format
It's either a mesa_format or mesa_array_format.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-05-30 12:01:37 -07:00
Chad Versace da042d951c i965: Add whitespace in intel_update_image_buffers()
Improve readability.  Add an empty line between two large 'if' blocks.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-05-30 12:01:37 -07:00
Chad Versace b86e079ab7 i965: Move an 'i' declaration into its 'for' loop
In intel_update_dri2_buffers().
Trivial cleanup.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-05-30 12:01:37 -07:00
Chad Versace a90a15d638 i965: Fix type of intel_update_image_buffers::format
It's a mesa_format, not an unsigned int.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-05-30 12:01:37 -07:00