swr/rast: fix _simd16_movemask_(ps,pd) native AVX512 intrinsics
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
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@ -539,8 +539,6 @@ INLINE int SIMDAPI _simd16_testz_ps(simd16scalar a, simd16scalar b)
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return lo & hi;
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}
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#define _simd16_cmplt_epi32(a, b) _simd16_cmpgt_epi32(b, a)
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SIMD16_EMU_AVX512_2(simd16scalar, _simd16_unpacklo_ps, _simd_unpacklo_ps)
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SIMD16_EMU_AVX512_2(simd16scalar, _simd16_unpackhi_ps, _simd_unpackhi_ps)
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SIMD16_EMU_AVX512_2(simd16scalard, _simd16_unpacklo_pd, _simd_unpacklo_pd)
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@ -898,12 +896,14 @@ INLINE simd16scalari SIMDAPI _simd16_blendv_epi32(simd16scalari a, simd16scalari
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INLINE simd16mask SIMDAPI _simd16_movemask_ps(simd16scalar a)
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{
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return _simd16_scalari2mask(_mm512_castps_si512(a));
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// movemask_ps only checks the top bit of the float single elements
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return _simd16_scalari2mask(_mm512_and_si512(_mm512_castps_si512(a), _mm512_set1_epi32(0x80000000)));
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}
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INLINE simd16mask SIMDAPI _simd16_movemask_pd(simd16scalard a)
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{
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return _simd16_scalard2mask(a);
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// movemask_pd only checks the top bit of the float double elements
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return _simd16_scalard2mask(_mm512_castsi512_pd(_mm512_and_si512(_mm512_castpd_si512(a), _mm512_set1_epi64(0x8000000000000000))));
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}
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#if 0
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