e29353ff20
radeonsi: don't snoop currently-bound GS shader when compiling ES
...
Instead, pass the layout of GS inputs in memory to the ES using the shader
key. Only 64 bits are needed to represent the layout in the key.
Mixing and matching different VS and GS shaders should now always work.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-24 14:48:02 +02:00
2774abd4ce
radeonsi: shorten si_pipe_* prefixes to si_*
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This was the original naming convention in r600g and it somehow crept
into radeonsi.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-24 14:48:02 +02:00
8c37c16cbc
radeonsi: merge si_pipe_shader into si_shader
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One is part of the other anyway.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-24 14:48:02 +02:00
dba4c5baf4
radeonsi: move DB_SHADER_CONTROL into db_render_state
...
I will need this for fixing sample shading with 1 sample.
The good news is that all shader pm4 states no longer use the current context
state, so we can generate the pm4 states outside of draw_vbo if needed.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-24 14:48:02 +02:00
adc5797f54
radeonsi: set KILL_ENABLE during shader compilation, remove uses_kill flag
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-24 14:48:02 +02:00
a34c9f70b1
radeonsi: remove shader.ps_conservative_z, set db_shader_control instead
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Also set the field on SI too. It's not just specific to CIK.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-24 14:48:02 +02:00
a768b43bc3
radeonsi: remove unused variable si_pipe_shader::sprite_coord_enable
...
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-24 14:48:02 +02:00
b0f780345e
radeonsi/compute: Add support scratch buffer support v2
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The scratch buffer will be used for private memory and also register
spilling.
v2:
- Code cleanups
2014-07-21 10:00:09 -04:00
09056b352d
radeonsi: use an SGPR instead of VGT_INDX_OFFSET
...
The draw indirect packets cannot set VGT_INDX_OFFSET, they can only set user
data SGPRs. This is the only way to support start/index_bias with indirect
drawing.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-07-18 01:58:58 +02:00
6a2b38381e
radeonsi: pass ARB_conservative_depth parameters to the hardware
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-06-19 00:17:36 +02:00
99df120e00
radeonsi: interpolate varyings at sample when full sample shading is enabled
2014-06-02 12:58:22 +02:00
d9e102b220
radeonsi: prepare depth export registers at compile time
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
f8e16010e5
radeonsi: Put GS ring buffer descriptors with streamout buffer descriptors
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And mark the constant buffers as read only for the GPU again.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-01-29 11:09:26 +09:00
8afde9fa23
radeonsi: Take GS into account for VS state in more places
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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-01-29 11:07:35 +09:00
d8b3d806fc
radeonsi: Handle TGSI_SEMANTIC_PRIMID
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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-01-29 11:07:11 +09:00
7c7d7380f1
radeonsi: Generalize counting of shader parameters
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Now it covers ES->GS as well as VS->PS.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-01-29 11:06:58 +09:00
404b29d765
radeonsi: Initial geometry shader support
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Partly based on the corresponding r600g work by Vadim Girlin and Dave
Airlie.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-01-29 11:06:28 +09:00
8662e66bf2
radeonsi: Rename the commonly occurring rctx/r600 variables.
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The "r" stands for R600.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-01-14 00:07:14 +01:00
238aeabce0
radeonsi: Rename r600->si for structs in si_pipe.h.
...
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-01-14 00:07:13 +01:00
786af2f963
radeonsi: Apply si_* file naming scheme.
...
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-01-14 00:07:13 +01:00
Marek Olšák
Tom Stellard
Michel Dänzer
Andreas Hartmetz