radeonsi: Put GS ring buffer descriptors with streamout buffer descriptors
And mark the constant buffers as read only for the GPU again. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Michel Dänzer
Michel Dänzer
parent
d7c68e2dc1
commit
f8e16010e5
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@ -516,7 +516,7 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
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unsigned element_size, unsigned index_stride)
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->const_buffers[shader];
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struct si_buffer_resources *buffers = &sctx->rw_buffers[shader];
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if (shader >= SI_NUM_SHADERS)
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return;
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@ -608,9 +608,9 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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unsigned append_bitmask)
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->streamout_buffers;
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struct si_buffer_resources *buffers = &sctx->rw_buffers[PIPE_SHADER_VERTEX];
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unsigned old_num_targets = sctx->b.streamout.num_targets;
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unsigned i;
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unsigned i, bufidx;
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/* Streamout buffers must be bound in 2 places:
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* 1) in VGT by setting the VGT_STRMOUT registers
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@ -622,12 +622,14 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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/* Set the shader resources.*/
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for (i = 0; i < num_targets; i++) {
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bufidx = SI_RW_SO + i;
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if (targets[i]) {
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struct pipe_resource *buffer = targets[i]->buffer;
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uint64_t va = r600_resource_va(ctx->screen, buffer);
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/* Set the descriptor. */
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uint32_t *desc = buffers->desc_data[i];
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uint32_t *desc = buffers->desc_data[bufidx];
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desc[0] = va;
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desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
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desc[2] = 0xffffffff;
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@ -637,25 +639,29 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
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/* Set the resource. */
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pipe_resource_reference(&buffers->buffers[i], buffer);
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pipe_resource_reference(&buffers->buffers[bufidx],
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buffer);
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r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
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(struct r600_resource*)buffer,
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buffers->shader_usage);
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buffers->desc.enabled_mask |= 1 << i;
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buffers->desc.enabled_mask |= 1 << bufidx;
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} else {
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/* Clear the descriptor and unset the resource. */
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memset(buffers->desc_data[i], 0, sizeof(uint32_t) * 4);
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pipe_resource_reference(&buffers->buffers[i], NULL);
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buffers->desc.enabled_mask &= ~(1 << i);
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memset(buffers->desc_data[bufidx], 0,
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sizeof(uint32_t) * 4);
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pipe_resource_reference(&buffers->buffers[bufidx],
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NULL);
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buffers->desc.enabled_mask &= ~(1 << bufidx);
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}
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buffers->desc.dirty_mask |= 1 << i;
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buffers->desc.dirty_mask |= 1 << bufidx;
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}
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for (; i < old_num_targets; i++) {
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bufidx = SI_RW_SO + i;
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/* Clear the descriptor and unset the resource. */
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memset(buffers->desc_data[i], 0, sizeof(uint32_t) * 4);
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pipe_resource_reference(&buffers->buffers[i], NULL);
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buffers->desc.enabled_mask &= ~(1 << i);
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buffers->desc.dirty_mask |= 1 << i;
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memset(buffers->desc_data[bufidx], 0, sizeof(uint32_t) * 4);
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pipe_resource_reference(&buffers->buffers[bufidx], NULL);
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buffers->desc.enabled_mask &= ~(1 << bufidx);
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buffers->desc.dirty_mask |= 1 << bufidx;
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}
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si_update_descriptors(sctx, &buffers->desc);
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@ -712,25 +718,37 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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/* Vertex buffers. */
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/* Nothing to do. Vertex buffer bindings are updated before every draw call. */
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/* Streamout buffers. */
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for (i = 0; i < sctx->streamout_buffers.num_buffers; i++) {
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if (sctx->streamout_buffers.buffers[i] == buf) {
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/* Update the descriptor. */
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si_desc_reset_buffer_offset(ctx, sctx->streamout_buffers.desc_data[i],
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old_va, buf);
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/* Read/Write buffers. */
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for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
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struct si_buffer_resources *buffers = &sctx->rw_buffers[shader];
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bool found = false;
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uint32_t mask = buffers->desc.enabled_mask;
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r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
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(struct r600_resource*)buf,
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sctx->streamout_buffers.shader_usage);
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sctx->streamout_buffers.desc.dirty_mask |= 1 << i;
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si_update_descriptors(sctx, &sctx->streamout_buffers.desc);
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while (mask) {
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i = u_bit_scan(&mask);
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if (buffers->buffers[i] == buf) {
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si_desc_reset_buffer_offset(ctx, buffers->desc_data[i],
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old_va, buf);
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/* Update the streamout state. */
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if (sctx->b.streamout.begin_emitted) {
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r600_emit_streamout_end(&sctx->b);
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r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
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rbuffer, buffers->shader_usage);
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buffers->desc.dirty_mask |= 1 << i;
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found = true;
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if (i >= SI_RW_SO && shader == PIPE_SHADER_VERTEX) {
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/* Update the streamout state. */
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if (sctx->b.streamout.begin_emitted) {
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r600_emit_streamout_end(&sctx->b);
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}
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sctx->b.streamout.append_bitmask =
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sctx->b.streamout.enabled_mask;
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r600_streamout_buffers_dirty(&sctx->b);
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}
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}
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sctx->b.streamout.append_bitmask = sctx->b.streamout.enabled_mask;
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r600_streamout_buffers_dirty(&sctx->b);
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}
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if (found) {
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si_update_descriptors(sctx, &buffers->desc);
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}
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}
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@ -936,17 +954,20 @@ void si_init_all_descriptors(struct si_context *sctx)
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for (i = 0; i < SI_NUM_SHADERS; i++) {
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si_init_buffer_resources(sctx, &sctx->const_buffers[i],
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NUM_CONST_BUFFERS, i, SI_SGPR_CONST,
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RADEON_USAGE_READ);
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si_init_buffer_resources(sctx, &sctx->rw_buffers[i],
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i == PIPE_SHADER_VERTEX ?
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SI_RW_SO + 4 : SI_RW_SO,
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i, SI_SGPR_RW_BUFFERS,
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RADEON_USAGE_READWRITE);
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si_init_sampler_views(sctx, &sctx->samplers[i].views, i);
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sctx->atoms.const_buffers[i] = &sctx->const_buffers[i].desc.atom;
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sctx->atoms.rw_buffers[i] = &sctx->rw_buffers[i].desc.atom;
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sctx->atoms.sampler_views[i] = &sctx->samplers[i].views.desc.atom;
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}
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si_init_buffer_resources(sctx, &sctx->streamout_buffers, 4, PIPE_SHADER_VERTEX,
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SI_SGPR_SO_BUFFER, RADEON_USAGE_WRITE);
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sctx->atoms.streamout_buffers = &sctx->streamout_buffers.desc.atom;
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/* Set pipe_context functions. */
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sctx->b.b.set_constant_buffer = si_set_constant_buffer;
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@ -961,9 +982,9 @@ void si_release_all_descriptors(struct si_context *sctx)
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for (i = 0; i < SI_NUM_SHADERS; i++) {
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si_release_buffer_resources(&sctx->const_buffers[i]);
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si_release_buffer_resources(&sctx->rw_buffers[i]);
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si_release_sampler_views(&sctx->samplers[i].views);
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}
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si_release_buffer_resources(&sctx->streamout_buffers);
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}
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void si_all_descriptors_begin_new_cs(struct si_context *sctx)
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@ -972,7 +993,7 @@ void si_all_descriptors_begin_new_cs(struct si_context *sctx)
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for (i = 0; i < SI_NUM_SHADERS; i++) {
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si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
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si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers[i]);
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si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
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}
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si_buffer_resources_begin_new_cs(sctx, &sctx->streamout_buffers);
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}
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@ -78,6 +78,8 @@ struct si_surface {
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#define SI_NUM_SHADERS (PIPE_SHADER_GEOMETRY+1)
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#define SI_RW_SO 2 /* Streamout buffer descriptors after ring buffers */
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struct si_context {
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struct r600_common_context b;
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struct blitter_context *blitter;
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@ -93,8 +95,8 @@ struct si_context {
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struct {
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/* The order matters. */
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struct r600_atom *const_buffers[SI_NUM_SHADERS];
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struct r600_atom *rw_buffers[SI_NUM_SHADERS];
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struct r600_atom *sampler_views[SI_NUM_SHADERS];
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struct r600_atom *streamout_buffers;
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/* Caches must be flushed after resource descriptors are
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* updated in memory. */
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struct r600_atom *cache_flush;
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@ -120,7 +122,7 @@ struct si_context {
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unsigned sprite_coord_enable;
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unsigned export_16bpc;
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struct si_buffer_resources const_buffers[SI_NUM_SHADERS];
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struct si_buffer_resources streamout_buffers;
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struct si_buffer_resources rw_buffers[SI_NUM_SHADERS];
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struct si_textures_info samplers[SI_NUM_SHADERS];
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struct r600_resource *border_color_table;
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unsigned border_color_offset;
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@ -319,7 +319,8 @@ static LLVMValueRef fetch_input_gs(
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4);
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/* Load the ESGS ring resource descriptor */
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
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SI_PARAM_RW_BUFFERS);
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t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
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lp_build_const_int32(gallivm, SI_RING_ESGS));
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@ -1202,7 +1203,8 @@ static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
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}
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/* Load the ESGS ring resource descriptor */
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
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SI_PARAM_RW_BUFFERS);
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t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
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lp_build_const_int32(gallivm, SI_RING_ESGS));
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@ -1910,7 +1912,8 @@ static void si_llvm_emit_vertex(
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int i;
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/* Load the GSVS ring resource descriptor */
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
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SI_PARAM_RW_BUFFERS);
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t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
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lp_build_const_int32(gallivm, SI_RING_GSVS));
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@ -2038,7 +2041,7 @@ static void create_function(struct si_shader_context *si_shader_ctx)
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struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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struct si_pipe_shader *shader = si_shader_ctx->shader;
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LLVMTypeRef params[21], f32, i8, i32, v2i32, v3i32;
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LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32;
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unsigned i, last_sgpr, num_params;
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i8 = LLVMInt8TypeInContext(gallivm->context);
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@ -2049,6 +2052,8 @@ static void create_function(struct si_shader_context *si_shader_ctx)
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params[SI_PARAM_CONST] = LLVMPointerType(
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LLVMArrayType(LLVMVectorType(i8, 16), NUM_CONST_BUFFERS), CONST_ADDR_SPACE);
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params[SI_PARAM_RW_BUFFERS] = params[SI_PARAM_CONST];
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/* We assume at most 16 textures per program at the moment.
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* This need probably need to be changed to support bindless textures */
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params[SI_PARAM_SAMPLER] = LLVMPointerType(
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@ -2059,7 +2064,6 @@ static void create_function(struct si_shader_context *si_shader_ctx)
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switch (si_shader_ctx->type) {
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case TGSI_PROCESSOR_VERTEX:
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params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_CONST];
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params[SI_PARAM_SO_BUFFER] = params[SI_PARAM_CONST];
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params[SI_PARAM_START_INSTANCE] = i32;
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num_params = SI_PARAM_START_INSTANCE+1;
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if (shader->key.vs.as_es) {
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@ -2257,12 +2261,13 @@ static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
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return;
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LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
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SI_PARAM_SO_BUFFER);
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SI_PARAM_RW_BUFFERS);
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/* Load the resources, we rely on the code sinking to do the rest */
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for (i = 0; i < 4; ++i) {
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if (si_shader_ctx->shader->selector->so.stride[i]) {
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LLVMValueRef offset = lp_build_const_int32(gallivm, i);
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LLVMValueRef offset = lp_build_const_int32(gallivm,
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SI_RW_SO + i);
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si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
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}
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@ -2371,7 +2376,8 @@ static int si_generate_gs_copy_shader(struct si_context *sctx,
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preload_streamout_buffers(si_shader_ctx);
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/* Load the GSVS ring resource descriptor */
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
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SI_PARAM_RW_BUFFERS);
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t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
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lp_build_const_int32(gallivm, SI_RING_GSVS));
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@ -34,23 +34,23 @@
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#define SI_SGPR_CONST 0
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#define SI_SGPR_SAMPLER 2
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#define SI_SGPR_RESOURCE 4
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#define SI_SGPR_VERTEX_BUFFER 6 /* VS only */
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#define SI_SGPR_SO_BUFFER 8 /* VS only, stream-out */
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#define SI_SGPR_RW_BUFFERS 6 /* rings (& stream-out, VS only) */
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#define SI_SGPR_VERTEX_BUFFER 8 /* VS only */
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#define SI_SGPR_START_INSTANCE 10 /* VS only */
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#define SI_SGPR_ALPHA_REF 6 /* PS only */
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#define SI_SGPR_ALPHA_REF 8 /* PS only */
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#define SI_VS_NUM_USER_SGPR 11
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#define SI_GS_NUM_USER_SGPR 6
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#define SI_PS_NUM_USER_SGPR 7
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#define SI_GS_NUM_USER_SGPR 8
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#define SI_PS_NUM_USER_SGPR 9
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/* LLVM function parameter indices */
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#define SI_PARAM_CONST 0
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#define SI_PARAM_SAMPLER 1
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#define SI_PARAM_RESOURCE 2
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#define SI_PARAM_RW_BUFFERS 3
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/* VS only parameters */
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#define SI_PARAM_VERTEX_BUFFER 3
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#define SI_PARAM_SO_BUFFER 4
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#define SI_PARAM_VERTEX_BUFFER 4
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#define SI_PARAM_START_INSTANCE 5
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/* the other VS parameters are assigned dynamically */
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@ -58,36 +58,38 @@
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#define SI_PARAM_ES2GS_OFFSET 6
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/* GS only parameters */
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#define SI_PARAM_GS2VS_OFFSET 3
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#define SI_PARAM_GS_WAVE_ID 4
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#define SI_PARAM_VTX0_OFFSET 5
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#define SI_PARAM_VTX1_OFFSET 6
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#define SI_PARAM_PRIMITIVE_ID 7
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#define SI_PARAM_VTX2_OFFSET 8
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#define SI_PARAM_VTX3_OFFSET 9
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#define SI_PARAM_VTX4_OFFSET 10
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#define SI_PARAM_VTX5_OFFSET 11
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#define SI_PARAM_GS_INSTANCE_ID 12
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#define SI_PARAM_GS2VS_OFFSET 4
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#define SI_PARAM_GS_WAVE_ID 5
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#define SI_PARAM_VTX0_OFFSET 6
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#define SI_PARAM_VTX1_OFFSET 7
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#define SI_PARAM_PRIMITIVE_ID 8
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#define SI_PARAM_VTX2_OFFSET 9
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#define SI_PARAM_VTX3_OFFSET 10
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#define SI_PARAM_VTX4_OFFSET 11
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#define SI_PARAM_VTX5_OFFSET 12
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#define SI_PARAM_GS_INSTANCE_ID 13
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/* PS only parameters */
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#define SI_PARAM_ALPHA_REF 3
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#define SI_PARAM_PRIM_MASK 4
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#define SI_PARAM_PERSP_SAMPLE 5
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#define SI_PARAM_PERSP_CENTER 6
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#define SI_PARAM_PERSP_CENTROID 7
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#define SI_PARAM_PERSP_PULL_MODEL 8
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#define SI_PARAM_LINEAR_SAMPLE 9
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#define SI_PARAM_LINEAR_CENTER 10
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#define SI_PARAM_LINEAR_CENTROID 11
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#define SI_PARAM_LINE_STIPPLE_TEX 12
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#define SI_PARAM_POS_X_FLOAT 13
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#define SI_PARAM_POS_Y_FLOAT 14
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#define SI_PARAM_POS_Z_FLOAT 15
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#define SI_PARAM_POS_W_FLOAT 16
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#define SI_PARAM_FRONT_FACE 17
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#define SI_PARAM_ANCILLARY 18
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#define SI_PARAM_SAMPLE_COVERAGE 19
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#define SI_PARAM_POS_FIXED_PT 20
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||||
#define SI_PARAM_ALPHA_REF 4
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#define SI_PARAM_PRIM_MASK 5
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#define SI_PARAM_PERSP_SAMPLE 6
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#define SI_PARAM_PERSP_CENTER 7
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||||
#define SI_PARAM_PERSP_CENTROID 8
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||||
#define SI_PARAM_PERSP_PULL_MODEL 9
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||||
#define SI_PARAM_LINEAR_SAMPLE 10
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||||
#define SI_PARAM_LINEAR_CENTER 11
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||||
#define SI_PARAM_LINEAR_CENTROID 12
|
||||
#define SI_PARAM_LINE_STIPPLE_TEX 13
|
||||
#define SI_PARAM_POS_X_FLOAT 14
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||||
#define SI_PARAM_POS_Y_FLOAT 15
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||||
#define SI_PARAM_POS_Z_FLOAT 16
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||||
#define SI_PARAM_POS_W_FLOAT 17
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||||
#define SI_PARAM_FRONT_FACE 18
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||||
#define SI_PARAM_ANCILLARY 19
|
||||
#define SI_PARAM_SAMPLE_COVERAGE 20
|
||||
#define SI_PARAM_POS_FIXED_PT 21
|
||||
|
||||
#define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 1)
|
||||
|
||||
struct si_shader_input {
|
||||
unsigned name;
|
||||
|
|
|
|||
|
|
@ -115,10 +115,10 @@ union si_state {
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|||
#define NUM_SAMPLER_STATES NUM_TEX_UNITS
|
||||
|
||||
#define NUM_PIPE_CONST_BUFFERS 16
|
||||
#define SI_RING_ESGS 17
|
||||
#define SI_RING_GSVS 18
|
||||
#define NUM_CONST_BUFFERS (SI_RING_GSVS + 1)
|
||||
#define NUM_CONST_BUFFERS (NUM_PIPE_CONST_BUFFERS + 1)
|
||||
|
||||
#define SI_RING_ESGS 0
|
||||
#define SI_RING_GSVS 1
|
||||
|
||||
/* This represents resource descriptors in memory, such as buffer resources,
|
||||
* image resources, and sampler states.
|
||||
|
|
|
|||
Loading…
Reference in New Issue