e0c2a4d58c
radeonsi/gfx10: implement si_shader_gs
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This is only used in the legacy, non-NGG path.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
2864d53deb
radeonsi/gfx10: implement preload_ring_buffers
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
56cab3e996
radeonsi/gfx10: implement si_set_ring_buffer
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
3c1aeb834f
radeonsi/gfx10: allow rectangle outputs from NGG primitive shader
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
77e715541c
radeonsi/gfx10: emit VGT_GS_OUT_PRIM_TYPE from draw and add it to VS_STATE
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With NGG, the VGT_GS_OUT_PRIM_TYPE can change without a shader change.
The VS_STATE is required for both streamout and culling from a vertex
shader without pre-compiling outprim-specific variants.
We could consider compiling specialized variants in the future. We
could also consider compiling the NGG logic as an epilog.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
4ecc39e1aa
radeonsi/gfx10: NGG geometry shader PM4 and upload
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
a04aa4be2b
radeonsi/gfx10: generate geometry shaders for NGG
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
efe1cd4859
radeonsi/gfx10: use the correct register for image descriptor dumping
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
1ce52c1e37
radeonsi/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy mode
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
77c0f9e7ba
radeonsi/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSET
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
47c9505a92
radeonsi/gfx10: setup registers for OpenGL compute
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
b8d3fd46d6
radeonsi/gfx10: set user data base registers
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
016a465d7d
radeonsi/gfx10: implement gfx10_shader_ngg
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For pipelines without API GS. We will later expand this to cover NGG
geometry shaders as well.
Note that the vtx offset passed into the GS part is just the
vertex index multiplied by VGT_ESGS_RING_ITEMSIZE.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
d0c204a1e0
radeonsi/gfx10: add NGG registers to si_init_config
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
ae00cae0b7
radeonsi/gfx10: update shader-related fields in si_init_config
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
1dee01ee13
radeonsi/gfx10: implement si_shader_ps
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
612489bd5d
radeonsi/gfx10: generate VS and TES as NGG merged ESGS shaders
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This does not support geometry shading yet. Also missing are streamout
and NGG-specific optimizations.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
e86256c512
radeonsi/gfx10: distinguish between merged shaders and multi-part shaders
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
4063ea95e9
radeonsi/gfx10: update si_get_shader_name
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
8ec60d3031
radeonsi/gfx10: add as_ngg shader key bit
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Also add the shader main part NGG variant, so that in principle
we can switch between legacy in NGG modes.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
40b12c0f5a
radeonsi/gfx10: implement si_update_shaders
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
5726ec0d24
radeonsi/gfx10: implement si_build_vgt_shader_config
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
b45c3debe8
radeonsi/gfx10: keep track of whether NGG is used
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We always use NGG by default, except when tessellation is enabled with
extreme geometry shader amplification.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
226f650d92
radeonsi/gfx10: document NGG shader stages
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
7bb9bb0540
radeonsi/gfx10: implement gfx10_emit_cache_flush
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
0c6c6810bd
radeonsi/gfx10: add si_context::emit_cache_flush
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The introduction of GCR_CNTL makes cache flush handling on gfx10
sufficiently different that it makes sense to just use a separate
function.
Since emit_cache_flush is called quite early during context init,
we initialize the pointer explicitly in si_create_context.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
08e2a62b07
radeonsi/gfx10: implement DB registers
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
372652bccc
radeonsi/gfx10: set CB registers
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
44adae42ae
radeonsi/gfx10: always set up sample locations
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
79b1eaf2fd
radeonsi/gfx10: use Z32_FLOAT_CLAMP for upgraded depth textures
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
c049a6f895
radeonsi/gfx10: implement vertex format changes
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
62f73d8214
radeonsi/gfx10: implement si_set_{constant,shader}_buffer
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
21ac1da0d1
radeonsi/gfx10: implement si_make_buffer_descriptor
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
7bc818aef1
radeonsi/gfx10: implement si_set_mutable_tex_desc_fields
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
8598a999ea
radeonsi/gfx10: gfx10 can render up to 8192 layers
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
3f2b2b52d0
radeonsi/gfx10: add gfx10_make_texture_descriptor
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
595a7f7c47
radeonsi/gfx10: add pipe_screen::make_texture_descriptor
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Texture descriptors in gfx10 are very different.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
4afce5efdd
radeonsi/gfx10: determine view->is_integer based on the pipe_format
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It was convenient, but NUM_FORMAT no longer exists in gfx10.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
3163db3ba4
radeonsi/gfx10: implement si_is_format_supported
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
0ffa2292b3
radeonsi/gfx10: generate gfx10_format_table.h
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
af29ad7cc6
radeonsi/gfx10: set MAX_ALLOC_COUNT
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The number for Vega was copied from PAL and has no effect because of MIN2.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
594010e366
radeonsi/gfx10: require LLVM 9
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
de99e0a563
radeon/vcn: update for new vcn enc interface
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
9ab1e427bb
radeonsi: enable jpeg decode for navi10
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
6480c7b577
radeon/vcn: implement vcn 2.0 jpeg decode
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Use direct register to implement vcn 2.0 jpeg deocde
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
0cd7953ece
radeon/vcn: add direct register bool
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VCN 2.0 uses direct register space where VCN 1.0 uses some indirect registers
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
7a5c22d32a
radeon/vcn: add defines for vcn 2.0 jpeg
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Add neccesary register defines for vcn 2.0 jpeg deocde
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
0c27971157
radeon/vcn: use variable to assign ib cmd
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
587b9c5dae
radeon/vcn: implement vcn 2.0 encode
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
40e1bed389
radeon/vcn: add vcn2.0 encode skeleton
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
(v2: build fix -- Nicolai)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
Nicolai Hähnle
Boyuan Zhang