Commit Graph

632 Commits

Author SHA1 Message Date
Samuel Pitoiset fe57fe1fd8 ac/nir/ngg: count the number of generated primitives for VS and TES
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>
2022-06-09 08:02:39 +00:00
Georg Lehmann 5ebb014bdf radv, aco: Round texture array layer in NIR.
Foz-DB Navi21:
Totals from 9100 (6.75% of 134913) affected shaders:
VGPRs: 609912 -> 610104 (+0.03%); split: -0.01%, +0.05%
SpillSGPRs: 1459 -> 1489 (+2.06%)
CodeSize: 66705920 -> 66620288 (-0.13%); split: -0.13%, +0.00%
MaxWaves: 148546 -> 148518 (-0.02%); split: +0.00%, -0.02%
Instrs: 12278485 -> 12255821 (-0.18%); split: -0.19%, +0.00%
Latency: 277414916 -> 277261192 (-0.06%); split: -0.08%, +0.02%
InvThroughput: 48431180 -> 48394637 (-0.08%); split: -0.11%, +0.03%
VClause: 250866 -> 251062 (+0.08%); split: -0.04%, +0.11%
SClause: 498377 -> 498173 (-0.04%); split: -0.08%, +0.04%
Copies: 652835 -> 655371 (+0.39%); split: -0.09%, +0.48%
Branches: 284367 -> 284371 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 498580 -> 498477 (-0.02%)
PreVGPRs: 558436 -> 558709 (+0.05%); split: -0.01%, +0.06%

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16871>
2022-06-08 20:57:22 +00:00
Konstantin Seurer d5dd0df65f radv: ray cull mask
Lower the cull_mask system value to rt variable
load and advertise the corresponding capability.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16430>
2022-06-08 20:20:21 +00:00
Timur Kristóf 0280b526d5 radv: Implement mesh shader scratch ring.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Timur Kristóf b664279755 ac/nir/ngg: Use mesh shader scratch ring when outputs don't fit LDS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Timur Kristóf ac5ab8d227 ac: Add task shader ring information.
Similarly to tessellation rings information, move the task
rings info to ac_gpu_info.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Georg Lehmann d8493e5310 radv, aco: Lower txf offset in NIR.
Foz-DB Navi21:
Totals from 384 (0.28% of 134913) affected shaders:
VGPRs: 29736 -> 29536 (-0.67%)
CodeSize: 2455796 -> 2452652 (-0.13%); split: -0.13%, +0.01%
MaxWaves: 6350 -> 6358 (+0.13%)
Instrs: 457743 -> 456273 (-0.32%); split: -0.33%, +0.01%
Latency: 6680266 -> 6730612 (+0.75%); split: -0.03%, +0.78%
InvThroughput: 1562936 -> 1599375 (+2.33%); split: -0.05%, +2.38%
VClause: 9258 -> 9291 (+0.36%); split: -0.14%, +0.50%
SClause: 15713 -> 15707 (-0.04%); split: -0.08%, +0.04%
Copies: 26878 -> 27021 (+0.53%); split: -0.03%, +0.56%
PreVGPRs: 27259 -> 27230 (-0.11%); split: -0.11%, +0.01%

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16869>
2022-06-08 08:13:01 +00:00
Timur Kristóf f7f2770e72 ac/nir: Add remappability to tess and ESGS I/O lowering passes.
This will be used for radeonsi to map common I/O location to fixed
slots agreed by different shader stages.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Qiang Yu 6a95452ddf ac/nir: use nir_intrinsic_load_lshs_vertex_stride_amd
For radeonsi which pass this value by argument.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Samuel Pitoiset 5af1409c1b radv: fix lowering GS intrinsics if NGG is disabled per pipeline
If NGG is disabled per pipeline for extreme (or suboptimal) geometry
or with transform feedback, make sure to not lower GS intrinsics that
are only needed for NGG GS. This means we have to lower GS intrinsics
later in the compilation process to effectively know if the pipeline
uses NGG.

fossils-db (Navi21):
Totals from 8 (0.01% of 134913) affected shaders:
VGPRs: 512 -> 520 (+1.56%)
CodeSize: 58180 -> 65080 (+11.86%); split: -0.04%, +11.90%
MaxWaves: 128 -> 126 (-1.56%)
Instrs: 10525 -> 11779 (+11.91%); split: -0.05%, +11.96%
Latency: 62941 -> 49428 (-21.47%); split: -21.59%, +0.12%
InvThroughput: 16121 -> 12950 (-19.67%); split: -19.96%, +0.29%
VClause: 122 -> 123 (+0.82%); split: -0.82%, +1.64%
SClause: 130 -> 143 (+10.00%)
Copies: 566 -> 596 (+5.30%); split: -0.35%, +5.65%
Branches: 200 -> 208 (+4.00%)
PreSGPRs: 424 -> 422 (-0.47%)
PreVGPRs: 430 -> 424 (-1.40%); split: -1.63%, +0.23%

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15885>
2022-06-02 09:42:54 +02:00
Georg Lehmann aa9d2d8893 radv: Enable VK_INTEL_shader_integer_functions2.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 4e6667ea87 radv: Lower hadd/hradd.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann cc3f03b757 radv: Lower mul_32x16.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Jason Ekstrand 7003ff2e3a radv: Use nir_gather_xfb_info
Instead of gathering XFB info over and over again every time we even
want to know if the shader uses XFB, gather it once when we compile the
shader and refer to the copy in the NIR.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16750>
2022-05-31 23:09:30 +00:00
Timur Kristóf c69b771e35 radv, ac/nir: Fix multiview layer export for mesh shaders.
Unfortunately, radv_lower_multiview is not suitable for mesh shaders
because it can't know the mapping between API mesh shader
invocations and output primitives.

Additionally, when lowering view id to layer, it must be created
as a per-primitive PS input.

Fixes: d32656bc65
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16504>
2022-05-31 07:58:29 +00:00
Samuel Pitoiset f7b1ad7c06 radv: update VRS rates on GFX11
GFX11 uses enum instead of 2-bit integer numbers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
iReviewed-by: Timur Kristóf <timur.kristof@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset 35af86af8c radv: move HS info and task_num_entries to the physical device
They are not logical device properties.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>
2022-05-25 11:39:20 +00:00
Samuel Pitoiset fc3717df0c radv: cleanup using device/physical_device during pipeline creation
This removes a TON of pipeline->device occurences which were a mess.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16603>
2022-05-23 07:32:56 +00:00
Rhys Perry 75c80be484 radv: add missing NIR_PASS() and switch from NIR_PASS_V()
Unlike NIR_PASS_V(), NIR_PASS() can skip printing the shader when
NIR_DEBUG=print.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5244
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
2022-05-19 13:37:20 +00:00
Rhys Perry d98b7817fc radv: call nir_metadata_preserve in various lowering passes
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
2022-05-19 13:37:20 +00:00
Marek Olšák 2443054932 amd: rename fishes to Navi21, Navi22, Navi23, Navi24, and Rembrandt
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16604>
2022-05-19 11:55:50 +00:00
Samuel Pitoiset 8e1085c19a radv: do not try to dump the NIR of the trap handler shader
There is no NIR at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16553>
2022-05-18 07:19:20 +00:00
Samuel Pitoiset 9207d791af radv: rename shader compile functions to spirv_to_nir/nir_to_asm
For better clarity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16553>
2022-05-18 07:19:20 +00:00
Samuel Pitoiset 2d02e210b5 radv: do not align VGPRS to 8 or 16 on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
2022-05-17 10:08:17 +00:00
Dave Airlie a179e1aede aco/radv: drop radv_nir_compiler_options from aco.
Add a new aco input and options structs, then convert from radv
pieces on submit.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
2022-05-17 06:15:25 +00:00
Dave Airlie 8198900071 ac/radv: drop info pointer from the ac and radv shader structs
This was being used for one bool, just pass the bool.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
2022-05-17 06:15:25 +00:00
Marek Olšák 39800f0fa3 amd: change chip_class naming to "enum amd_gfx_level gfx_level"
This aligns the naming with PAL.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>
2022-05-13 14:56:22 -04:00
Samuel Pitoiset 42ef89e8db radv,aco: use the new TCS WaveID SGPR to compute vs_rel_patch_id on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16369>
2022-05-12 15:46:20 +00:00
Timur Kristóf 0d0165db8e radv: Print task shader stage name before disasm.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
2022-05-12 00:29:51 +00:00
Timur Kristóf 8dbde92659 radv: Lower shared and task_payload variables in task/mesh shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
2022-05-12 00:29:51 +00:00
Timur Kristóf 73c260594f radv: Postprocess task shader configuration.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
2022-05-12 00:29:51 +00:00
Timur Kristóf c17c523ec0 radv: Use I/O lowering for task and mesh shaders.
We set the number of task shader ring entries in radv_device
based on the generous assumption that each CU can run task/mesh
shaders with maximum occupancy.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
2022-05-12 00:29:51 +00:00
Timur Kristóf 101a7321c4 radv: Fill task shader info.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
2022-05-12 00:29:51 +00:00
Dave Airlie c44d5d61ce aco: remove radv vs prolog key from aco internals.
This creates an aco specific key, and converts radv to it.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
2022-05-11 19:07:11 +00:00
Dave Airlie 04c07a2413 aco/radv: convert to aco shader info at the radv level.
This removes the radv shader info type from aco completely.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
2022-05-11 19:07:11 +00:00
Daniel Schürmann 4875c82d2d radv: call nir_lower_vars_to_ssa later
Totals from 599 (0.44% of 134913) affected shaders: (GFX10.3)
CodeSize: 1243732 -> 1240512 (-0.26%); split: -0.26%, +0.00%
Instrs: 223370 -> 222702 (-0.30%); split: -0.30%, +0.00%
Latency: 901762 -> 885446 (-1.81%); split: -1.81%, +0.00%
InvThroughput: 305546 -> 305536 (-0.00%)
SClause: 12690 -> 12554 (-1.07%); split: -1.13%, +0.06%
Copies: 23779 -> 23778 (-0.00%)
PreSGPRs: 17781 -> 17829 (+0.27%)

Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5668>
2022-05-10 22:20:54 +00:00
Daniel Schürmann f8ee0efd04 radv: move two NIR passes out of tight optimization loop
nir_remove_dead_variables
nir_opt_shrink_vectors

Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5668>
2022-05-10 22:20:54 +00:00
Timur Kristóf 212f183c1f ac/nir: Remove now-superfluous ac_nir_lower_tess_to_const.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13155>
2022-05-10 17:16:03 +00:00
Rhys Perry 8a525c0fa5 radv: consider radix sort shaders to be internal/meta
Cleans up RADV_DEBUG=shaders

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16198>
2022-05-02 10:19:23 +00:00
Emma Anholt 536c8ee96d nir/lower_tex: Make the adding a 0 LOD to nir_op_tex in the VS optional.
This controls the whole lowering of "make tex ops with implicit
derivatives on non-implicit-derivative stages be tex ops with an explicit
lod of 0 instead", but it's really hard to describe that in a git commit
summary.

All existing callers get it added except:
- nir_to_tgsi which didn't want it.
- nouveau, which didn't want it (fixes regressions in shadowcube and
  shadow2darray with NIR, since the shading languages don't expose txl of
  those sampler types and thus it's not supported in HW)
- optional lowering passes in mesa/st (lower_rect, YUV lowering, etc)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16156>
2022-04-28 21:26:08 +00:00
Konstantin Seurer 324b2ae5f2 radv: Enable rt primitive culling for spirv2nir
Fixes: c8fe408fcc ("radv: Advertise ray primitive culling")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16028>
2022-04-20 11:38:52 +00:00
Rhys Perry 75e68f44af radv: always use nir_lower_io_lower_64bit_to_32
Our I/O lowering doesn't handle 64-bit TCS stores and TES loads which use
several slots. Because of the large stride between slots, we have to split
the load so that there's a single load_buffer_amd/store_buffer_amd
intrinsic for each slot.

Our I/O lowering also sometimes creates nir_op_pack_64_2x32 after
nir_lower_alu_to_scalar.

Fixes KHR-GL45.gpu_shader_fp64.fp64.varyings with Zink
(https://gitlab.freedesktop.org/mesa/mesa/-/issues/6276)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15863>
2022-04-16 11:19:11 +00:00
Rhys Perry b62e90ad43 radv: use nir_op_imm helpers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15854>
2022-04-15 23:56:11 +00:00
Rhys Perry 8e0e98a9af radv: initialize meta shader options earlier
We might need this for NIR builders.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15854>
2022-04-15 23:56:11 +00:00
Samuel Pitoiset 2591a52560 radv: fix enabling adjust_frag_coord_z and apply per-pipeline
Fossilize always enables all supported extensions, that means that
adjust_frag_coord_z would always be enabled on RDNA2, even if the
application doesn't enable it. The pipeline key would then be different
and precompilation wouldn't work. Move this per-pipeline since we can
know if VRS will be used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15444>
2022-04-15 05:49:54 +00:00
Timur Kristóf 394b93bfeb radv: Only use TES vertex offset 2 for triangles and quads.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15837>
2022-04-13 15:04:26 +00:00
Timur Kristóf e02c71d6c5 radv: Fix gs_vgpr_comp_cnt for NGG VS without passthrough mode.
When not in passthrough mode, the NGG shader needs to calculate the
primitive export value from the input primitive's vertex indices.

So, GS vertex offset 2 is needed when NGG has triangles
and isn't in passthrough mode.

Fixes: 7ad69e2f7e "radv: stop loading invocation ID for NGG vertex shaders"
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15837>
2022-04-13 15:04:26 +00:00
Rhys Perry 7f6262bb85 radv: allow holes in inline push constants
Use a dword mask instead of a range to track which push constants to
inline.

fossil-db (Sienna Cichlid):
Totals from 5724 (4.25% of 134621) affected shaders:
CodeSize: 20894044 -> 20815748 (-0.37%); split: -0.39%, +0.02%
Instrs: 4002568 -> 3988385 (-0.35%); split: -0.38%, +0.02%
Latency: 29285060 -> 29224414 (-0.21%); split: -0.22%, +0.01%
InvThroughput: 5529700 -> 5526893 (-0.05%); split: -0.05%, +0.00%
VClause: 78093 -> 78240 (+0.19%); split: -0.23%, +0.41%
SClause: 135495 -> 131027 (-3.30%); split: -3.30%, +0.00%
Copies: 330856 -> 324552 (-1.91%); split: -2.37%, +0.46%
PreSGPRs: 226031 -> 224778 (-0.55%); split: -0.61%, +0.05%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12145>
2022-04-12 11:44:30 +00:00
Samuel Pitoiset dca28a6355 radv: drop the remaining uses of shader modules
With VK_EXT_graphics_pipeline_library, shader modules can be NULL and
be passed via the pNext of VkPipelineShaderStageCreateInfo. To prepare
for this, just store everything we need to radv_pipeline_stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15847>
2022-04-12 06:13:24 +00:00
Samuel Pitoiset a652c1653a radv: introduce new radv_pipeline_stage structure
This is used to store everything for a pipeline stage like the module,
the NIR, the shader arguments etc. This is inspired from ANV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15794>
2022-04-08 16:38:30 +00:00