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radv: always use nir_lower_io_lower_64bit_to_32 

Our I/O lowering doesn't handle 64-bit TCS stores and TES loads which use
several slots. Because of the large stride between slots, we have to split
the load so that there's a single load_buffer_amd/store_buffer_amd
intrinsic for each slot.

Our I/O lowering also sometimes creates nir_op_pack_64_2x32 after
nir_lower_alu_to_scalar.

Fixes KHR-GL45.gpu_shader_fp64.fp64.varyings with Zink
(https://gitlab.freedesktop.org/mesa/mesa/-/issues/6276)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15863>
This commit is contained in:
Rhys Perry 2022-04-08 19:29:22 +01:00 committed by Marge Bot
parent ab1409010a
commit 75e68f44af
2 changed files with 2 additions and 6 deletions
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7
src/amd/vulkan/radv_shader.c
View File

@ -986,11 +986,8 @@ radv_lower_io(struct radv_device *device, nir_shader *nir)
nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs, MESA_SHADER_FRAGMENT);
}
/* The RADV/LLVM backend expects 64-bit IO to be lowered. */
nir_lower_io_options options =
radv_use_llvm_for_stage(device, nir->info.stage) ? nir_lower_io_lower_64bit_to_32 : 0;
NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out, type_size_vec4, options);
NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out, type_size_vec4,
nir_lower_io_lower_64bit_to_32);
/* This pass needs actual constants */
nir_opt_constant_folding(nir);

1
src/gallium/drivers/zink/ci/zink-radv-fails.txt
View File

@ -1,5 +1,4 @@
# probable ACO bug: #6276
KHR-GL46.gpu_shader_fp64.fp64.varyings,Fail
KHR-GL46.shader_image_load_store.basic-allTargets-atomicCS,Fail
KHR-GL46.shader_image_load_store.basic-allTargets-atomicGS,Fail
KHR-GL46.shader_image_load_store.basic-allTargets-atomicVS,Fail