Commit Graph

88748 Commits

Author SHA1 Message Date
Edward O'Callaghan d77fa310ed ilo: EOL drop unmaintained gallium drv from buildsys
This is no longer actively maintained and is just
accumulating bitrot.

Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Acked-by: Chia-I Wu <olvaffe@gmail.com>
2017-02-03 16:13:36 +11:00
Edward O'Callaghan 01b625ef1a ilo: EOL unplumb unmaintained gallium drv from winsys
This is no longer actively maintained and is just
accumulating bitrot.

Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Acked-by: Chia-I Wu <olvaffe@gmail.com>
2017-02-03 16:13:32 +11:00
Ilia Mirkin 2b4eaabff0 configure: libdrm is a single package
The intent of the libdrm_$driver version limits has always been to not
burden the "other" drivers with updating their libdrm unless really
necessary. Unfortunately the configure script erroneously only checked
the driver-specific bit and not the generic bit of libdrm as well. Fix
this.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-02-02 20:36:09 -05:00
Ilia Mirkin 7d3f9ed71c st/mesa: MAX_VARYING is the max supported number of patch varyings, not min
This fixes
GL45-CTS.tessellation_shader.tessellation_shader_tessellation.max_in_out_attributes
on nouveau. We only support 30 patch varyings (as 2 vec4 slots end up
being used for tess level settings), but were getting 32 exposed.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-02-02 20:28:58 -05:00
Ilia Mirkin e73f87fcbd vbo: process buffer binding state changes on draw when recording
The VBO module keeps track of any vbo buffers. It updates this list when
receiving an InvalidateState call, however this never happens when
recording draws right now. Make sure that we do all the usual state
updates when recording draws so that the VBO list may be kept up to
date.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99631
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-02-02 20:28:27 -05:00
Dave Airlie 6cc3c46f58 radv/ac: move to using shared emit_ddxy code.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-03 09:54:04 +10:00
Dave Airlie c9a2fc3679 radeonsi/ac: move most of emit_ddxy to shared code.
We can reuse this in radv.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-03 09:54:04 +10:00
Dave Airlie 278d5ef70a radv/ac: use shared thread id code
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-03 09:54:04 +10:00
Dave Airlie c5f0a56aeb radeonsi/ac: move get thread id to shared code.
radv will use this.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-03 09:54:04 +10:00
Dave Airlie 1c5c268a8a radv/ac: migrate to using shared code for some load/store stuff.
This migrates to the code shared with radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-03 09:54:04 +10:00
Dave Airlie b3c28942c7 radeonsi/ac: move tbuffer store and buffer load to shared code.
These are all reuseable by radv.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-03 09:54:04 +10:00
Dave Airlie a9773311f6 radeonsi/ac: move a bunch of load/store related things to common code.
These are all shareable with radv, so start migrating them to the
common code.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-03 09:54:04 +10:00
Eduardo Lima Mitev e198a64e35 texgetimage: Add check for the effective target to GetTextureSubImage
OpenGL 4.5 spec, section "8.11.4 Texture Image Queries", page 233 of
the PDF states:

    "An INVALID_OPERATION error is generated if texture is the name of a buffer
     or multisample texture."

This is currently not being checked and e.g a multisample texture image can
be passed down to the driver hook. On i965, it is crashing the driver with an
assertion:

intel_mipmap_tree.c:3125: intel_miptree_map: Assertion `mt->num_samples <= 1' failed.

v2: (Ilia Mirkin) Move the check from gettextimage_error_check() to
    GetTextureSubImage() and use the texObj target.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-02-03 00:43:46 +01:00
Marek Olšák dfe111368d Revert "radeonsi: decrease the number of texture slots to 24"
This reverts commit bdd860e307.

Requested by a game developer.

Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-02-03 00:39:48 +01:00
Dave Airlie b457f67495 configure.ac: explicitly require libdrm for dri classic drivers.
Although this might come from somewhere else require it explicitly.

Reviewed-by: Chad Versace <chadversary@chromium.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-03 09:38:15 +10:00
Jason Ekstrand 37a6f48ceb intel/isl: Add a better comment for format_supports_ccs_e
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand 45b3eb4dfc anv: Remove the finishme for CCS_E with storage images
The data port can't handle CCS at all so replace the finishme with
better comments.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand fc9f0db8e3 intel/isl: Assert that we don't use CCS for storage images
I enabled CCS for storage images in the Vulkan driver and ran it through
the CTS.  It didn't result in any hangs but it demonstrated that the data
port cannot handle CCS.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand 7e6a9d9c4b intel/isl: Add a formats_are_ccs_e_compatible helper
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand 6142e3c07c intel/isl: Add a format_supports_ccs_d helper
Nothing uses this yet but it serves as a nice bit of documentation
that's relatively easy to find.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand ab06fc6684 intel/isl: Rename supports_lossless_compression to supports_ccs_e
The term "lossless compression" could potentially mean multisample
color compression, single-sample color compression or HiZ because they
are all lossless.  The term CCS_E, however, has a very precise meaning;
in ISL and is only used to refer to single-sample color compression.
It's also much shorter which is nice.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2017-02-02 13:33:43 -08:00
Nanley Chery 043d92fef9 anv/pass: Store the depth-stencil attachment's last subpass index
Commit 968ffd6c86 stored the last subpass
index of all the attachments but that of the depth-stencil attachment.
This could cause depth buffers used in multiple subpasses not to be in
the requested final layout. Fix this error.

Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2017-02-02 10:36:14 -08:00
Nicolai Hähnle a020cb3a72 gallium: turn PIPE_SHADER_CAP_DOUBLES into a screen capability
Make the cap consistent with PIPE_CAP_INT64.

Aside from the hypothetical case of using draw for vertex shaders (and
actually caring about doubles...), every implementation supports doubles
either nowhere or everywhere.

Also, st/mesa didn't even check the cap correctly in all supported
shader stages.

While at it, add a missing LLVM version check for 64-bit integers in
radeonsi. This is conservative: judging by the log, LLVM 3.8 might be
sufficient, but there are probably bugs that have been fixed since then.

v2: fix clover (Marek)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-02-02 16:53:42 +01:00
Plamena Manolova 96123dbad9 mesa: Enable EXT_compressed_ETC1_RGB8_sub_texture
Since we already have the functionality in place and games
like Game of Thrones seem to depend on this extension, I
think it makes sense to enable it by making it part of
the extension string even though it's still a draft:

https://www.khronos.org/registry/gles/extensions/EXT/EXT_compressed_ETC1_RGB8_sub_texture.txt

Note: OES_compressed_ETC1_RGB8_sub_texture seems to be listed
in gl2ext.h, but there's no documentation for it in the KHR
registry

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-02-02 12:28:31 +00:00
Vinson Lee 6ee4665a77 configure: Only require libdrm 2.4.75 for intel.
Fixes: b8acb6b179 ("configure: Require libdrm >= 2.4.75")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Acked-by: Dave Airlie <airlied@redhat.com>
2017-02-02 13:10:00 +10:00
Lionel Landwerlin 7158255069 anv: enable VK_KHR_shader_draw_parameters
Enables 10 tests from:

   dEQP-VK.draw.shader_draw_parameters.*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-02-02 01:33:16 +00:00
Lionel Landwerlin 9413e11869 anv: emit DrawID if needed
v2: use define for buffer ID (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-02-02 01:33:06 +00:00
Lionel Landwerlin 543d5db4e2 anv: always allocate a vertex element with vertexid or instanceid
Up to now on Gen8+ we only allocated a vertex element for
gl_InstanceIndex or gl_VertexIndex when a vertex shader uses
gl_BaseInstanceARB or gl_BaseVertexARB. This is because we would
configure the VF_SGVS packet to make the VF unit write the
gl_InstanceIndex & gl_VertexIndex values right behind the values
computed from the vertex buffers.

In the next commit we will also write the gl_DrawIDARB value. Our
backend expects to pull the gl_DrawIDARB value from the element
following the element containing gl_InstanceIndex, gl_VertexIndex,
gl_BaseInstanceARB and gl_BaseVertexARB (see
vec4_vs_visitor::setup_attributes). Therefore we need to allocate an
element for the SGVS elements as long as at least one of the SGVS
element is read by the shader. Otherwise our shader will use a
gl_DrawIDARB value pulled from the URB one element too far (most
likely garbage).

v2: Fix my english (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-02-02 01:32:58 +00:00
Lionel Landwerlin 289aef771d anv: move BaseVertexID/BaseInstanceID vertex buffer index to 31
v2: use define for buffer ID (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-02-02 01:32:48 +00:00
Lionel Landwerlin 98cf60a3ce anv: limit vertex buffers to 31
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-02-02 01:32:39 +00:00
Mauro Rossi 9c45bb731c android: fix llvm, elf dependencies for M, N releases
These changes set the correct llvm version and elf include path
which differ for Marshmallow and Nougat

Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2017-02-01 23:01:35 +00:00
Jason Ekstrand ccdd5b3738 anv: Don't use bogus alpha swizzles
For RGB formats in Vulkan, we use the corresponding RGBA format with a
swizzle of RGB1.  While this swizzle is exactly what we want for
texturing, it's not allowed for rendering according to the docs.  While
we haven't been getting hangs or anything, we should probably obey the
docs.  This commit just sanitizes all render swizzles so that the alpha
channel maps to ALPHA.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-01 14:41:06 -08:00
Micah Fedke 752ae38a09 Add missing copyright header to wayland-egl-priv.h
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-02-01 22:33:40 +00:00
Dave Airlie cda9f3d8ec radv: handle VK_QUEUE_FAMILY_IGNORED in image transitions (v3)
The CTS tests at least are using this, and we were totally
ignoring it.

This hopefully fixes the bouncing multisample CTS tests.

v2: get family mask in ignored case from command buffer.
v3: only change things in one place, use logic from Bas.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-02 08:25:04 +10:00
Dave Airlie fa316ed02f radv/ac: handle clip/cull distance sizing in geometry shader outputs
Otherwise we were writing these as 4 components, and things went bad.

Fixes (the remaining):
dEQP-VK.clipping.user_defined.*.vert_geom.*

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-02 08:25:04 +10:00
Dave Airlie 230e308ff9 radv/ac: add const_index to fetch index for gs inputs
This fixes clip distance fetches as they are single item loads
with a const_index like float[1].

Fixes:
dEQP-VK.clipping.user_defined.*.vert_geom.[0-6]

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-02 08:25:04 +10:00
Dave Airlie dc68b920df radeonsi/ac: move frag interp emission code to shared llvm code.
This code should be used in radv, so move it to a shared location
in advance of doing that.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-02 08:24:53 +10:00
Timothy Arceri b940b2fd16 st/mesa: inline get_mesa_program()
In the past I've gotten this function confused with the one in
ir_to_mesa.cpp of the same name. Now that the affected flag setting
has move into a helper it makes sense just to inline this remaining
code.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-02-02 08:31:28 +11:00
Timothy Arceri a7050ea1f9 st/mesa: create set_prog_affected_state_flags() helper
This will be used when restoring tgsi from the on-disk shader
cache.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-02-02 08:31:28 +11:00
Timothy Arceri 8d3d8a6d4e st/mesa: st_atom_shader.c C99 tidy up
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-02-02 08:31:28 +11:00
Timothy Arceri f3e2428a7a st/mesa: remove pre C99 statement block for variable declaration
Acked-by: Marek Olšák <marek.olsak@amd.com>
2017-02-02 08:31:28 +11:00
Jason Ekstrand 0c114f2cf0 isl: Add assertions for render target swizzle restrictions
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-01 12:07:54 -08:00
Boyuan Zhang f90ccf48bc st/va: add h264 constrained baseline profile
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-02-01 14:32:32 -05:00
Boyuan Zhang d596bd29ec st/vdpau: add h264 constrained baseline profile
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-02-01 14:32:32 -05:00
Boyuan Zhang c29191eea8 radeon/uvd: add h264 constrained baseline support
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-02-01 14:32:32 -05:00
Boyuan Zhang 22841ec84a vl: add h264 constrained baseline profile
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-02-01 14:32:32 -05:00
Bas Nieuwenhuizen f5f8eb2c7c radv: Enable VK_KHR_shader_draw_parameters.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-02-01 19:49:40 +01:00
Bas Nieuwenhuizen cf8a11c1ba radv: Pass draw index to shader.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-02-01 19:49:40 +01:00
Bas Nieuwenhuizen 80f4331ed1 radv/ac: Add draw index support.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-02-01 19:49:40 +01:00
Robert Foss 25f2d3c1d3 i965: Prevent coverity warning
Add assert checking that num_sources is never larger than 3.

This prevents Coverity from concluding that the unhandled
cases of num_sources not being 0-3 are relevant.

Coverity-Id: 1399480-1399489
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2017-02-01 16:47:05 +00:00