Commit Graph

104959 Commits

Author SHA1 Message Date
Hyunjun Ko aef410f31e freedreno/ir3: fix the param order of cmpxchg
According to the following definition,
int AtomicCompSwap(inout int mem, uint compare, uint data);

the preceding one in atomic_comp_swap of NIR is compare and data is
followed, while src0 for cmpxchg needs vec2(data, compare)
So for ssbo/image deref comp_swap, that should be reversed.

Fixes: dEQP-GLES31.functional.image_load_store.*.atomic.comp_swap*
2018-09-27 16:05:49 -04:00
Rob Clark 49d22c2dfc freedreno/a6xx: fix shaders w/ >= 24 regs
Possibly these bits mean something else now.  Blob always seems to use
FOUR_QUADS, and changing to TWO_QUADS seems to cause different threads
to overlap registers.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:49:14 -04:00
Rob Clark 6530fcc4a7 freedreno/a6xx: fix gl_FragCoord.w
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:45:44 -04:00
Rob Clark 919741b8d5 freedreno: handle invalidated buffers harder
Do a better job of skipping mem2gmem/gmem2mem..

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:41:46 -04:00
Rob Clark 19e9d28646 freedreno/a6xx: fix constlen
Fix a few bits of confusion, as with previous gen's constlen is aligned
to 4, and value in bitfield is left-shifted by 2 (ie. divided by 4).
But this is done by the CONSTLEN() accessor/builder fxn, so don't do it
twice.  Also HLSQ_FS_CNTL.CONSTLEN is not special.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:33:10 -04:00
Rob Clark 12de415ad1 freedreno: fix inorder rendering case
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:32:39 -04:00
Rob Clark b65b6f7606 freedreno/a6xx: backface stencil state
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:31:56 -04:00
Rob Clark 93db15d300 freedreno/a6xx: fix gpu crash with separate-stencil
Fixes a crash in (of all things) dEQP-GLES2.info.vendor with
--deqp-surface-type=fbo..

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:31:34 -04:00
Rob Clark a52ef80d24 freedreno/a6xx: fix MRT config
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:30:36 -04:00
Rob Clark 8930e83642 freedreno: fix potential hang when destroying batch
batch_flush_reset_dependencies() expects to be called unlocked, and can
call fd_batch_reference() which can try to aquire the screen lock again.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:29:45 -04:00
Rob Clark ef6d15f8a8 freedreno: fix corrupted fb state
In c3d9f29b we allowed ctx->batch to be null, and started tracking the
current framebuffer state in fd_context.  But the existing logic in
fd_blitter_pipe_begin() would, if !ctx->batch, set null fb state to be
restored after blit.  Which broke the world of deqp (and probably other
things)

Fixes: c3d9f29b78 freedreno: allocate ctx's batch on demand
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:27:38 -04:00
Rob Clark 5bb96bf73a freedreno: simplify pctx->clear()
This is defined to always clear the entire surface(s) specified,
regardless of scissor state.. mesa/st will turn scissored clears
into a draw.  So rip about a bunch of unnecessary machinery.

Also remove a comment that was obsolete since using u_blitter to
turn clear into draw (for the cases where there isn't a hw blitter
fast-path).

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:26:32 -04:00
Rob Clark a7fa44cd33 freedreno: fix FD_MESA_DEBUG=flush
The logic to force a flush every draw was short-circuited with newer
kernels.  Also it should apply to clears as well.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:25:49 -04:00
Rob Clark 83c5c026ee freedreno: fix scissor state emit
The effective scissor changes based on rasterizer->scissor flag, so we
need to re-emit scissor state when rasterizer state changes.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:25:24 -04:00
Rob Clark 106f18258a freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:25:01 -04:00
Erik Faye-Lund c3486cd8c9 st/mesa: do not call update_framebuffer_size with NULL pointer
In st_renderbuffer_alloc_storage, we avoid allocating storage for
zero-sized buffers, leading to this pointer being NULL. We already
take care to avoid dereferencing these pointers for color-buffers,
but not for depth/stencil-buffers.

So let's thread a bit more carefully here.

This avoids a crash while running Piglit's glx/glx-visuals-stencil
test, both on virgl and r600g.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Guillaume Charifi <guillaume.charifi@sfr.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-09-27 10:33:44 +02:00
Maxime dd333c66bd vulkan: Disable randr lease for libxcb < 1.13
Since the Randr lease code was added, compiling against libxcb 1.12 no
longer works.

CC: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108024
Fixes: 7ab1fffcd2
Tested-By: Maxime <berillions@gmail.com>
Fixes: 7ab1fffcd2 "vulkan: Add EXT_acquire_xlib_display [v5]"
2018-09-27 16:31:42 +10:00
Bas Nieuwenhuizen 40585ddb48 radv: Remove garbage comment.
Trivial.
2018-09-27 02:04:06 +02:00
Bas Nieuwenhuizen 0207ebcbf1 radv: Do not use multiple draws for multisample copies.
Use sample rate shading instead, should give better locality.

Makes Nier with 8x msaa on a Raven go 5 fps -> 7 fps in the menu.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-09-27 02:04:00 +02:00
Jordan Justen ca1d3fc538
anv: If softpin is supported, use it with the hiz clear value bo
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-09-26 10:21:23 -07:00
Jordan Justen 2a97390552
anv: s/batch/value_bo/ on anv_device_init_hiz_clear_batch
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-09-26 10:21:23 -07:00
Dylan Baker e9bd071f49 docs: update calendar, add news and link release notes for 18.1.9 2018-09-26 09:44:40 -07:00
Dylan Baker d4bdcf5d22 docs: Add sha256 sums to 18.1.9 2018-09-26 09:41:53 -07:00
Dylan Baker 4769f49455 docs: Add 18.1.9 release notes 2018-09-26 09:40:56 -07:00
Jason Ekstrand b3f477ef7a intel/isl: Add a unit suffixes to some struct fields and variables
I was about to make the claim to someone that every field in isl_surf
is either an enum or has explicit units.  Then I looked at isl_surf and
discovered this claim was wrong.  We should fix that.  This commit does
a few refactors:

 * Add _B suffixes to some struct fields
 * Add _B to some variables and parameters
 * Rename row_pitch_tiles -> row_pitch_tl

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-09-26 08:52:26 -05:00
Axel Davy 0d495bec25 radeonsi: NaN should pass kill_if
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105333
Fixes: https://github.com/iXit/Mesa-3D/issues/314

For this application, NaN is passed to KILL_IF and is expected to
pass.

v2: Explain in the code why UGE is used.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

CC: <mesa-stable@lists.freedesktop.org>
2018-09-25 22:05:24 +02:00
Axel Davy 46814e771a st/nine: Do not mark both ff vs and ps updated
Previously if only ff vs or only ff ps was used,
the constants for both were marked as updated,
while only the constants of the used ff shader
were updated.

Now that NINE_STATE_FF_VS and
NINE_STATE_FF_PS do not intersect anymore,
we can correctly mark the correct set of constant
as updated.

Fixes: https://github.com/iXit/Mesa-3D/issues/319

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy 8e0526555d st/nine: Split NINE_STATE_FF_OTHER
NINE_STATE_FF_OTHER was mostly ff vs states.

Rename it to NINE_STATE_FF_VS_OTHER and
move common states with ps to
NINE_STATE_FF_PS_CONSTS (renamed from
NINE_STATE_FF_PSSTAGES).

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy 5f7a41c33b st/nine: Add dummy ff shader state
Some states only affect the ff shader,
not its constants.
Currently we don't check anything and
always recompute the ff shader key.

However we do check for NINE_STATE_FF_OTHER
and if set we reupload some constants.

Thus for those states which had NINE_STATE_FF_OTHER
set but didn't need it,
replace by a dummy ff shader state (which is
easier to understand for an external reader than
just setting 0 and more future proof).

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy f6bf1d2db0 st/nine: Mark pointsize states as ff states
The pointsize states were missing the ff
NINE_STATE_FF_OTHER flag, and thus might
miss state updates when using ff.

Fixes some wine tests.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy 89beea100f st/nine: Minor refactor of a few NINE_STATE_* flags
Rename NINE_STATE_FOG_SHADER,
NINE_STATE_POINTSIZE_SHADER and NINE_STATE_PS1X_SHADER
into
NINE_STATE_VS_PARAMS_MISC and NINE_STATE_PS_PARAMS_MISC.

The behaviour is unchanged, except one minor change:
D3DRS_FOGTABLEMODE doesn't need to affect VS.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy 7ae2509ce0 st/nine: Increase maximum number of temp registers
With some test app I hit the limit.
As we allocate on demand (up to the maximum),
it is free to increase the limit.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
2018-09-25 22:05:24 +02:00
Axel Davy dc4b53e129 st/nine: Lock the entire buffer in some cases.
Previously we had already found that for
MANAGED buffers the buffer started dirty
(which meant all writes out of bound
before the first draw call using the
buffer have to be taken into account).

Possibly it is the same for the other types of buffers.
For now always lock the entire buffer (starting from the offset)
for these (except for DYNAMIC buffers, which might hurt
performance too much).

Fixes: https://github.com/iXit/Mesa-3D/issues/301

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy 0eeb583650 st/nine: Don't call SetCursor until a cursor is set
The previous code was ignoring the input
until a cursor is set inside d3d
(with SetCursorProperties), as expected
by wine tests.

However it did still make a call to ID3DPresent_SetCursor,
which would result into a SetCursor(NULL) call, thus
hidding any cursor set outside d3d, which we shouldn't do.

Add comment about not avoiding redundant ID3DPresent_SetCursor
calls once a cursor has been set in d3d, as it has been tested to
cause regressions.

Fixes: https://github.com/iXit/Mesa-3D/issues/197

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy dcfde02bb0 st/nine: Avoid redundant SetCursorPos calls
For some applications SetCursorPosition
is called when a cursor event is received.

Our SetCursorPosition was always calling
wine SetCursorPos which would trigger
a cursor event.

The infinite loop is avoided by not calling
SetCursorPos when the position hasn't changed.
Found thanks to wine tests.

Fixes irresponsive GUI for some applications.

Fixes: https://github.com/iXit/Mesa-3D/issues/173

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
2018-09-25 22:05:24 +02:00
Axel Davy 112c770597 st/nine: Init cursor position at device creation
This is only useful for software cursor,
but at least now we won't start it at (0, 0).

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy 62ea55ec8b st/nine: Initialize manually cursor structure
Initialize manually the cursor structure fields
for more clarity on its content.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy 110950318c st/nine: Check if format is DS before retrieving flags
d3d9_get_pipe_depth_format_bindings assumes the input format
is a depth stencil format.
Previously the user could hit this function with an invalid format.
Protect the last non protected call with a depth_stencil_format check.

Another solution is to have d3d9_get_pipe_depth_format_bindings
support non depth stencil format, but we don't want the user
to create depth buffers with d3d formats that can't be one,
it's better to check if the format can be depth buffer with d3d.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy af60fbc0a4 st/nine: Remove clamping when mul_zero_wins
Tests show the clamping can be removed
when mul_zero_wins is supported.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy a0afa80889 st/nine: Implement predicated instructions
Most of the work was already there, just not implemented.

Fixes: https://github.com/iXit/Mesa-3D/issues/318

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy e7e82bcdc9 st/nine: Fix aliased read in ff
Fix aliasing of colorarg_b4 with
colorarg_b5.

Fixes: https://github.com/iXit/Mesa-3D/issues/302

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy 9fc6aa1bbe st/nine: Fix ff assignment with aliasing
"tex_stage[s][D3DTSS_COLORARG0] >> 4" could be a two bit
number, thus colorarg_b4 was incorrectly set.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy 8c35fb0280 st/nine: Clarify some ff assignments
colorarg0, etc are 3 bits wide.
Make the code more readable by adding an & 0x7
to further indicate we only remember the first 3 bits only.

The 4th bit is always 0,
and colorarg_b4, colorarg_b5, etc are used to store
the 5th and 6th bits.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy 59aaeeb730 st/nine: Print transform matrices in debug
This is useful to see the matrices content
in the log to debug.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy d9da0a1f6d st/nine: Add ff key hash to help debug
This is very useful to find in the log
the ff shader shource of a given call.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy fcbb00a502 st/nine: Avoid RefToBind calls in ff
When using csmt, ff shader creation happens on the csmt
thread. Creating the shaders, then calling RefToBind causes
the device ref to be increased then decreased.

However the device dtor assumes than no work pending on the
csmt thread could increase the device ref, leading to hang.

The issue is avoided by creating the shaders with a bind
count directly.

Fixes: https://github.com/iXit/Mesa-3D/issues/295

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy e83b15cba0 st/nine: Add new helper for object creation with bind
Add a new helper to create objects starting with a bind
count instead of a ref count.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy fd86ce7c14 st/nine: Add parameter to start with bind
Add a parameter to start new object with a bind
instead of a refcount.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy a9bf82ecf4 st/nine: Use perspective correction for ps depth fog
Emulate perspective interpolation of depth for programmable ps fog

ff ps fog uses position z, or 1/w depending on the ff
projection matrix set. This is according to public documents
found describing the algorithm and tests we made.

In the case of programmable ps, we used position's z,
which was sufficient to pass wine tests (which test shaders
don't set w).

Issue https://github.com/iXit/Mesa-3D/issues/315 showed
that this calculation was wrong.
Using perspective interpolation on z, that is using z * 1/w
seems to satisfy both this application and wine tests.

Fixes: https://github.com/iXit/Mesa-3D/issues/315

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2018-09-25 22:05:24 +02:00
Axel Davy 7ee5e5e239 st/nine: Clamp RCP when 0*inf!=0
Tests done on several devices of all 3 vendors and
of different generations showed that there are several
ways of handling infs and NaN for d3d9.

Tests showed Intel on windows does always clamp
RCP, RSQ and LOG (thus preventing inf/nan generation),
for all shader versions (some vendor behaviours vary
with shader versions).
Doing this in nine avoids 0*inf issues for drivers
that can't generate 0*inf=0 (which is controled by
TGSI's MUL_ZERO_WINS).

For now clamp for all drivers. An ulterior optimization
would be to avoid clamping for drivers with MUL_ZERO_WINS
for the specific shader versions where NV or AMD don't
clamp.

LOG and RSQ being already clamped, this patch only
clamps RCP.

Fixes: https://github.com/iXit/Mesa-3D/issues/316

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
2018-09-25 22:05:23 +02:00