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Author SHA1 Message Date
Marek Olšák bbad432e96 radeonsi: eliminate shader code for disabled or masked color outputs 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7721>
 2020-12-01 15:33:03 -05:00
Marek Olšák 509142876b radeonsi: add AMD_DEBUG=nofastlaunch for debugging 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7721>
 2020-12-01 15:33:03 -05:00
Marek Olšák de799b2270 radeonsi: enable NGG and NGG culling on gfx10.3 APUs by default 
VanGogh benefits.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7721>
 2020-12-01 15:33:03 -05:00
Pierre-Eric Pelloux-Prayer 0b3bd7c516 radeonsi/gfx10: flush gfx cs on ngg -> legacy transition 
with a sequence like this:

  glClear(STENCIL)
  glBeginTransformFeedback()
  ...
  glEndTransformFeedback()
  glClear(STENCIL)

The second clear sometimes may produce an unexpected result.

Calling si_flush_gfx_cs() when doing ngg -> legacy transition seems to be a
valid workaround (both for the synthetic reproducer and the real Blender bug).

Using flush flags or events (BOTTOM_OF_PIPE_TS, RESET_TO_LOWEST_VGT) didn't help.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2941
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7750>
 2020-11-26 10:19:26 +01:00
Marek Olšák 61fe66a2e4 radeonsi: pass VS->TCS IO via VGPRs if VS and TCS have the same thread count 
It can only be done if a TCS input is accessed without indirect indexing and
with gl_InvocationID as the vertex index, and the number of VS and TCS threads
is the same.

This eliminates LDS stores and loads for VS->TCS IO, reducing shader lifetime
and LDS traffic.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7623>
 2020-11-23 02:22:21 +00:00
Marek Olšák 1190808eca radeonsi: if VS and TCS have the same number of threads, merge the conditonals 
Instead of:
    if (VS) {
	VS;
    }
    if (TCS) {
	TCS;
    }

Do this if the number of threads is the same in VS and TCS:
    exec = enabled_threads;
    VS;
    TCS;

Skipping declare_vb_descriptor_input_sgprs is needed to match the VS return
values.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7623>
 2020-11-23 02:22:21 +00:00
Marek Olšák be905b74f7 radeonsi: don't add num_vbos_in_user_sgprs to the shader cache key for non-VS 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7542>
 2020-11-18 06:19:59 +00:00
Marek Olšák 025bc9e50e radeonsi: add options.inline_uniforms to the shader cache key 
It affects how shaders are finalized before caching.

Fixes: b7501184b9 ("radeonsi: implement inlinable uniforms")

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7542>
 2020-11-18 06:19:59 +00:00
Marek Olšák c4ebdf9ee7 radeonsi: do VGT_FLUSH when switching NGG -> legacy on Sienna Cichlid 
Other chips don't need this.

Fixes: 9538b9a68e - radeonsi: add support for Sienna Cichlid

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7542>
 2020-11-18 06:19:58 +00:00
Marek Olšák c3432ad852 radeonsi: add an option to enable 2x2 coarse shading for non-GUI elements 
This is for experiments with VRS.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7646>
 2020-11-17 22:16:19 +00:00
Marek Olšák baa5807e36 nir: rename needs_helper_invocations to needs_quad_helper_invocations 
This indicates that only quad operations use helper invocations.
Also handle quad_swizzle_amd.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7586>
 2020-11-12 21:02:05 +00:00
Marek Olšák b7501184b9 radeonsi: implement inlinable uniforms 
This improves performance for uber shaders.

It must be enabled using the new driconf option.

The driver compiles the specialized shaders in another thread without stalls,
same as all other optimizations.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7057>
 2020-10-30 11:07:22 +00:00
Marek Olšák 57d317865e radeonsi: enable NGG culling by default on Navi1x PRO cards 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7172>
 2020-10-17 01:58:19 +00:00
Marek Olšák bc3c74e2a2 radeonsi: tweak LATE_ALLOC_GS numbers for faster NGG culling 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7172>
 2020-10-17 01:58:19 +00:00
Marek Olšák 7648060dc0 radeonsi: enable NGG culling by default on gfx10.3 dGPUs 
for better performance

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7172>
 2020-10-17 01:58:19 +00:00
Marek Olšák 6810e6e4d0 Revert "radeonsi/gfx10: disable vertex grouping" 
This reverts commit 42f921387b.

It causes GPU hangs on gfx10.3.

Fixes: a23802bcb9 - ac,radeonsi: start adding support for gfx10.3

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7172>
 2020-10-17 01:58:19 +00:00
Marek Olšák 701f7ae9d2 radeonsi: move si_set_active_descriptors_for_shader into si_update_common_shader_state 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6948>
 2020-10-01 16:29:46 +00:00
Marek Olšák f5912c6d32 radeonsi: kill disabled clip distances and planes at per-channel granularity 
Apps often enable only 1 plane for gl_ClipVertex, which means 1 scalar
clip distance.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6948>
 2020-10-01 16:29:46 +00:00
Marek Olšák 30c3b2c0b6 radeonsi: simplify NGG culling enablement and add radeonsi_shader_culling option 
Add a vertex count threshold into si_shader_selector to simplify
the draw_vbo code.

The new option is supposed to be used in 00-mesa-defaults.conf and should be
tweaked for best performance unlike the AMD_DEBUG experimental options.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6948>
 2020-10-01 16:29:46 +00:00
Pierre-Eric Pelloux-Prayer 8e2768bbfb radeonsi/tmz: add tmz variant for sctx::tess_rings 
tess_rings must be encrypted when used in a secure job so this commit
introduces a tess_rings_tmz resource.

The cs_preamble_state doesn't contain the tess_rings address anymore since
it can change. The tess_rings related registers go in a separate preamble.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6049>
 2020-09-24 14:51:16 +00:00
Pierre-Eric Pelloux-Prayer 5e4aecec93 radeonsi: introduce SI_RESOURCE_FLAG_INTERNAL / RADEON_FLAG_DRIVER_INTERNAL 
Tag allocations as driver internal.
Some of these allocations will need to be doubled to handle TMZ (one secure bo,
one normal bo) but these allocations shouldn't switch the winsys in "the app
is using TMZ".

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6049>
 2020-09-24 14:51:16 +00:00
Marek Olšák b5debe180e radeonsi: break a binning batch on a new PS if bins can use multiple state sets 
ported from PAL

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6822>
 2020-09-24 11:55:06 +00:00
Marek Olšák 98188409d1 radeonsi: move debug options from si_disk_cache_create to si_get_ir_cache_key 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6810>
 2020-09-22 15:58:51 +00:00
Marek Olšák fc44861517 radeonsi: eliminate unused shader outputs for separate NGG geometry shaders 
This just works because the same output export code is used for VS too.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6634>
 2020-09-08 16:59:23 +00:00
Marek Olšák 5c445be39a radeonsi: set outputs_written_before_ps for geometry shaders too 
it will be used in following commit

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6634>
 2020-09-08 16:59:23 +00:00
Marek Olšák c56fbed99b radeonsi: kill point size VS output if it's not used by the rasterizer 
Fixed-func shaders can contain the output, because their generator
doesn't consider the current primitive type into account.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6620>
 2020-09-07 11:27:30 +00:00
Marek Olšák 234505162c radeonsi: deduplicate setting key.mono.u.vs_export_prim_id 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6620>
 2020-09-07 11:27:30 +00:00
Marek Olšák 757f790ad8 radeonsi: remove redundant si_shader_info::uses_derivatives 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:41 +00:00
Marek Olšák f3f08bca23 radeonsi: remove redundant si_shader_selector::max_gs_stream 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:41 +00:00
Marek Olšák 2b4fa68808 radeonsi: remove redundant GS variables in si_shader_selector 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák 7960668dc9 radeonsi: remove redundant si_shader_info::writes_memory 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák 99c4e61084 radeonsi: remove redundant si_shader_info::uses_kill 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák 8df349a31e radeonsi: merge uses_persp_opcode_interp_sample/uses_linear_opcode_interp_sample 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák f02cd0e027 radeonsi: remove redundant si_shader_info:*(clip|cull)* fields 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák d15a7d16d6 radeonsi: remove redundant si_shader_info::const_buffers_declared 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák 0dabcb9e53 radeonsi: remove redundant si_shader_info::images_declared 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák c1af2f4bee radeonsi: remove redundant si_shader_info::shader_buffers_declared 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák cb63e4afc9 radeonsi: remove info::samplers_declared, image_buffers, msaa_images_declared 
They are redundant with shader_info.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák cb7bc983ae radeonsi: stop using TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák ebe8238f1b radeonsi: stop using TGSI_PROPERTY_FS_DEPTH_LAYOUT 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák ce0291df4a radeonsi: stop using TGSI_PROPERTY_FS_COORD_PIXEL_CENTER 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák c597e394d4 radeonsi: stop using TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák 5aeaf3d7bc radeonsi: stop using TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák e627528e27 radeonsi: stop using TGSI_PROPERTY_GS_* 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák a8e7024792 radeonsi: stop using TGSI_PROPERTY_TES_VERTEX_ORDER_CW 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák eeea2f52c7 radeonsi: stop using TGSI_PROPERTY_TES_SPACING 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák 34b8e60cb8 radeonsi: stop using TGSI_PROPERTY_TES_POINT_MODE / TES_PRIM_MODE 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák a37d897d69 radeonsi: stop using TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION / VS_BLIT_SGPRS_AMD 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák 46bb051bc2 radeonsi: stop using TGSI_PROPERTY_NEXT_SHADER 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
 2020-09-07 11:15:40 +00:00
Marek Olšák 98e866c669 radeonsi: optimize out the loop in si_get_ps_input_cntl 
Use a remap table from a semantic to an index instead of searching
for the correct index.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>
 2020-09-02 23:03:00 -04:00
Marek Olšák 6ecb8b6899 radeonsi: replace TGSI_SEMANTIC with VARYING_SLOT and FRAG_RESULT 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>
 2020-09-02 23:03:00 -04:00
Marek Olšák a803008c7f radeonsi: replace TGSI_INTERPOLATE with INTERP_MODE 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>
 2020-09-02 23:03:00 -04:00
Marek Olšák 6925401a38 radeonsi: remove si_shader_selector::type 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>
 2020-09-02 23:03:00 -04:00
Marek Olšák 966307983b radeonsi: precompute si_*_descriptors_idx in si_shader_selector 
It helps remove one use of sel->type.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>
 2020-09-02 23:03:00 -04:00
Marek Olšák 3c54d73e4b radeonsi: change PIPE_SHADER to MESA_SHADER (debug flags) 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>
 2020-09-02 23:03:00 -04:00
Marek Olšák b1cb72c449 radeonsi: change PIPE_SHADER to MESA_SHADER (si_shader_selector::type) 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>
 2020-09-02 23:03:00 -04:00
Marek Olšák 14391533f8 radeonsi: simplify handling color interp modes in si_emit_spi_map 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>
 2020-09-02 23:03:00 -04:00
Marek Olšák 81d106d6ec radeonsi: lower IO intrinsics - complete rewrite of input/output scanning 
Input and output info is gathered from intrinsics. nir_variables are
ignored (and we'll remove them anyway).

This is a prerequisite for ACO, but also makes the IR prettier.
The ac_nir_to_llvm change has to be in this commit.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6445>
 2020-09-02 22:45:38 -04:00
Marek Olšák b7a6333ee4 amd/registers: switch to new generated register definitions 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6423>
 2020-09-01 08:45:54 -04:00
Marek Olšák 633d2aa915 radeonsi: use the same units for esgs_ring_size and ngg_emit_size 
for consistency

Fixes: a23802bcb9 - ac,radeonsi: start adding support for gfx10.3

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:21 -04:00
Marek Olšák 8af0f91fd3 radeonsi: add reg shadowing codepaths to GS and tess ring setup 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:33 -04:00
Marek Olšák b84dbd2936 radeonsi: reorder code in update_gs_ring_buffers and init_tess_factor_ring 
to reduce the churn when adding codepaths for shadowed registers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák 081691b5ae radeonsi: prevent a gfx10_ngg_calculate_subgroup_info failure for TES+NGG GS 
arb_tessellation_shader-tes-gs-max-output -small -scan 1 50 -auto -fbo
doesn't pass, but at least all shaders are compiled successfully.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5700>
 2020-07-16 04:04:52 +00:00
Marek Olšák 50d7553600 radeonsi: add a debug option to enable NGG culling for tessellation 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5524>
 2020-06-30 10:56:41 +00:00
Marek Olšák 9049e39804 radeonsi: always use Wave32 for GS fast launch, because Wave64 hangs 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5524>
 2020-06-30 10:56:41 +00:00
Pierre-Eric Pelloux-Prayer 5a05f9714b radeonsi: bump SI_NUM_SHADER_BUFFERS to 32 
Some app uses more than 8 SSBOs (https://gitlab.freedesktop.org/mesa/mesa/-/issues/2946),
so increase SI_NUM_SHADER_BUFFERS to 32 (which allows 16 SSBOs).

Since we're now using a 64 bits number to track buffers, we could bump
SI_NUM_SHADER_BUFFERS to 48 but that would conflict with Mesa's
MAX_COMBINED_ATOMIC_BUFFERS limit (= 90).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2122
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5632>
 2020-06-30 09:23:14 +02:00
Marek Olšák da78d50bc8 radeonsi: make si_pm4_cmd_begin/end static and simplify all usages 
There is no longer the confusing trailing si_pm4_cmd_end call.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 7b2a0f880b radeonsi: disallow adding BOs into si_pm4_state except 1 shader BO per state 
The si_shader pointer is already there, so use it and remove the array
of BOs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 428360662f radeonsi: don't add the tess ring buffers into the cs_preamble state 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 1c1d34a67a radeonsi: rename init_config states to cs_preamble states 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 3fec2f67c3 radeonsi: compact MRTs to save PS export memory space 
If there are holes between color outputs (e.g. a shader exports MRT1, but
not MRT0), we can remove the holes by moving higher MRTs lower.

The hardware will remap the MRTs to their correct locations if we remove
holes in SPI_SHADER_COL_FORMAT but not CB_SHADER_MASK.

This is a performance optimization, but MRTs with holes are pretty rare,
so there is most likely no effect on any app.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5535>
 2020-06-23 00:23:51 -04:00
Marek Olšák a23802bcb9 ac,radeonsi: start adding support for gfx10.3 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Marek Olšák a1602516d7 ac,radeonsi: replace == GFX10 with >= GFX10 where it's needed 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Marek Olšák 2a3806ffa3 amd: replace SH -> SA (shader array) in comments 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5184>
 2020-05-26 06:00:54 -04:00
Marek Olšák 2cf46f2e3d ac/gpu_info: replace num_good_cu_per_sh with min/max_good_cu_per_sa 
Perf counters use the new max number.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5184>
 2020-05-26 06:00:54 -04:00
Marek Olšák 3cd96b5109 radeonsi: don't use INDIRECT_BUFFER within IBs 
It's fragile. If I change the size or alignment, it hangs. Better safe than
sorry.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:44:44 -04:00
Axel Davy 45e69e7d11 radeonsi: Enable tgsi to nir disk cache 
Enable the tgsi to nir cache for radeonsi.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4993>
 2020-05-13 19:43:05 +00:00
Axel Davy 522bd414f3 ttn: Add new allow_disk_cache parameter 
For now this parameter doesn't do anything.
It means the implementation is allowed to use
a cache on disk.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4993>
 2020-05-13 19:43:05 +00:00
Pierre-Eric Pelloux-Prayer 547e81655a radeonsi: don't print gs_copy_shader stats for shaderdb 
Fixes: dbc86fa3de ("radeonsi: dump shader stats when hitting the live cache")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
 2020-05-05 12:26:02 +02:00
Marek Olšák b4fd8f1919 ac,radeonsi: simplify checking for Navi1x chips 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4698>
 2020-04-24 10:38:54 +00:00
Pierre-Eric Pelloux-Prayer dbc86fa3de radeonsi: dump shader stats when hitting the live cache 
With the introduction of the live shader cache, when a shader is
fetched from the cache no stats are printed for shaderdb.
So in a sequence like this: vs1, fs1, vs1, fs2, shaderdb may see
3 or 4 lines, depending on the threads being used.
If one run produces 3 lines while the other produces 4 lines, it
would compare vs1 stats with fs2 stats.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4355>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4355>
 2020-04-02 08:31:37 +02:00
Pierre-Eric Pelloux-Prayer d7008fe46a radeonsi: switch to 3-spaces style 
Generated automatically using clang-format and the following config:

AlignAfterOpenBracket: true
AlignConsecutiveMacros: true
AllowAllArgumentsOnNextLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: false
AlwaysBreakAfterReturnType: None
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BinPackParameters: true
BreakBeforeBraces: Custom
ColumnLimit: 100
ContinuationIndentWidth: 3
Cpp11BracedListStyle: false
Cpp11BracedListStyle: true
ForEachMacros:
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  - nir_foreach_use_safe
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  - nir_foreach_def
  - nir_foreach_def_safe
  - nir_foreach_phi_src
  - nir_foreach_phi_src_safe
  - nir_foreach_parallel_copy_entry
  - nir_foreach_instr
  - nir_foreach_instr_reverse
  - nir_foreach_instr_safe
  - nir_foreach_instr_reverse_safe
  - nir_foreach_function
  - nir_foreach_block
  - nir_foreach_block_safe
  - nir_foreach_block_reverse
  - nir_foreach_block_reverse_safe
  - nir_foreach_block_in_cf_node
IncludeBlocks: Regroup
IncludeCategories:
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    Priority:        2
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IndentWidth: 3
PenaltyBreakBeforeFirstCallParameter: 1
PenaltyExcessCharacter: 100
SpaceAfterCStyleCast: false
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: false
SpacesInContainerLiterals: false

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
 2020-03-30 11:05:52 +00:00
Marek Olšák 4ef1c8d60b radeonsi/gfx10: fix the wave size for compute-based culling 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
 2020-03-28 00:58:34 +00:00
Marek Olšák 65e9239977 radeonsi: add num_vbos_in_user_sgprs into the shader cache key 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
 2020-03-28 00:58:34 +00:00
Marek Olšák 7ba5e94c50 ac: add radeon_info::use_late_alloc to control LATE_ALLOC globally 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
 2020-03-12 17:27:23 +00:00
Marek Olšák 7481c4be58 radeonsi: add a bug workaround for NGG - LATE_ALLOC_GS 
Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
 2020-03-09 16:08:10 -04:00
Daniel Schürmann 9d64ad2fe7 radeonsi: lower discard to demote when FS_CORRECT_DERIVS_AFTER_KILL is enabled 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
 2020-03-09 12:29:32 +00:00
Marek Olšák c046551e60 radeonsi: print shader cache stats with AMD_DEBUG=cache_stats 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
 2020-01-24 20:29:29 -05:00
Marek Olšák 2fd3bb23ab radeonsi: restructure si_shader_cache_load_shader 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
 2020-01-24 20:29:29 -05:00
Marek Olšák 0db74f479b radeonsi: use the live shader cache 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
 2020-01-24 20:29:29 -05:00
Marek Olšák 7ce84b256e radeonsi: make si_compile_shader return bool 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
 2020-01-23 19:10:21 +00:00
Marek Olšák 735a3ba007 radeonsi/gfx10: enable GS fast launch for triangles and strips with NGG culling 
Only non-indexed triangle lists and strips are supported. This increases
performance if there is something to cull.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-20 16:16:11 -05:00
Marek Olšák c377f45c18 radeonsi/gfx10: rewrite late alloc computation 
- Use conservative late alloc when the number of CUs <= 6.
- Move the late alloc GS register to the GS shader state, so that it can be
  tuned for NGG culling.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-20 16:16:11 -05:00
Marek Olšák 8db00a51f8 radeonsi/gfx10: implement NGG culling for 4x wave32 subgroups 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-20 16:16:11 -05:00
Marek Olšák aa2d846604 radeonsi/gfx10: move GE_PC_ALLOC setting to shader states 
The value is not changed. I just use a different way to compute it.

The value will vary with NGG culling.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-20 16:16:11 -05:00
Marek Olšák 41fef6fc09 radeonsi/gfx10: don't initialize VGPRs not used by NGG passthrough 
v2: TES doesn't use the GS PrimitiveID

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-20 16:16:11 -05:00
Marek Olšák 42112010a3 radeonsi: rename si_shader_create -> si_create_shader_variant for clarity 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák 03950473df radeonsi: merge si_tessctrl_info into si_shader_info 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák 5fa2ab831e radeonsi: fork tgsi_shader_info and tgsi_tessctrl_info 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák 363b4027fc radeonsi: put up to 5 VBO descriptors into user SGPRs 
gfx6-8: 1 VBO descriptor in user SGPRs
gfx9-10: 5 VBO descriptors in user SGPRs

We no longer pull up to 5 VBO descriptors from GTT when SDMA is disabled.

Totals from affected shaders:
SGPRS: 1110528 -> 1170528 (5.40 %)
VGPRS: 952896 -> 951936 (-0.10 %)
Spilled SGPRs: 83 -> 61 (-26.51 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 23766296 -> 22843920 (-3.88 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 179344 -> 179344 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-13 15:57:07 -05:00