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radeonsi: stop using TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION / VS_BLIT_SGPRS_AMD 

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
This commit is contained in:
Marek Olšák 2020-09-01 17:50:59 -04:00 committed by Marge Bot
parent 46bb051bc2
commit a37d897d69
8 changed files with 30 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
View File

@ -90,7 +90,7 @@ static LLVMValueRef ngg_get_vertices_per_prim(struct si_shader_context *ctx, uns
const struct si_shader_info *info = &ctx->shader->selector->info;
if (ctx->stage == MESA_SHADER_VERTEX) {
if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
if (info->base.vs.blit_sgprs_amd) {
/* Blits always use axis-aligned rectangles with 3 vertices. */
*num_vertices = 3;
return LLVMConstInt(ctx->ac.i32, 3, 0);
@ -1322,7 +1322,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi, unsigned max_outputs, LL
}
/* Update query buffer */
if (ctx->screen->use_ngg_streamout && !info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
if (ctx->screen->use_ngg_streamout && !info->base.vs.blit_sgprs_amd) {
assert(!unterminated_es_if_block);
tmp = si_unpack_param(ctx, ctx->vs_state_bits, 6, 1);

11
src/gallium/drivers/radeonsi/si_shader.c
View File

@ -387,7 +387,6 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader)
unsigned num_returns = 0;
unsigned num_prolog_vgprs = 0;
unsigned stage = ctx->stage;
unsigned vs_blit_property = shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
memset(&ctx->args, 0, sizeof(ctx->args));
@ -403,8 +402,8 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader)
case MESA_SHADER_VERTEX:
declare_global_desc_pointers(ctx);
if (vs_blit_property) {
declare_vs_blit_inputs(ctx, vs_blit_property);
if (shader->selector->info.base.vs.blit_sgprs_amd) {
declare_vs_blit_inputs(ctx, shader->selector->info.base.vs.blit_sgprs_amd);
/* VGPRs */
declare_vs_input_vgprs(ctx, &num_prolog_vgprs, ngg_cull_shader);
@ -523,14 +522,14 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader)
NULL); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
declare_global_desc_pointers(ctx);
if (ctx->stage != MESA_SHADER_VERTEX || !vs_blit_property) {
if (ctx->stage != MESA_SHADER_VERTEX || !shader->selector->info.base.vs.blit_sgprs_amd) {
declare_per_stage_desc_pointers(
ctx, (ctx->stage == MESA_SHADER_VERTEX || ctx->stage == MESA_SHADER_TESS_EVAL));
}
if (ctx->stage == MESA_SHADER_VERTEX) {
if (vs_blit_property)
declare_vs_blit_inputs(ctx, vs_blit_property);
if (shader->selector->info.base.vs.blit_sgprs_amd)
declare_vs_blit_inputs(ctx, shader->selector->info.base.vs.blit_sgprs_amd);
else
declare_vs_specific_input_sgprs(ctx);
} else {

2
src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
View File

@ -41,7 +41,7 @@ static LLVMValueRef unpack_sint16(struct si_shader_context *ctx, LLVMValueRef i3
static void load_input_vs(struct si_shader_context *ctx, unsigned input_index, LLVMValueRef out[4])
{
const struct si_shader_info *info = &ctx->shader->selector->info;
unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
unsigned vs_blit_property = info->base.vs.blit_sgprs_amd;
if (vs_blit_property) {
LLVMValueRef vertex_id = ctx->abi.vertex_id;

5
src/gallium/drivers/radeonsi/si_shader_nir.c
View File

@ -456,11 +456,6 @@ void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *inf
info->base = nir->info;
info->stage = nir->info.stage;
if (nir->info.stage == MESA_SHADER_VERTEX) {
info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] = nir->info.vs.window_space_position;
info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] = nir->info.vs.blit_sgprs_amd;
}
if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] = nir->info.tess.tcs_vertices_out;
}

3
src/gallium/drivers/radeonsi/si_state.c
View File

@ -732,7 +732,8 @@ static void si_emit_clip_regs(struct si_context *sctx)
struct si_shader_selector *vs_sel = vs->selector;
struct si_shader_info *info = &vs_sel->info;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
unsigned window_space = info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
bool window_space = info->stage == MESA_SHADER_VERTEX ?
info->base.vs.window_space_position : 0;
unsigned clipdist_mask = vs_sel->clipdist_mask;
unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
unsigned culldist_mask = vs_sel->culldist_mask;

2
src/gallium/drivers/radeonsi/si_state_draw.c
View File

@ -1827,7 +1827,7 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
(!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
(!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
(!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
!sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
!sctx->vs_shader.cso->info.base.vs.window_space_position &&
!sctx->vs_shader.cso->so.num_outputs &&
#else
(sctx->vs_shader.cso->prim_discard_cs_allowed ||

33
src/gallium/drivers/radeonsi/si_state_shaders.c
View File

@ -1064,7 +1064,8 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
unsigned num_user_sgprs;
unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
uint64_t va;
unsigned window_space = gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
bool window_space = gs_info->stage == MESA_SHADER_VERTEX ?
gs_info->base.vs.window_space_position : 0;
bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
unsigned input_prim = si_get_input_prim(gs_sel);
@ -1086,9 +1087,9 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
if (es_stage == MESA_SHADER_VERTEX) {
es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
if (es_info->base.vs.blit_sgprs_amd) {
num_user_sgprs =
SI_SGPR_VS_BLIT_DATA + es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
SI_SGPR_VS_BLIT_DATA + es_info->base.vs.blit_sgprs_amd;
} else {
num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
}
@ -1346,7 +1347,8 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
unsigned num_user_sgprs, vgpr_comp_cnt;
uint64_t va;
unsigned nparams, oc_lds_en;
unsigned window_space = info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
bool window_space = info->stage == MESA_SHADER_VERTEX ?
info->base.vs.window_space_position : 0;
bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
pm4 = si_get_shader_pm4_state(shader);
@ -1390,8 +1392,8 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
} else if (shader->selector->info.stage == MESA_SHADER_VERTEX) {
vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
if (info->base.vs.blit_sgprs_amd) {
num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->base.vs.blit_sgprs_amd;
} else {
num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
}
@ -1701,7 +1703,7 @@ static unsigned si_get_alpha_test_func(struct si_context *sctx)
void si_shader_selector_key_vs(struct si_context *sctx, struct si_shader_selector *vs,
struct si_shader_key *key, struct si_vs_prolog_bits *prolog_key)
{
if (!sctx->vertex_elements || vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
if (!sctx->vertex_elements || vs->info.base.vs.blit_sgprs_amd)
return;
struct si_vertex_elements *elts = sctx->vertex_elements;
@ -2611,20 +2613,20 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
}
sel->num_vs_inputs =
sel->info.stage == MESA_SHADER_VERTEX && !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]
sel->info.stage == MESA_SHADER_VERTEX && !sel->info.base.vs.blit_sgprs_amd
? sel->info.num_inputs
: 0;
sel->num_vbos_in_user_sgprs = MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
/* The prolog is a no-op if there are no inputs. */
sel->vs_needs_prolog = sel->info.stage == MESA_SHADER_VERTEX && sel->info.num_inputs &&
!sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
!sel->info.base.vs.blit_sgprs_amd;
sel->prim_discard_cs_allowed =
sel->info.stage == MESA_SHADER_VERTEX && !sel->info.uses_bindless_images &&
!sel->info.uses_bindless_samplers && !sel->info.writes_memory &&
!sel->info.writes_viewport_index &&
!sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] && !sel->so.num_outputs;
!sel->info.base.vs.window_space_position && !sel->so.num_outputs;
switch (sel->info.stage) {
case MESA_SHADER_GEOMETRY:
@ -2741,8 +2743,9 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
sel->info.writes_position &&
!sel->info.writes_viewport_index && /* cull only against viewport 0 */
!sel->info.writes_memory && !sel->so.num_outputs &&
!sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] &&
!sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
(sel->info.stage != MESA_SHADER_VERTEX ||
(!sel->info.base.vs.blit_sgprs_amd &&
!sel->info.base.vs.window_space_position));
/* PA_CL_VS_OUT_CNTL */
if (sctx->chip_class <= GFX9)
@ -2848,8 +2851,8 @@ static void si_update_clip_regs(struct si_context *sctx, struct si_shader_select
{
if (next_hw_vs &&
(!old_hw_vs ||
old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
(old_hw_vs->info.stage == MESA_SHADER_VERTEX && old_hw_vs->info.base.vs.window_space_position) !=
(next_hw_vs->info.stage == MESA_SHADER_VERTEX && next_hw_vs->info.base.vs.window_space_position) ||
old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
old_hw_vs->culldist_mask != next_hw_vs->culldist_mask || !old_hw_vs_variant ||
@ -2885,7 +2888,7 @@ static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
sctx->vs_shader.cso = sel;
sctx->vs_shader.current = sel ? sel->first_variant : NULL;
sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
sctx->num_vs_blit_sgprs = sel ? sel->info.base.vs.blit_sgprs_amd : 0;
if (si_update_ngg(sctx))
si_shader_change_notify(sctx);

2
src/gallium/drivers/radeonsi/si_state_viewport.c
View File

@ -557,7 +557,7 @@ void si_update_vs_viewport_state(struct si_context *ctx)
return;
/* When the VS disables clipping and viewport transformation. */
vs_window_space = info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
vs_window_space = info->stage == MESA_SHADER_VERTEX && info->base.vs.window_space_position;
if (ctx->vs_disables_clipping_viewport != vs_window_space) {
ctx->vs_disables_clipping_viewport = vs_window_space;