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radeonsi: stop using TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL 

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
This commit is contained in:
Marek Olšák 2020-09-01 18:17:41 -04:00 committed by Marge Bot
parent ba7b87a8a2
commit 5aeaf3d7bc
3 changed files with 40 additions and 37 deletions
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5
src/gallium/drivers/radeonsi/si_shader_nir.c
View File

@ -462,8 +462,9 @@ void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *inf
}
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
/* post_depth_coverage implies early_fragment_tests */
info->base.fs.early_fragment_tests |= info->base.fs.post_depth_coverage;
info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
if (nir->info.fs.pixel_center_integer) {

2
src/gallium/drivers/radeonsi/si_state.c
View File

@ -3354,7 +3354,7 @@ static bool si_out_of_order_rasterization(struct si_context *sctx)
/* The set of PS invocations is always order invariant,
* except when early Z/S tests are requested. */
if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.writes_memory &&
sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
sctx->ps_shader.cso->info.base.fs.early_fragment_tests &&
!dsa_order_invariant.pass_set)
return false;

70
src/gallium/drivers/radeonsi/si_state_shaders.c
View File

@ -2773,39 +2773,41 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
break;
}
/* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
*
* | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
* --|-----------|------------|------------|--------------------|-------------------|-------------
* 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
* 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
* 2 | false | true | n/a | LateZ | 1 | 0
* 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
* 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
*
* In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
* In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
*
* Don't use ReZ without profiling !!!
*
* ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
* shaders.
*/
if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
/* Cases 3, 4. */
sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
} else if (sel->info.writes_memory) {
/* Case 2. */
sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) | S_02880C_EXEC_ON_HIER_FAIL(1);
} else {
/* Case 1. */
sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
}
if (sel->info.stage == MESA_SHADER_FRAGMENT) {
/* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
*
* | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
* --|-----------|------------|------------|--------------------|-------------------|-------------
* 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
* 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
* 2 | false | true | n/a | LateZ | 1 | 0
* 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
* 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
*
* In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
* In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
*
* Don't use ReZ without profiling !!!
*
* ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
* shaders.
*/
if (sel->info.base.fs.early_fragment_tests) {
/* Cases 3, 4. */
sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
} else if (sel->info.writes_memory) {
/* Case 2. */
sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) | S_02880C_EXEC_ON_HIER_FAIL(1);
} else {
/* Case 1. */
sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
}
if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
}
(void)simple_mtx_init(&sel->mutex, mtx_plain);
@ -3055,8 +3057,8 @@ static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
if (sctx->screen->has_out_of_order_rast &&
(!old_sel || old_sel->info.writes_memory != sel->info.writes_memory ||
old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
old_sel->info.base.fs.early_fragment_tests !=
sel->info.base.fs.early_fragment_tests))
si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
}
si_set_active_descriptors_for_shader(sctx, sel);