Commit Graph

137484 Commits

Author SHA1 Message Date
Anuj Phogat 9da8a55b08 intel: Rename GEN_GEN macro to GFX_VER
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_GEN" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_GEN/GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:06 +00:00
Anuj Phogat 295bb3c263 intel: Rename GEN_VERSIONx10 macro to GFX_VERx10
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_VERSION" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_VERSION/GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:06 +00:00
Ilia Mirkin b9b4324ca3 mesa: fix restoring of texture attributes for msaa binding points
This fixes rendering in Unigine Tropics with MSAA enabled. Since the
binding for MSAA does not get restored, we can't rely on the "defaults
get restored below" logic in that case.

Fixes: 81e6f6ef0c (mesa: don't push/pop default texture attributes redundantly)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4558
Reported-by: Andrew Randrianasulu <randrianasulu@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10001>
2021-04-02 17:49:59 +00:00
Jesse Natalie f447c69653 spirv_to_dxil: Handle clip/cull distance
Clip/cull only needs a little bit of lowering before nir_to_dxil can
handle it. Specifically, we just need to split apart arrays that
straddle the 4-component boundary of location, so that the signature
builder can handle it.

To do that cleanly, we need to add some lowering and optimization passes:
* nir_lower_clip_cull_distance_arrays: Merge clip/cull into a single array,
  which is similar to DXIL's requirements here.
* nir_lower_io_to_temporaries: Ensure that we only have one non-indirect write
  to the clip/cull output.
* nir_split_var_copies and nir_lower_var_copies: Ensure that each array entry
  has an independent write with a constant index
* Optimization loop: Make sure that there's no extra derefs in the way between
  deref_var for the output, deref_array for the component, and store_deref.
Then we can actually lower the clip/cull array cleanly.

Still to do is to sort the variables and add driver_location.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-by: Michael Tang <tangm@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9846>
2021-04-02 17:16:48 +00:00
Jesse Natalie 39aa32b838 microsoft/spirv_to_dxil: Implement TODO for removing dead functions
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-by: Michael Tang <tangm@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9846>
2021-04-02 17:16:48 +00:00
Jesse Natalie bd64669fa7 d3d12: Use compact arrays for clip/cull distance
This puts us more in line with other drivers, and matches what
SPIR-V would produce rather than the GLSL compiler. It also means
we can delete the current fixup pass, since previously clip distance
was always float4s but some components could go unused. Now, clip
distance is an array that's appropriately sized for what's actually
written.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9846>
2021-04-02 17:16:48 +00:00
Jesse Natalie baeb363df0 microsoft/compiler: Support compact arrays for clip/cull in nir_to_dxil
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Acked-by: Michael Tang <tangm@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9846>
2021-04-02 17:16:48 +00:00
Jesse Natalie 4941decc58 microsoft/compiler: Enable dxil_nir.h to be included from C++
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Acked-by: Michael Tang <tangm@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9846>
2021-04-02 17:16:48 +00:00
Jesse Natalie 65e1bee99c microsoft/compiler: Add a lowering pass to split clip/cull distance compact arrays
As the pass's comment explains, NIR compact arrays are a better match
to represent the GLSL float[] design of clip/cull distance arrays, compared
to the float4[2] approach. This pass adjusts the variables to more closely
match what DXIL signatures would look like for that representation.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Acked-by: Michael Tang <tangm@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9846>
2021-04-02 17:16:48 +00:00
Jesse Natalie 96cd961853 microsoft/compiler: Add copy_prop_vars to optimization loop
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Acked-by: Michael Tang <tangm@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9846>
2021-04-02 17:16:48 +00:00
Jesse Natalie 3f1b90d638 microsoft/compiler: Move blob_init earlier to prevent crash on failure
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Acked-by: Michael Tang <tangm@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9846>
2021-04-02 17:16:48 +00:00
Michael Tang cb5120bcf7 microsoft/spirv_to_dxil: Add extra lowering functions according to the docs on nir_inline_functions
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9846>
2021-04-02 17:16:48 +00:00
Michael Tang 2f3dc0264c microsoft/spirv_to_dxil: Add lowering pass to handle gl_PerVertex
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9846>
2021-04-02 17:16:48 +00:00
Mike Blumenkrantz fbebe36547 features: mark off GL_OES_viewport_array for zink
also done for a while

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10007>
2021-04-02 11:35:44 -04:00
Mike Blumenkrantz 8199bd653e features: mark off ARB_compute_variable_group_size for zink
this has been implemented for a long time

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10007>
2021-04-02 11:30:21 -04:00
Adrian Ratiu 8371b75241 docs: docker: minor stale documentation fix
Commits like the following changed the script names and distro tag
but didn't update the documentation. We do not explicitely mention
script names because they will likely change in the future but the
distro tag is less likely to change because it is shared with the
upstream ci-templates repo.

Fixes: af7dca3560 ("ci: Update the ci-templates commit.")
Fixes: 506e9d5fc7 ("gitlab-ci: Rename container install scripts to ...")
Fixes: c6c7652753 ("gitlab-ci: Organize images using new REPO_SUFFIX ...")
Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9781>
2021-04-02 15:16:54 +00:00
Mike Blumenkrantz 9d8dd8d27b zink: add some asserts to avoid zero-sized blit regions
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9999>
2021-04-02 14:14:57 +00:00
Mike Blumenkrantz 44076a3d6c zink: fix layercount for array texture blits
3d is base, base+count, array is base, count

Fixes: 83bee837e5 ("zink: be more explicit about blit layer/depth usage")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9999>
2021-04-02 14:14:57 +00:00
Marek Olšák 5e4d31f646 ac/surface/tests: move shareable code into ac_surface_test_common.h
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák b3e6514984 radeonsi: don't use CP DMA for clears/copies except for very small ones
The current compute shaders are much faster.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 64cbab5348 radeonsi: turn the loops over color buffers into while loops in si_clear
NULL color buffers are not set in "buffers" here.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 5ba77c4a5d radeonsi: unset PIPE_CLEAR_* flags for non-existent buffers
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 0580d4c1a2 radeonsi: enable HTILE with mipmapping on gfx9+
Everything seems to be there except fast clears.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 4e35eb1d69 radeonsi: set better default depth clear value
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 3345e32de7 radeonsi: group and parallelize all clears in si_texture_create_object
This reduces aux_context flushes significantly.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák cb6e1c7c11 radeonsi: add num_layers variable into si_do_fast_color_clear
in preparation for the next commit

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 1936a046b1 radeonsi: return success/failure from si_alloc_separate_cmask
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 8cd61d1248 radeonsi: parallelize CMASK and DCC clears
Clearing 8 RTs with both DCC and CMASK caused 16 synchronized clears where
we also did 16 times WAIT_REG_MEM for CB flushes that were 15 times
useless.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák d0f06e5c47 radeonsi: remove si_screen::dcc_msaa_allowed
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 4707dc6a64 radeonsi: determine accurately whether the framebuffer state has DCC MSAA
We only need to check storage samples, which is what affects DCC.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 933df67296 ac/surface: add CMASK info for level 0
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák b3e7c77f13 amd: fix parsing the last dword of DMA_DATA packets
It was parsing it as SQ_WAVE_GPR_ALLOC instead of COMMAND.
Change the offset to an odd number to work around it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 95940459be radeonsi: pack the variable block size in one SGPR, 10 bits per component
The side effect of this is that the compute copy image shader now has
enough free user SGPRs that it passes the src image via user SGPRs,
resulting in lower wave lifetime.

Previous copy shader:
    s_load_dwordx8
    image_load
    s_load_dwordx8
    s_waitcnt
    image_store

Current copy shader:
    image_load
    s_load_dwordx8
    s_waitcnt
    image_store

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 034c1e4845 radeonsi: decrease the maximum variable block size
to allow packing the block size in 1 user SGPR with 10 bits per component,
so that block sizes such as 512x1x1 fit in there.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák ad71ef9326 radeonsi: don't use a constant buffer for the copy_image compute shader
just use user SGPRs and 16-bit values for the x,y,z coordinates.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 5701baa34b radeonsi: don't use constbuf and set cache policy for 12-byte clear shader
This removes the constant buffer and sets the cache policy like other
compute shaders.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 7d14eb623b radeonsi: return false from si_is_format_supported instead of NULL
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák c53261645d radeonsi: add SI_CONTEXT_PFP_SYNC_ME to skip syncing PFP for image operations
DCC/CMASK/HTILE clears will not set this. We could do a better job
at not setting this in other cases too

Image copies also don't set this.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 4fb1b7b2d8 radeonsi: use the optimal packet order before draw packets for VS flushes too
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák b1a73ec99b radeonsi: rename and apply SI_OP_CPDMA_SKIP_CACHE_FLUSH to compute as well
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 419e05d5f6 radeonsi: don't do an L2 flush in compute_do_clear_or_copy if we're not syncing
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák aed881e34e radeonsi: reduce syncing in si_compute_expand_fmask when it's already idle
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 5c827bde29 radeonsi: reduce syncing for initializing new buffers
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 207bafd4dd radeonsi: reduce syncing in si_dcc_decompress
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 7e2b5ce722 radeonsi: set compute/cpdma sync flags in the outermost caller
This allows us to control syncing everywhere.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák a4ad08b455 radeonsi: inline clear_buffer in si_screen_clear_buffer
We'll add a new parameter there.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 1af99a28a0 radeonsi: merge CP DMA flags with internal compute flags
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák dd5e9af78f radeonsi: remove unused SI_CP_DMA_SKIP_* definitions
The existing uses had no effect.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 938dc0e291 radeonsi: rename internal compute sync flags
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 69ff9c16bb radeonsi: never set DISABLE_WR_CONFIRM for CP DMA clears and copies
Only prefetches set it. Unsynchronized clears and copies shouldn't set it
because syncing later wouldn't wait for the writes.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00