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intel: Rename GEN_VERSIONx10 macro to GFX_VERx10 

Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_VERSION" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_VERSION/GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
This commit is contained in:
Anuj Phogat 2021-03-16 10:09:00 -07:00 committed by Marge Bot
parent b9b4324ca3
commit 295bb3c263
24 changed files with 192 additions and 192 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/gallium/drivers/iris/Android.mk
View File

@ -50,7 +50,7 @@ LOCAL_MODULE := libmesa_iris_gen8
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(LIBIRIS_SRC_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=80
LOCAL_CFLAGS := -DGFX_VERx10=80
LOCAL_C_INCLUDES := $(IRIS_COMMON_INCLUDES)
@ -70,7 +70,7 @@ LOCAL_MODULE := libmesa_iris_gen9
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(LIBIRIS_SRC_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=90
LOCAL_CFLAGS := -DGFX_VERx10=90
LOCAL_C_INCLUDES := $(IRIS_COMMON_INCLUDES)
@ -90,7 +90,7 @@ LOCAL_MODULE := libmesa_iris_gen11
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(LIBIRIS_SRC_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=110
LOCAL_CFLAGS := -DGFX_VERx10=110
LOCAL_C_INCLUDES := $(IRIS_COMMON_INCLUDES)
@ -110,7 +110,7 @@ LOCAL_MODULE := libmesa_iris_gen12
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(LIBIRIS_SRC_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=120
LOCAL_CFLAGS := -DGFX_VERx10=120
LOCAL_C_INCLUDES := $(IRIS_COMMON_INCLUDES)
@ -130,7 +130,7 @@ LOCAL_MODULE := libmesa_iris_gen125
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(LIBIRIS_SRC_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=125
LOCAL_CFLAGS := -DGFX_VERx10=125
LOCAL_C_INCLUDES := $(IRIS_COMMON_INCLUDES)

18
src/gallium/drivers/iris/iris_state.c
View File

@ -870,7 +870,7 @@ gen11_upload_pixel_hashing_tables(struct iris_batch *batch)
mode.SliceHashingTableEnable = true;
}
}
#elif GEN_VERSIONx10 == 120
#elif GFX_VERx10 == 120
static void
gen12_upload_pixel_hashing_tables(struct iris_batch *batch)
{
@ -1036,7 +1036,7 @@ iris_init_render_context(struct iris_batch *batch)
gen11_upload_pixel_hashing_tables(batch);
#endif
#if GEN_VERSIONx10 == 120
#if GFX_VERx10 == 120
gen12_upload_pixel_hashing_tables(batch);
#endif
@ -4567,7 +4567,7 @@ iris_store_cs_state(const struct gen_device_info *devinfo,
void *map = shader->derived_data;
iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA), map, desc) {
#if GEN_VERSIONx10 < 125
#if GFX_VERx10 < 125
desc.ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs;
desc.CrossThreadConstantDataReadLength =
cs_prog_data->push.cross_thread.regs;
@ -5283,7 +5283,7 @@ iris_restore_compute_saved_bos(struct iris_context *ice,
struct iris_bo *bo = iris_resource_bo(shader->assembly.res);
iris_use_pinned_bo(batch, bo, false, IRIS_DOMAIN_NONE);
if (GEN_VERSIONx10 < 125) {
if (GFX_VERx10 < 125) {
struct iris_bo *curbe_bo =
iris_resource_bo(ice->state.last_res.cs_thread_ids);
iris_use_pinned_bo(batch, curbe_bo, false, IRIS_DOMAIN_NONE);
@ -6801,7 +6801,7 @@ iris_load_indirect_location(struct iris_context *ice,
}
}
#if GEN_VERSIONx10 >= 125
#if GFX_VERx10 >= 125
static void
iris_upload_compute_walker(struct iris_context *ice,
@ -6863,7 +6863,7 @@ iris_upload_compute_walker(struct iris_context *ice,
}
#else /* #if GEN_VERSIONx10 >= 125 */
#else /* #if GFX_VERx10 >= 125 */
static void
iris_upload_gpgpu_walker(struct iris_context *ice,
@ -7012,7 +7012,7 @@ iris_upload_gpgpu_walker(struct iris_context *ice,
iris_emit_cmd(batch, GENX(MEDIA_STATE_FLUSH), msf);
}
#endif /* #if GEN_VERSIONx10 >= 125 */
#endif /* #if GFX_VERx10 >= 125 */
static void
iris_upload_compute_state(struct iris_context *ice,
@ -7057,7 +7057,7 @@ iris_upload_compute_state(struct iris_context *ice,
genX(invalidate_aux_map_state)(batch);
#endif
#if GEN_VERSIONx10 >= 125
#if GFX_VERx10 >= 125
iris_upload_compute_walker(ice, batch, grid);
#else
iris_upload_gpgpu_walker(ice, batch, grid);
@ -7988,7 +7988,7 @@ iris_set_frontend_noop(struct pipe_context *ctx, bool enable)
void
genX(init_screen_state)(struct iris_screen *screen)
{
assert(screen->devinfo.genx10 == GEN_VERSIONx10);
assert(screen->devinfo.genx10 == GFX_VERx10);
screen->vtbl.destroy_state = iris_destroy_state;
screen->vtbl.init_render_context = iris_init_render_context;
screen->vtbl.init_compute_context = iris_init_compute_context;

2
src/gallium/drivers/iris/meson.build
View File

@ -65,7 +65,7 @@ foreach v : ['80', '90', '110', '120', '125']
include_directories : [inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_gallium_aux, inc_intel],
c_args : [
no_override_init_args, c_sse2_args,
'-DGEN_VERSIONx10=@0@'.format(v),
'-DGFX_VERx10=@0@'.format(v),
],
gnu_symbol_visibility : 'hidden',
dependencies : [dep_libdrm, dep_valgrind, idep_nir_headers],

20
src/intel/Android.isl.mk
View File

@ -38,7 +38,7 @@ LOCAL_MODULE := libmesa_isl_gen4
LOCAL_SRC_FILES := $(ISL_GEN4_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=40
LOCAL_CFLAGS := -DGFX_VERx10=40
LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
@ -57,7 +57,7 @@ LOCAL_MODULE := libmesa_isl_gen5
LOCAL_SRC_FILES := $(ISL_GEN5_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=50
LOCAL_CFLAGS := -DGFX_VERx10=50
LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
@ -76,7 +76,7 @@ LOCAL_MODULE := libmesa_isl_gen6
LOCAL_SRC_FILES := $(ISL_GEN6_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=60
LOCAL_CFLAGS := -DGFX_VERx10=60
LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
@ -95,7 +95,7 @@ LOCAL_MODULE := libmesa_isl_gen7
LOCAL_SRC_FILES := $(ISL_GEN7_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=70
LOCAL_CFLAGS := -DGFX_VERx10=70
LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
@ -114,7 +114,7 @@ LOCAL_MODULE := libmesa_isl_gen75
LOCAL_SRC_FILES := $(ISL_GEN75_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=75
LOCAL_CFLAGS := -DGFX_VERx10=75
LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
@ -133,7 +133,7 @@ LOCAL_MODULE := libmesa_isl_gen8
LOCAL_SRC_FILES := $(ISL_GEN8_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=80
LOCAL_CFLAGS := -DGFX_VERx10=80
LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
@ -152,7 +152,7 @@ LOCAL_MODULE := libmesa_isl_gen9
LOCAL_SRC_FILES := $(ISL_GEN9_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=90
LOCAL_CFLAGS := -DGFX_VERx10=90
LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
@ -171,7 +171,7 @@ LOCAL_MODULE := libmesa_isl_gen11
LOCAL_SRC_FILES := $(ISL_GEN11_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=110
LOCAL_CFLAGS := -DGFX_VERx10=110
LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
@ -190,7 +190,7 @@ LOCAL_MODULE := libmesa_isl_gen12
LOCAL_SRC_FILES := $(ISL_GEN12_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=120
LOCAL_CFLAGS := -DGFX_VERx10=120
LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
@ -209,7 +209,7 @@ LOCAL_MODULE := libmesa_isl_gen125
LOCAL_SRC_FILES := $(ISL_GEN125_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=125
LOCAL_CFLAGS := -DGFX_VERx10=125
LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)

14
src/intel/Android.vulkan.mk
View File

@ -71,7 +71,7 @@ LOCAL_MODULE := libmesa_anv_gen7
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(VULKAN_GEN7_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=70
LOCAL_CFLAGS := -DGFX_VERx10=70
LOCAL_C_INCLUDES := $(VULKAN_COMMON_INCLUDES)
@ -92,7 +92,7 @@ LOCAL_MODULE := libmesa_anv_gen75
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(VULKAN_GEN75_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=75
LOCAL_CFLAGS := -DGFX_VERx10=75
LOCAL_C_INCLUDES := $(VULKAN_COMMON_INCLUDES)
@ -113,7 +113,7 @@ LOCAL_MODULE := libmesa_anv_gen8
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(VULKAN_GEN8_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=80
LOCAL_CFLAGS := -DGFX_VERx10=80
LOCAL_C_INCLUDES := $(VULKAN_COMMON_INCLUDES)
@ -134,7 +134,7 @@ LOCAL_MODULE := libmesa_anv_gen9
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(VULKAN_GEN9_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=90
LOCAL_CFLAGS := -DGFX_VERx10=90
LOCAL_C_INCLUDES := $(VULKAN_COMMON_INCLUDES)
@ -155,7 +155,7 @@ LOCAL_MODULE := libmesa_anv_gen11
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(VULKAN_GEN11_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=110
LOCAL_CFLAGS := -DGFX_VERx10=110
LOCAL_C_INCLUDES := $(VULKAN_COMMON_INCLUDES)
@ -176,7 +176,7 @@ LOCAL_MODULE := libmesa_anv_gen12
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(VULKAN_GEN12_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=120
LOCAL_CFLAGS := -DGFX_VERx10=120
LOCAL_C_INCLUDES := $(VULKAN_COMMON_INCLUDES)
@ -197,7 +197,7 @@ LOCAL_MODULE := libmesa_anv_gen125
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
LOCAL_SRC_FILES := $(VULKAN_GEN125_FILES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=125
LOCAL_CFLAGS := -DGFX_VERx10=125
LOCAL_C_INCLUDES := $(VULKAN_COMMON_INCLUDES)

4
src/intel/blorp/blorp_genX_exec.h
View File

@ -227,7 +227,7 @@ emit_urb_config(struct blorp_batch *batch,
false, false, entry_size,
entries, start, deref_block_size, &constrained);
#if GEN_VERSIONx10 == 70
#if GFX_VERx10 == 70
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
*
* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
@ -958,7 +958,7 @@ blorp_emit_ps_config(struct blorp_batch *batch,
ps.MaximumNumberofThreads =
batch->blorp->isl_dev->info->max_wm_threads - 1;
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
ps.SampleMask = 1;
#endif

2
src/intel/common/meson.build
View File

@ -84,7 +84,7 @@ if install_intel_gpu_tests
files('tests/mi_builder_test.cpp'),
cpp_args : [
cpp_msvc_compat_args,
'-DGEN_VERSIONx10=@0@'.format(g[0])
'-DGFX_VERx10=@0@'.format(g[0])
],
gnu_symbol_visibility : 'hidden',
include_directories : [inc_include, inc_src, inc_intel],

52
src/intel/common/mi_builder.h
View File

@ -96,7 +96,7 @@ struct mi_value {
uint32_t reg;
};
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
bool invert;
#endif
};
@ -132,7 +132,7 @@ struct mi_builder {
const struct gen_device_info *devinfo;
__gen_user_data *user_data;
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
uint32_t gprs;
uint8_t gpr_refs[MI_BUILDER_NUM_ALLOC_GPRS];
@ -150,7 +150,7 @@ mi_builder_init(struct mi_builder *b,
b->devinfo = devinfo;
b->user_data = user_data;
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
b->gprs = 0;
b->num_math_dwords = 0;
#endif
@ -159,7 +159,7 @@ mi_builder_init(struct mi_builder *b,
static inline void
mi_builder_flush_math(struct mi_builder *b)
{
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
if (b->num_math_dwords == 0)
return;
@ -177,7 +177,7 @@ mi_builder_flush_math(struct mi_builder *b)
/* The actual hardware limit on GPRs */
#define _MI_BUILDER_NUM_HW_GPRS 16
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
static inline bool
mi_value_is_reg(struct mi_value val)
@ -226,7 +226,7 @@ mi_new_gpr(struct mi_builder *b)
.reg = _MI_BUILDER_GPR_BASE + gpr * 8,
};
}
#endif /* GEN_VERSIONx10 >= 75 */
#endif /* GFX_VERx10 >= 75 */
/** Take a reference to a mi_value
*
@ -241,7 +241,7 @@ mi_new_gpr(struct mi_builder *b)
static inline struct mi_value
mi_value_ref(struct mi_builder *b, struct mi_value val)
{
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
if (_mi_value_is_allocated_gpr(val)) {
unsigned gpr = _mi_value_as_gpr(val);
assert(gpr < MI_BUILDER_NUM_ALLOC_GPRS);
@ -249,7 +249,7 @@ mi_value_ref(struct mi_builder *b, struct mi_value val)
assert(b->gpr_refs[gpr] < UINT8_MAX);
b->gpr_refs[gpr]++;
}
#endif /* GEN_VERSIONx10 >= 75 */
#endif /* GFX_VERx10 >= 75 */
return val;
}
@ -261,7 +261,7 @@ mi_value_ref(struct mi_builder *b, struct mi_value val)
static inline void
mi_value_unref(struct mi_builder *b, struct mi_value val)
{
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
if (_mi_value_is_allocated_gpr(val)) {
unsigned gpr = _mi_value_as_gpr(val);
assert(gpr < MI_BUILDER_NUM_ALLOC_GPRS);
@ -270,7 +270,7 @@ mi_value_unref(struct mi_builder *b, struct mi_value val)
if (--b->gpr_refs[gpr] == 0)
b->gprs &= ~(1u << gpr);
}
#endif /* GEN_VERSIONx10 >= 75 */
#endif /* GFX_VERx10 >= 75 */
}
static inline struct mi_value
@ -289,7 +289,7 @@ mi_reg32(uint32_t reg)
.type = MI_VALUE_TYPE_REG32,
.reg = reg,
};
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
assert(!_mi_value_is_allocated_gpr(val));
#endif
return val;
@ -302,7 +302,7 @@ mi_reg64(uint32_t reg)
.type = MI_VALUE_TYPE_REG64,
.reg = reg,
};
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
assert(!_mi_value_is_allocated_gpr(val));
#endif
return val;
@ -365,7 +365,7 @@ static inline void
_mi_copy_no_unref(struct mi_builder *b,
struct mi_value dst, struct mi_value src)
{
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
/* TODO: We could handle src.invert by emitting a bit of math if we really
* wanted to.
*/
@ -455,7 +455,7 @@ _mi_copy_no_unref(struct mi_builder *b,
cmm.DestinationMemoryAddress = dst.addr;
cmm.SourceMemoryAddress = src.addr;
}
#elif GEN_VERSIONx10 == 75
#elif GFX_VERx10 == 75
{
struct mi_value tmp = mi_new_gpr(b);
_mi_copy_no_unref(b, tmp, src);
@ -511,7 +511,7 @@ _mi_copy_no_unref(struct mi_builder *b,
case MI_VALUE_TYPE_REG32:
case MI_VALUE_TYPE_REG64:
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
if (src.reg != dst.reg) {
mi_builder_emit(b, GENX(MI_LOAD_REGISTER_REG), lrr) {
struct mi_reg_num reg = mi_adjust_reg_num(src.reg);
@ -541,7 +541,7 @@ _mi_copy_no_unref(struct mi_builder *b,
}
}
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
static inline struct mi_value
mi_resolve_invert(struct mi_builder *b, struct mi_value src);
#endif
@ -557,7 +557,7 @@ mi_resolve_invert(struct mi_builder *b, struct mi_value src);
static inline void
mi_store(struct mi_builder *b, struct mi_value dst, struct mi_value src)
{
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
src = mi_resolve_invert(b, src);
#endif
_mi_copy_no_unref(b, dst, src);
@ -569,7 +569,7 @@ static inline void
mi_memset(struct mi_builder *b, __gen_address_type dst,
uint32_t value, uint32_t size)
{
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
assert(b->num_math_dwords == 0);
#endif
@ -587,7 +587,7 @@ static inline void
mi_memcpy(struct mi_builder *b, __gen_address_type dst,
__gen_address_type src, uint32_t size)
{
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
assert(b->num_math_dwords == 0);
#endif
@ -597,7 +597,7 @@ mi_memcpy(struct mi_builder *b, __gen_address_type dst,
for (uint32_t i = 0; i < size; i += 4) {
struct mi_value dst_val = mi_mem32(__gen_address_offset(dst, i));
struct mi_value src_val = mi_mem32(__gen_address_offset(src, i));
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
mi_store(b, dst_val, src_val);
#else
/* IVB does not have a general purpose register for command streamer
@ -614,7 +614,7 @@ mi_memcpy(struct mi_builder *b, __gen_address_type dst,
* MI_MATH Section. Only available on Haswell+
*/
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
/**
* Perform a predicated store (assuming the condition is already loaded
@ -902,7 +902,7 @@ mi_ior(struct mi_builder *b,
MI_ALU_STORE, MI_ALU_ACCU);
}
#if GEN_VERSIONx10 >= 125
#if GFX_VERx10 >= 125
static inline struct mi_value
mi_ishl(struct mi_builder *b, struct mi_value src0, struct mi_value src1)
{
@ -995,7 +995,7 @@ mi_ishr_imm(struct mi_builder *b, struct mi_value src, uint32_t shift)
return res;
}
#endif /* if GEN_VERSIONx10 >= 125 */
#endif /* if GFX_VERx10 >= 125 */
static inline struct mi_value
mi_imul_imm(struct mi_builder *b, struct mi_value src, uint32_t N)
@ -1041,7 +1041,7 @@ mi_ishl_imm(struct mi_builder *b, struct mi_value src, uint32_t shift)
struct mi_value res = mi_value_to_gpr(b, src);
#if GEN_VERSIONx10 >= 125
#if GFX_VERx10 >= 125
/* Annoyingly, we only have power-of-two shifts */
while (shift) {
int bit = u_bit_scan(&shift);
@ -1191,7 +1191,7 @@ _mi_resolve_address_token(struct mi_builder *b,
#endif /* MI_BUILDER_CAN_WRITE_BATCH */
#if GEN_VERSIONx10 >= 125
#if GFX_VERx10 >= 125
/*
* Indirect load/store. Only available on GFX 12.5+
@ -1366,6 +1366,6 @@ mi_goto_target_init_and_place(struct mi_builder *b)
#define mi_continue(b) mi_goto(b, &__continue)
#define mi_continue_if(b, cond) mi_goto_if(b, cond, &__continue)
#endif /* GEN_VERSIONx10 >= 125 */
#endif /* GFX_VERx10 >= 125 */
#endif /* MI_BUILDER_H */

18
src/intel/common/tests/mi_builder_test.cpp
View File

@ -55,7 +55,7 @@ __gen_address_offset(address addr, uint64_t offset)
return addr;
}
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
#define RSVD_TEMP_REG 0x2678 /* MI_ALU_REG15 */
#else
#define RSVD_TEMP_REG 0x2430 /* GEN7_3DPRIM_START_VERTEX */
@ -194,7 +194,7 @@ mi_builder_test::SetUp()
(void *)&getparam), 0) << strerror(errno);
ASSERT_TRUE(gen_get_device_info_from_pci_id(device_id, &devinfo));
if (devinfo.gen != GEN_GEN || devinfo.is_haswell != (GEN_VERSIONx10 == 75)) {
if (devinfo.gen != GEN_GEN || devinfo.is_haswell != (GFX_VERx10 == 75)) {
close(fd);
fd = -1;
continue;
@ -412,7 +412,7 @@ TEST_F(mi_builder_test, imm_mem)
}
/* mem -> mem copies are only supported on HSW+ */
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
TEST_F(mi_builder_test, mem_mem)
{
const uint64_t value = 0x0123456789abcdef;
@ -532,7 +532,7 @@ TEST_F(mi_builder_test, memcpy)
}
/* Start of MI_MATH section */
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
#define EXPECT_EQ_IMM(x, imm) EXPECT_EQ(x, mi_value_to_u64(imm))
@ -708,7 +708,7 @@ TEST_F(mi_builder_test, iand)
mi_imm(values[1])));
}
#if GEN_VERSIONx10 >= 125
#if GFX_VERx10 >= 125
TEST_F(mi_builder_test, ishl)
{
const uint64_t value = 0x0123456789abcdef;
@ -814,7 +814,7 @@ TEST_F(mi_builder_test, ishr_imm)
mi_ishr_imm(&b, mi_imm(value), i));
}
}
#endif /* if GEN_VERSIONx10 >= 125 */
#endif /* if GFX_VERx10 >= 125 */
TEST_F(mi_builder_test, imul_imm)
{
@ -953,9 +953,9 @@ TEST_F(mi_builder_test, store_if)
EXPECT_EQ(*(uint32_t *)(output + 12), (uint32_t)canary);
}
#endif /* GEN_VERSIONx10 >= 75 */
#endif /* GFX_VERx10 >= 75 */
#if GEN_VERSIONx10 >= 125
#if GFX_VERx10 >= 125
/*
* Indirect load/store tests. Only available on GFX 12.5+
@ -1180,4 +1180,4 @@ TEST_F(mi_builder_test, loop_continue_if)
EXPECT_EQ(*(uint64_t *)(output + 0), loop_count);
EXPECT_EQ(*(uint64_t *)(output + 8), 10);
}
#endif /* GEN_VERSIONx10 >= 125 */
#endif /* GFX_VERx10 >= 125 */

26
src/intel/genxml/genX_pack.h
View File

@ -24,31 +24,31 @@
#ifndef GENX_PACK_H
#define GENX_PACK_H
#ifndef GEN_VERSIONx10
# error "The GEN_VERSIONx10 macro must be defined"
#ifndef GFX_VERx10
# error "The GFX_VERx10 macro must be defined"
#endif
#if (GEN_VERSIONx10 == 40)
#if (GFX_VERx10 == 40)
# include "genxml/gen4_pack.h"
#elif (GEN_VERSIONx10 == 45)
#elif (GFX_VERx10 == 45)
# include "genxml/gen45_pack.h"
#elif (GEN_VERSIONx10 == 50)
#elif (GFX_VERx10 == 50)
# include "genxml/gen5_pack.h"
#elif (GEN_VERSIONx10 == 60)
#elif (GFX_VERx10 == 60)
# include "genxml/gen6_pack.h"
#elif (GEN_VERSIONx10 == 70)
#elif (GFX_VERx10 == 70)
# include "genxml/gen7_pack.h"
#elif (GEN_VERSIONx10 == 75)
#elif (GFX_VERx10 == 75)
# include "genxml/gen75_pack.h"
#elif (GEN_VERSIONx10 == 80)
#elif (GFX_VERx10 == 80)
# include "genxml/gen8_pack.h"
#elif (GEN_VERSIONx10 == 90)
#elif (GFX_VERx10 == 90)
# include "genxml/gen9_pack.h"
#elif (GEN_VERSIONx10 == 110)
#elif (GFX_VERx10 == 110)
# include "genxml/gen11_pack.h"
#elif (GEN_VERSIONx10 == 120)
#elif (GFX_VERx10 == 120)
# include "genxml/gen12_pack.h"
#elif (GEN_VERSIONx10 == 125)
#elif (GFX_VERx10 == 125)
# include "genxml/gen125_pack.h"
#else
# error "Need to add a pack header include for this gen"

32
src/intel/genxml/gen_macros.h
View File

@ -31,7 +31,7 @@
*
* You can do pseudo-runtime checks in your function such as
*
* if (GEN_VERSIONx10 == 75) {
* if (GFX_VERx10 == 75) {
* // Do something
* }
*
@ -41,7 +41,7 @@
* For places where you really do have a compile-time conflict, you can
* use preprocessor logic:
*
* #if (GEN_VERSIONx10 == 75)
* #if (GFX_VERx10 == 75)
* // Do something
* #endif
*
@ -52,44 +52,44 @@
/* Base macro defined on the command line. If we don't have this, we can't
* do anything.
*/
#ifndef GEN_VERSIONx10
# error "The GEN_VERSIONx10 macro must be defined"
#ifndef GFX_VERx10
# error "The GFX_VERx10 macro must be defined"
#endif
#define GEN_GEN ((GEN_VERSIONx10) / 10)
#define GEN_GEN ((GFX_VERx10) / 10)
/* Prefixing macros */
#if (GEN_VERSIONx10 == 40)
#if (GFX_VERx10 == 40)
# define GENX(X) GEN4_##X
# define genX(x) gen4_##x
#elif (GEN_VERSIONx10 == 45)
#elif (GFX_VERx10 == 45)
# define GENX(X) GEN45_##X
# define genX(x) gen45_##x
#elif (GEN_VERSIONx10 == 50)
#elif (GFX_VERx10 == 50)
# define GENX(X) GEN5_##X
# define genX(x) gen5_##x
#elif (GEN_VERSIONx10 == 60)
#elif (GFX_VERx10 == 60)
# define GENX(X) GEN6_##X
# define genX(x) gen6_##x
#elif (GEN_VERSIONx10 == 70)
#elif (GFX_VERx10 == 70)
# define GENX(X) GEN7_##X
# define genX(x) gen7_##x
#elif (GEN_VERSIONx10 == 75)
#elif (GFX_VERx10 == 75)
# define GENX(X) GEN75_##X
# define genX(x) gen75_##x
#elif (GEN_VERSIONx10 == 80)
#elif (GFX_VERx10 == 80)
# define GENX(X) GEN8_##X
# define genX(x) gen8_##x
#elif (GEN_VERSIONx10 == 90)
#elif (GFX_VERx10 == 90)
# define GENX(X) GEN9_##X
# define genX(x) gen9_##x
#elif (GEN_VERSIONx10 == 110)
#elif (GFX_VERx10 == 110)
# define GENX(X) GEN11_##X
# define genX(x) gen11_##x
#elif (GEN_VERSIONx10 == 120)
#elif (GFX_VERx10 == 120)
# define GENX(X) GEN12_##X
# define genX(x) gen12_##x
#elif (GEN_VERSIONx10 == 125)
#elif (GFX_VERx10 == 125)
# define GENX(X) GEN125_##X
# define genX(x) gen125_##x
#else

2
src/intel/isl/isl_emit_depth_stencil.c
View File

@ -169,7 +169,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
sb.StencilCompressionEnable =
info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS;
sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
#elif GEN_VERSIONx10 >= 75
#elif GFX_VERx10 >= 75
sb.StencilBufferEnable = true;
#endif
sb.SurfaceBaseAddress = info->stencil_address;

10
src/intel/isl/isl_surface_state.c
View File

@ -324,7 +324,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
assert(info->write_disables == 0);
#endif
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
s.IntegerSurfaceFormat =
isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
#endif
@ -363,7 +363,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
*
* This restriction appears to exist only on Ivy Bridge.
*/
if (GEN_VERSIONx10 == 70 && !ISL_DEV_IS_BAYTRAIL(dev) &&
if (GFX_VERx10 == 70 && !ISL_DEV_IS_BAYTRAIL(dev) &&
(info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
info->surf->samples > 1)
assert(info->view->base_array_layer == 0);
@ -529,7 +529,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
#endif
#endif
#if (GEN_VERSIONx10 >= 75)
#if (GFX_VERx10 >= 75)
if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
@ -547,7 +547,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
s.MOCS = info->mocs;
#endif
#if GEN_VERSIONx10 >= 45
#if GFX_VERx10 >= 45
if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
/* There are fairly strict rules about when the offsets can be used.
* These are mostly taken from the Sky Lake PRM documentation for
@ -917,7 +917,7 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
s.MOCS = info->mocs;
#endif
#if (GEN_VERSIONx10 >= 75)
#if (GFX_VERx10 >= 75)
s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;

2
src/intel/isl/meson.build
View File

@ -71,7 +71,7 @@ foreach g : [['40', isl_gen4_files], ['50', []], ['60', isl_gen6_files],
dependencies : idep_mesautil,
c_args : [
no_override_init_args,
'-DGEN_VERSIONx10=@0@'.format(_gen)
'-DGFX_VERx10=@0@'.format(_gen)
],
gnu_symbol_visibility : 'hidden',
)

8
src/intel/vulkan/gen7_cmd_buffer.c
View File

@ -33,7 +33,7 @@
#include "genxml/gen_macros.h"
#include "genxml/genX_pack.h"
#if GEN_VERSIONx10 == 70
#if GFX_VERx10 == 70
static int64_t
clamp_int64(int64_t x, int64_t min, int64_t max)
{
@ -163,7 +163,7 @@ void genX(CmdBindIndexBuffer)(
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
if (GEN_VERSIONx10 == 75)
if (GFX_VERx10 == 75)
cmd_buffer->state.restart_index = restart_index_for_type(indexType);
cmd_buffer->state.gfx.gen7.index_buffer = buffer;
cmd_buffer->state.gfx.gen7.index_type = vk_to_gen_index_type(indexType);
@ -312,7 +312,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
struct anv_buffer *buffer = cmd_buffer->state.gfx.gen7.index_buffer;
uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset;
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart;
vf.CutIndex = cmd_buffer->state.restart_index;
@ -320,7 +320,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
#endif
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
#if GEN_VERSIONx10 != 75
#if GFX_VERx10 != 75
ib.CutIndexEnable = pipeline->primitive_restart;
#endif
ib.IndexFormat = cmd_buffer->state.gfx.gen7.index_type;

52
src/intel/vulkan/genX_cmd_buffer.c
View File

@ -759,7 +759,7 @@ set_image_fast_clear_state(struct anv_cmd_buffer *cmd_buffer,
/* This is only really practical on haswell and above because it requires
* MI math in order to get it correct.
*/
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
static void
anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
@ -840,7 +840,7 @@ anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
mip.CompareOperation = COMPARE_SRCS_EQUAL;
}
}
#endif /* GEN_VERSIONx10 >= 75 */
#endif /* GFX_VERx10 >= 75 */
#if GEN_GEN <= 8
static void
@ -931,7 +931,7 @@ anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer *cmd_buffer,
assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT);
assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
anv_cmd_compute_resolve_predicate(cmd_buffer, image,
aspect, 0, array_layer,
resolve_op, fast_clear_supported);
@ -1000,7 +1000,7 @@ init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer,
} else {
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
sdi.Address = addr;
if (GEN_VERSIONx10 >= 75) {
if (GFX_VERx10 >= 75) {
/* Pre-SKL, the dword containing the clear values also contains
* other fields, so we need to initialize those fields to match the
* values that would be in a color attachment.
@ -1682,7 +1682,7 @@ genX(BeginCommandBuffer)(
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
}
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
const VkCommandBufferInheritanceConditionalRenderingInfoEXT *conditional_rendering_info =
vk_find_struct_const(pBeginInfo->pInheritanceInfo->pNext, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT);
@ -1801,7 +1801,7 @@ genX(CmdExecuteCommands)(
assert(secondary->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY);
assert(!anv_batch_has_error(&secondary->batch));
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
if (secondary->state.conditional_render_enabled) {
if (!primary->state.conditional_render_enabled) {
/* Secondary buffer is constructed as if it will be executed
@ -2144,7 +2144,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
bits &= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES);
if (GEN_VERSIONx10 == 75) {
if (GFX_VERx10 == 75) {
/* Haswell needs addition work-arounds:
*
* From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
@ -2345,7 +2345,7 @@ cmd_buffer_alloc_push_constants(struct anv_cmd_buffer *cmd_buffer)
#if GEN_GEN >= 8
const unsigned push_constant_kb = 32;
#elif GEN_VERSIONx10 == 75
#elif GFX_VERx10 == 75
const unsigned push_constant_kb = cmd_buffer->device->info.gt == 3 ? 32 : 16;
#else
const unsigned push_constant_kb = 16;
@ -3053,7 +3053,7 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
c.MOCS = isl_mocs(&cmd_buffer->device->isl_dev, 0, false);
#endif
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
/* The Skylake PRM contains the following restriction:
*
* "The driver must ensure The following case does not occur
@ -3076,7 +3076,7 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
/* For Ivy Bridge, make sure we only set the first range (actual
* push constants)
*/
assert((GEN_VERSIONx10 >= 75) || i == 0);
assert((GFX_VERx10 >= 75) || i == 0);
c.ConstantBody.ReadLength[i + shift] = range->length;
c.ConstantBody.Buffer[i + shift] =
@ -3780,7 +3780,7 @@ void genX(CmdDrawIndirectByteCountEXT)(
uint32_t counterOffset,
uint32_t vertexStride)
{
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, counter_buffer, counterBuffer);
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
@ -3838,7 +3838,7 @@ void genX(CmdDrawIndirectByteCountEXT)(
}
update_dirty_vbs_for_gen8_vb_flush(cmd_buffer, SEQUENTIAL);
#endif /* GEN_VERSIONx10 >= 75 */
#endif /* GFX_VERx10 >= 75 */
}
static void
@ -3855,7 +3855,7 @@ load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer,
struct mi_value instance_count = mi_mem32(anv_address_add(addr, 4));
unsigned view_count = anv_subpass_view_count(cmd_buffer->state.subpass);
if (view_count > 1) {
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
instance_count = mi_imul_imm(&b, instance_count, view_count);
#else
anv_finishme("Multiview + indirect draw requires MI_MATH; "
@ -3987,7 +3987,7 @@ prepare_for_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
struct mi_value ret = mi_imm(0);
if (conditional_render_enabled) {
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
ret = mi_new_gpr(b);
mi_store(b, mi_value_ref(b, ret), mi_mem32(count_address));
#endif
@ -4032,7 +4032,7 @@ emit_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
}
}
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
static void
emit_draw_count_predicate_with_conditional_render(
struct anv_cmd_buffer *cmd_buffer,
@ -4094,7 +4094,7 @@ void genX(CmdDrawIndirectCount)(
for (uint32_t i = 0; i < maxDrawCount; i++) {
struct anv_address draw = anv_address_add(buffer->address, offset);
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
if (cmd_state->conditional_render_enabled) {
emit_draw_count_predicate_with_conditional_render(
cmd_buffer, &b, i, mi_value_ref(&b, max));
@ -4165,7 +4165,7 @@ void genX(CmdDrawIndexedIndirectCount)(
for (uint32_t i = 0; i < maxDrawCount; i++) {
struct anv_address draw = anv_address_add(buffer->address, offset);
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
if (cmd_state->conditional_render_enabled) {
emit_draw_count_predicate_with_conditional_render(
cmd_buffer, &b, i, mi_value_ref(&b, max));
@ -4352,7 +4352,7 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
&pipeline->cs, 1);
cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
#if GEN_VERSIONx10 < 125
#if GFX_VERx10 < 125
uint32_t iface_desc_data_dw[GENX(INTERFACE_DESCRIPTOR_DATA_length)];
struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = {
.BindingTablePointer =
@ -4381,7 +4381,7 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
comp_state->push_data =
anv_cmd_buffer_cs_push_constants(cmd_buffer);
#if GEN_VERSIONx10 < 125
#if GFX_VERx10 < 125
if (comp_state->push_data.alloc_size) {
anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
curbe.CURBETotalDataLength = comp_state->push_data.alloc_size;
@ -4448,7 +4448,7 @@ void genX(CmdDispatch)(
genX(CmdDispatchBase)(commandBuffer, 0, 0, 0, x, y, z);
}
#if GEN_VERSIONx10 >= 125
#if GFX_VERx10 >= 125
static inline void
emit_compute_walker(struct anv_cmd_buffer *cmd_buffer,
@ -4490,7 +4490,7 @@ emit_compute_walker(struct anv_cmd_buffer *cmd_buffer,
}
}
#else /* #if GEN_VERSIONx10 >= 125 */
#else /* #if GFX_VERx10 >= 125 */
static inline void
emit_gpgpu_walker(struct anv_cmd_buffer *cmd_buffer,
@ -4520,7 +4520,7 @@ emit_gpgpu_walker(struct anv_cmd_buffer *cmd_buffer,
anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH), msf);
}
#endif /* #if GEN_VERSIONx10 >= 125 */
#endif /* #if GFX_VERx10 >= 125 */
static inline void
emit_cs_walker(struct anv_cmd_buffer *cmd_buffer,
@ -4529,7 +4529,7 @@ emit_cs_walker(struct anv_cmd_buffer *cmd_buffer,
uint32_t groupCountX, uint32_t groupCountY,
uint32_t groupCountZ)
{
#if GEN_VERSIONx10 >= 125
#if GFX_VERx10 >= 125
emit_compute_walker(cmd_buffer, pipeline, indirect, prog_data, groupCountX,
groupCountY, groupCountZ);
#else
@ -4674,7 +4674,7 @@ void genX(CmdDispatchIndirect)(
mip.CompareOperation = COMPARE_FALSE;
}
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
if (cmd_buffer->state.conditional_render_enabled) {
/* predicate &= !(conditional_rendering_predicate == 0); */
mi_store(&b, mi_reg32(MI_PREDICATE_SRC0),
@ -6049,7 +6049,7 @@ void genX(CmdEndRenderPass2)(
void
genX(cmd_emit_conditional_render_predicate)(struct anv_cmd_buffer *cmd_buffer)
{
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
struct mi_builder b;
mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
@ -6065,7 +6065,7 @@ genX(cmd_emit_conditional_render_predicate)(struct anv_cmd_buffer *cmd_buffer)
#endif
}
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
void genX(CmdBeginConditionalRenderingEXT)(
VkCommandBuffer commandBuffer,
const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)

18
src/intel/vulkan/genX_pipeline.c
View File

@ -280,7 +280,7 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
entry_size, entries, start, deref_block_size,
&constrained);
#if GEN_VERSIONx10 == 70
#if GFX_VERx10 == 70
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
*
* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
@ -611,7 +611,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline,
sf.VertexSubPixelPrecisionSelect = _8Bit;
sf.AALineDistanceMode = true;
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
sf.LineStippleEnable = line_info && line_info->stippledLineEnable;
#endif
@ -2076,7 +2076,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
ps.DualSourceBlendEnable = dual_src_blend;
#endif
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
/* Haswell requires the sample mask to be set in this packet as well
* as in 3DSTATE_SAMPLE_MASK; the values should match.
*/
@ -2365,7 +2365,7 @@ genX(graphics_pipeline_create)(
return pipeline->base.batch.status;
}
#if GEN_VERSIONx10 >= 125
#if GFX_VERx10 >= 125
static void
emit_compute_state(struct anv_compute_pipeline *pipeline,
@ -2390,7 +2390,7 @@ emit_compute_state(struct anv_compute_pipeline *pipeline,
}
}
#else /* #if GEN_VERSIONx10 >= 125 */
#else /* #if GFX_VERx10 >= 125 */
static void
emit_compute_state(struct anv_compute_pipeline *pipeline,
@ -2438,7 +2438,7 @@ emit_compute_state(struct anv_compute_pipeline *pipeline,
*/
vfe.PerThreadScratchSpace =
ffs(cs_bin->prog_data->total_scratch) - 11;
} else if (GEN_VERSIONx10 == 75) {
} else if (GFX_VERx10 == 75) {
/* Haswell's Per Thread Scratch Space is in the range [0, 10]
* where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
*/
@ -2471,11 +2471,11 @@ emit_compute_state(struct anv_compute_pipeline *pipeline,
.SharedLocalMemorySize =
encode_slm_size(GEN_GEN, cs_prog_data->base.total_shared),
#if GEN_VERSIONx10 != 75
#if GFX_VERx10 != 75
.ConstantURBEntryReadOffset = 0,
#endif
.ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs,
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
.CrossThreadConstantDataReadLength =
cs_prog_data->push.cross_thread.regs,
#endif
@ -2499,7 +2499,7 @@ emit_compute_state(struct anv_compute_pipeline *pipeline,
&desc);
}
#endif /* #if GEN_VERSIONx10 >= 125 */
#endif /* #if GFX_VERx10 >= 125 */
static VkResult
compute_pipeline_create(

2
src/intel/vulkan/genX_query.c
View File

@ -1294,7 +1294,7 @@ void genX(CmdWriteTimestamp)(
}
}
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
#define MI_PREDICATE_SRC0 0x2400
#define MI_PREDICATE_SRC1 0x2408

14
src/intel/vulkan/genX_state.c
View File

@ -106,7 +106,7 @@ genX(emit_slice_hashing_state)(struct anv_device *device,
anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
mode.SliceHashingTableEnable = true;
}
#elif GEN_VERSIONx10 == 120
#elif GFX_VERx10 == 120
/* For each n calculate ppipes_of[n], equal to the number of pixel pipes
* present with n active dual subslices.
*/
@ -311,7 +311,7 @@ init_render_queue_state(struct anv_queue *queue)
void
genX(init_physical_device_state)(ASSERTED struct anv_physical_device *device)
{
assert(device->info.genx10 == GEN_VERSIONx10);
assert(device->info.genx10 == GFX_VERx10);
}
VkResult
@ -411,7 +411,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
l3sqc.ConvertIS_UC = !has_is;
l3sqc.ConvertC_UC = !has_c;
l3sqc.ConvertT_UC = !has_t;
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
l3sqc.L3SQGeneralPriorityCreditInitialization = SQGPCI_DEFAULT;
#else
l3sqc.L3SQGeneralPriorityCreditInitialization =
@ -424,7 +424,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
l3cr2.SLMEnable = cfg->n[INTEL_L3P_SLM];
l3cr2.URBLowBandwidth = urb_low_bw;
l3cr2.URBAllocation = cfg->n[INTEL_L3P_URB] - n0_urb;
#if !GEN_VERSIONx10 == 75
#if !GFX_VERx10 == 75
l3cr2.ALLAllocation = cfg->n[INTEL_L3P_ALL];
#endif
l3cr2.ROAllocation = cfg->n[INTEL_L3P_RO];
@ -440,7 +440,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
l3cr3.TLowBandwidth = 0;
}
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
if (device->physical->cmd_parser_version >= 4) {
/* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
* them disabled to avoid crashing the system hard.
@ -453,7 +453,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
c3.L3AtomicDisable = !has_dc;
}
}
#endif /* GEN_VERSIONx10 == 75 */
#endif /* GFX_VERx10 == 75 */
#endif /* GEN_GEN < 8 */
}
@ -657,7 +657,7 @@ VkResult genX(CreateSampler)(
vk_object_base_init(&device->vk, &sampler->base, VK_OBJECT_TYPE_SAMPLER);
sampler->n_planes = 1;
uint32_t border_color_stride = GEN_VERSIONx10 == 75 ? 512 : 64;
uint32_t border_color_stride = GFX_VERx10 == 75 ? 512 : 64;
uint32_t border_color_offset;
ASSERTED bool has_custom_color = false;
if (pCreateInfo->borderColor <= VK_BORDER_COLOR_INT_OPAQUE_WHITE) {

2
src/intel/vulkan/meson.build
View File

@ -70,7 +70,7 @@ foreach g : [['70', ['gen7_cmd_buffer.c']], ['75', ['gen7_cmd_buffer.c']],
],
c_args : [
no_override_init_args, c_sse2_args,
'-DGEN_VERSIONx10=@0@'.format(_gen),
'-DGFX_VERx10=@0@'.format(_gen),
],
gnu_symbol_visibility : 'hidden',
dependencies : [

18
src/mesa/drivers/dri/i965/Android.mk
View File

@ -66,7 +66,7 @@ LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=40
LOCAL_CFLAGS := -DGFX_VERx10=40
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@ -87,7 +87,7 @@ LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=45
LOCAL_CFLAGS := -DGFX_VERx10=45
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@ -108,7 +108,7 @@ LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=50
LOCAL_CFLAGS := -DGFX_VERx10=50
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@ -129,7 +129,7 @@ LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=60
LOCAL_CFLAGS := -DGFX_VERx10=60
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@ -150,7 +150,7 @@ LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=70
LOCAL_CFLAGS := -DGFX_VERx10=70
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@ -171,7 +171,7 @@ LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=75
LOCAL_CFLAGS := -DGFX_VERx10=75
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@ -192,7 +192,7 @@ LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=80
LOCAL_CFLAGS := -DGFX_VERx10=80
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@ -213,7 +213,7 @@ LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=90
LOCAL_CFLAGS := -DGFX_VERx10=90
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@ -234,7 +234,7 @@ LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
LOCAL_CFLAGS := -DGEN_VERSIONx10=110
LOCAL_CFLAGS := -DGFX_VERx10=110
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)

12
src/mesa/drivers/dri/i965/genX_pipe_control.c
View File

@ -65,7 +65,7 @@ get_post_sync_flags(enum pipe_control_flags flags)
/* Closed interval - GEN_GEN \in [x, y] */
#define IS_GEN_BETWEEN(x, y) (GEN_GEN >= x && GEN_GEN <= y)
#define IS_GENx10_BETWEEN(x, y) \
(GEN_VERSIONx10 >= x && GEN_VERSIONx10 <= y)
(GFX_VERx10 >= x && GFX_VERx10 <= y)
/**
* Emit a series of PIPE_CONTROL commands, taking into account any
@ -151,7 +151,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
}
}
if (GEN_VERSIONx10 < 75 && (flags & PIPE_CONTROL_DEPTH_STALL)) {
if (GFX_VERx10 < 75 && (flags & PIPE_CONTROL_DEPTH_STALL)) {
/* Project: PRE-HSW / Argument: Depth Stall
*
* "The following bits must be clear:
@ -178,7 +178,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
*/
}
if (GEN_VERSIONx10 < 75 && (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) {
if (GFX_VERx10 < 75 && (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) {
/* Project: PRE-HSW / Argument: Depth Cache Flush
*
* "Depth Stall must be clear ([13] of DW1)."
@ -230,7 +230,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
flags |= PIPE_CONTROL_CS_STALL;
}
if (GEN_VERSIONx10 == 75) {
if (GFX_VERx10 == 75) {
/* From the PIPE_CONTROL page itself:
*
* "HSW - Programming Note: PIPECONTROL with RO Cache Invalidation:
@ -407,7 +407,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
* don't skip the ones with only read-cache-invalidate bits set. This
* may or may not be a problem...
*/
if (GEN_VERSIONx10 == 70) {
if (GFX_VERx10 == 70) {
if (flags & PIPE_CONTROL_CS_STALL) {
/* If we're doing a CS stall, reset the counter and carry on. */
brw->pipe_controls_since_last_cs_stall = 0;
@ -499,7 +499,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
#if GEN_GEN >= 6
pc.TextureCacheInvalidationEnable =
flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
#elif GEN_GEN == 5 || GEN_VERSIONx10 == 45
#elif GEN_GEN == 5 || GFX_VERx10 == 45
pc.TextureCacheFlushEnable =
flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
#endif

44
src/mesa/drivers/dri/i965/genX_state_upload.c
View File

@ -583,7 +583,7 @@ genX(emit_vertices)(struct brw_context *brw)
* vertex element may poke over the end of the buffer by 2 bytes.
*/
const unsigned padding =
(GEN_VERSIONx10 < 75 && !devinfo->is_baytrail) * 2;
(GFX_VERx10 < 75 && !devinfo->is_baytrail) * 2;
const unsigned end = buffer->offset + buffer->size + padding;
dw = genX(emit_vertex_buffer_state)(brw, dw, i, buffer->bo,
buffer->offset,
@ -864,7 +864,7 @@ genX(emit_index_buffer)(struct brw_context *brw)
vf_invalidate_for_ib_48bit_transition(brw);
brw_batch_emit(brw, GENX(3DSTATE_INDEX_BUFFER), ib) {
#if GEN_VERSIONx10 < 75
#if GFX_VERx10 < 75
assert(brw->ib.enable_cut_index == brw->prim_restart.enable_cut_index);
ib.CutIndexEnable = brw->ib.enable_cut_index;
#endif
@ -897,7 +897,7 @@ static const struct brw_tracked_state genX(index_buffer) = {
.emit = genX(emit_index_buffer),
};
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
static void
genX(upload_cut_index)(struct brw_context *brw)
{
@ -1332,7 +1332,7 @@ genX(upload_clip_state)(struct brw_context *brw)
ctx->Transform.DepthClampFar);
/* _NEW_TRANSFORM */
if (GEN_GEN == 5 || GEN_VERSIONx10 == 45) {
if (GEN_GEN == 5 || GFX_VERx10 == 45) {
clip.UserClipDistanceClipTestEnableBitmask =
ctx->Transform.ClipPlanesEnabled;
} else {
@ -1352,7 +1352,7 @@ genX(upload_clip_state)(struct brw_context *brw)
clip.ClipMode = brw->clip.prog_data->clip_mode;
#if GEN_VERSIONx10 == 45
#if GFX_VERx10 == 45
clip.NegativeWClipTestEnable = true;
#endif
}
@ -1628,7 +1628,7 @@ genX(upload_sf)(struct brw_context *brw)
sf.CullMode = CULLMODE_NONE;
}
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
sf.LineStippleEnable = ctx->Line.StippleFlag;
#endif
@ -1679,7 +1679,7 @@ genX(upload_sf)(struct brw_context *brw)
sf.SmoothPointEnable = false;
#endif
#if GEN_VERSIONx10 >= 45
#if GFX_VERx10 >= 45
sf.AALineDistanceMode = AALINEDISTANCE_TRUE;
#endif
@ -2032,7 +2032,7 @@ genX(upload_wm)(struct brw_context *brw)
* BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
* _NEW_COLOR
*/
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
if (!(brw_color_buffer_write_enabled(brw) || writes_depth) &&
wm_prog_data->has_side_effects)
wm.PSUAVonly = ON;
@ -2579,7 +2579,7 @@ genX(upload_gs_state)(struct brw_context *brw)
}
#endif
#if GEN_VERSIONx10 == 70
#if GFX_VERx10 == 70
/**
* From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
* Geometry > Geometry Shader > State:
@ -3092,7 +3092,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw)
&brw->wm.base,
};
if (GEN_VERSIONx10 == 70 && !devinfo->is_baytrail &&
if (GFX_VERx10 == 70 && !devinfo->is_baytrail &&
stage_states[MESA_SHADER_VERTEX]->push_constants_dirty)
gen7_emit_vs_workaround_flush(brw);
@ -3106,7 +3106,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw)
brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), pkt) {
pkt._3DCommandSubOpcode = push_constant_opcodes[stage];
if (stage_state->prog_data) {
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
/* The Skylake PRM contains the following restriction:
*
* "The driver must ensure The following case does not occur
@ -3431,7 +3431,7 @@ UNUSED static const struct brw_tracked_state genX(color_calc_state) = {
/* ---------------------------------------------------------------------- */
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
static void
genX(upload_color_calc_and_blend_state)(struct brw_context *brw)
{
@ -3886,7 +3886,7 @@ genX(upload_ps)(struct brw_context *brw)
*/
/* _NEW_BUFFERS, _NEW_MULTISAMPLE */
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
ps.SampleMask = genX(determine_sample_mask(brw));
#endif
@ -4305,7 +4305,7 @@ genX(upload_cs_state)(struct brw_context *brw)
* where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
*/
per_thread_scratch_value = ffs(stage_state->per_thread_scratch) - 11;
} else if (GEN_VERSIONx10 == 75) {
} else if (GFX_VERx10 == 75) {
/* Haswell's Per Thread Scratch Space is in the range [0, 10]
* where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
*/
@ -4394,7 +4394,7 @@ genX(upload_cs_state)(struct brw_context *brw)
.SharedLocalMemorySize = encode_slm_size(GEN_GEN,
prog_data->total_shared),
.BarrierEnable = cs_prog_data->uses_barrier,
#if GEN_VERSIONx10 >= 75
#if GFX_VERx10 >= 75
.CrossThreadConstantDataReadLength =
cs_prog_data->push.cross_thread.regs,
#endif
@ -4925,7 +4925,7 @@ genX(emit_sampler_state_pointers_xs)(UNUSED struct brw_context *brw,
};
/* Ivybridge requires a workaround flush before VS packets. */
if (GEN_VERSIONx10 == 70 &&
if (GFX_VERx10 == 70 &&
stage_state->stage == MESA_SHADER_VERTEX) {
gen7_emit_vs_workaround_flush(brw);
}
@ -5013,7 +5013,7 @@ genX(upload_default_color)(struct brw_context *brw,
int alignment = 32;
if (GEN_GEN >= 8) {
alignment = 64;
} else if (GEN_VERSIONx10 == 75 && (is_integer_format || is_stencil_sampling)) {
} else if (GFX_VERx10 == 75 && (is_integer_format || is_stencil_sampling)) {
alignment = 512;
}
@ -5051,7 +5051,7 @@ genX(upload_default_color)(struct brw_context *brw,
* memcpy the values.
*/
BORDER_COLOR_ATTR(ASSIGN, 32bit, color.ui);
#elif GEN_VERSIONx10 == 75
#elif GFX_VERx10 == 75
if (is_integer_format || is_stencil_sampling) {
bool stencil = format == MESA_FORMAT_S_UINT8 || is_stencil_sampling;
const int bits_per_channel =
@ -5276,7 +5276,7 @@ genX(update_sampler_state)(struct brw_context *brw,
* integer formats. Fall back to CLAMP for now.
*/
if ((tex_cube_map_seamless || sampler->Attrib.CubeMapSeamless) &&
!(GEN_VERSIONx10 == 70 && texObj->_IsIntegerFormat)) {
!(GFX_VERx10 == 70 && texObj->_IsIntegerFormat)) {
wrap_s = TCM_CUBE;
wrap_t = TCM_CUBE;
wrap_r = TCM_CUBE;
@ -5719,7 +5719,7 @@ genX(init_atoms)(struct brw_context *brw)
&gen7_l3_state,
&gen7_push_constant_space,
&gen7_urb,
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
&genX(cc_and_blend_state),
#else
&genX(blend_state), /* must do before cc unit */
@ -5798,7 +5798,7 @@ genX(init_atoms)(struct brw_context *brw)
&genX(index_buffer),
&genX(vertices),
#if GEN_VERSIONx10 == 75
#if GFX_VERx10 == 75
&genX(cut_index),
#endif
};
@ -5924,5 +5924,5 @@ genX(init_atoms)(struct brw_context *brw)
brw->vtbl.emit_compute_walker = genX(emit_gpgpu_walker);
#endif
assert(brw->screen->devinfo.genx10 == GEN_VERSIONx10);
assert(brw->screen->devinfo.genx10 == GFX_VERx10);
}

2
src/mesa/drivers/dri/i965/meson.build
View File

@ -139,7 +139,7 @@ foreach v : ['40', '45', '50', '60', '70', '75', '80', '90', '110']
include_directories : [inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_intel, inc_dri_common],
c_args : [
no_override_init_args, c_sse2_args,
'-DGEN_VERSIONx10=@0@'.format(v),
'-DGFX_VERx10=@0@'.format(v),
],
gnu_symbol_visibility : 'hidden',
dependencies : [dep_libdrm, idep_nir_headers, idep_mesautil],