Commit Graph

13958 Commits

Author SHA1 Message Date
Samuel Pitoiset 958b5c3111 nvc0: force cache flush when binding a new ubo
This fixes the following piglit test:
  ext_transform_feedback-immediate-reuse-uniform-buffer

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-21 22:02:23 +02:00
Samuel Pitoiset a62ccdec62 nv50: force cache flush when binding a new ubo
This fixes the following piglit test:
  ext_transform_feedback-immediate-reuse-uniform-buffer

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-21 21:39:36 +02:00
Adam Jackson 5b4a7ec8f1 r600/sb: Fix an &/&& mistake
gcc says:

    sb/sb_sched.cpp: In member function 'bool r600_sb::alu_group_tracker::try_reserve(r600_sb::alu_node*)':
    sb/sb_sched.cpp:492:7: warning: suggest parentheses around operand of '!' or change '&' to '&&' or '!' to '~' [-Wparentheses]
      if (!trans & fbs)

It happens to be harmless; if fbs is ever non-zero, it will be VEC_210,
which is 5, so (!trans & 5) == 1 and the branch works as expected.  But
logical AND is clearly what was meant.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2015-07-21 13:38:27 -04:00
Samuel Pitoiset cd0dec0d9d nouveau: use bool instead of boolean
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-21 00:42:53 +02:00
Samuel Pitoiset 5b7dd4d419 nvc0: add a missing parameter to nvc0_set_shader_images()
This fixes a compilation warning introduced in commit 05a12c5
(gallium: add interface for writable shader images).

While we are at it, fix indentation and rename parameters according to
the gallium interface.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-20 18:49:14 +02:00
Samuel Pitoiset c2cb771354 nouveau: always align buffers to 0x100
Only constbufs must be aligned to 0x100, but since all buffers can be
rebinded as constant buffers they must be also aligned.

This patch prevents this behaviour by aligning everything to 256-byte
increments at buffer creation.

This fixes dmesg fails for the following piglit test:
  ext_transform_feedback-immediate-reuse-uniform-buffer -auto -fbo

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-20 18:48:27 +02:00
Samuel Pitoiset 19a6214b0f nv50: limit the maximum number of samplers to 16
NV50_3D_BIND_TSC only allows to bind 16 samplers, and since we don't
want to do anything with NV50_3D_BIND_TSC2, just limit the maximum
number of samplers to 16 like for nvc0.

This fixes dmesg fails with the following piglit test:
 max-samplers

But the test still fails.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-20 18:45:56 +02:00
Samuel Pitoiset 6d207b8e35 nv50: turn samples counts off during blit
Fixes the following piglit test:
  occlusion_query_meta_no_fragments

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-20 18:45:56 +02:00
Samuel Pitoiset d246a96bbc nv50: add nesting support for occlusion queries
This is loosely based on nvc0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-20 18:45:55 +02:00
Ilia Mirkin 801d41fa43 nv50: fix max level clamping on G80
It appears that the G80 did not have support for the sampler view
first/last clamping. Put the view's last level in the place of the
texture's so that it doesn't go past what the sampler view allows.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2015-07-20 00:59:37 -04:00
Ilia Mirkin 8c8a71f0d1 gm107/ir: fix indirect txq emission
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2015-07-18 19:03:07 -04:00
Ilia Mirkin 346ce0b988 nvc0/ir: don't worry about sampler in txq handling
There's no need to deal with samplers for texture size queries. That
code also was accidentally setting an invalid sIndirectSrc position, but
it can now just be removed.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2015-07-18 18:48:14 -04:00
Ilia Mirkin 20e484afa4 nvc0/ir: fix txq on indirect samplers
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2015-07-18 17:34:48 -04:00
Eric Anholt ff7896a398 vc4: Switch to using a separate ioctl for making shaders.
This gives the kernel a chance to validate and lock down the data,
without having to deal with mmap zapping.

With this, GLBenchmark stops on a texture relocations, because we'd
recycled a shader BO as another shader and failed to revalidate, since we
weren't clearing the cached validation state on mmap faults.
2015-07-17 22:11:56 -07:00
Eric Anholt 27aa31fab4 vc4: Fix printing of shader-db debug when shader-db isn't turned on. 2015-07-17 12:25:55 -07:00
Eric Anholt 5341349dde vc4: Add debugging on texture relocation validation failures. 2015-07-17 12:25:55 -07:00
Eric Anholt be7adc2eca vc4: Also consider uniform 0 in uniform lowering.
The hash table considers key 0 to be the empty key.
2015-07-17 12:25:55 -07:00
Eric Anholt 90dfabc3b5 vc4: Use the pure/const attributes on a bunch of our QPU functions.
On a release build, this makes the rest of vc4_qpu_validate.c go away
(the compiler didn't know that our qpu helper function calls had no
side effects).
2015-07-17 12:25:55 -07:00
Marek Olšák 05a12c53a3 gallium: add interface for writable shader images
PIPE_CAPs will be added some other time.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-16 16:52:20 +02:00
Marek Olšák b73bec0ecd gallium: add new limits for shader buffers and images
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-16 16:52:17 +02:00
Marek Olšák f9f79d29ce gallium: add BIND flags for R/W buffers and images
PIPE_CAPs and TGSI support will be added later. The TGSI support should be
straightforward. We only need to split TGSI_FILE_RESOURCE into TGSI_FILE_IMAGE
and TGSI_FILE_BUFFER, though duplicating all opcodes shouldn't be necessary.

The idea is:
* ARB_shader_image_load_store should use set_shader_images.
* ARB_shader_storage_buffer_object should use set_shader_buffers(slots 0..M-1)
  if M shader storage buffers are supported.
* ARB_shader_atomic_counters should use set_shader_buffers(slots M..N)
  if N-M+1 atomic counter buffers are supported.

PIPE_CAPs can describe various constraints for early DX11 hardware.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-16 16:52:02 +02:00
Marek Olšák 26222932c0 gallium: add PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-16 16:09:20 +02:00
Eric Anholt 7124feba1b vc4: Cache the texture p1 for the sampler.
Cuts another 12% of vc4_uniforms.o, in exchange for computing it at
CSO creation time.
2015-07-14 15:17:58 -07:00
Eric Anholt 0f4d2b0a2d vc4: Cache texture p0/p1 setup for the sampler view.
In exchange for a bit of space and computation in CSO setup, we cut
vc4_uniform.c (draw time) code size by 4.8%.
2015-07-14 15:17:58 -07:00
Eric Anholt 1835ce6e35 vc4: Move uniforms handling to a separate file.
The rest of vc4_program.c is about compiling, while this is about
uniform emit at draw time.
2015-07-14 15:17:58 -07:00
Eric Anholt 9476b11d6e vc4: Fix some -Wdouble-promotion warnings.
No code generation changes from this, but it'll be useful to have this
next time I go checking -Wdouble-promotion.
2015-07-14 15:17:58 -07:00
Eric Anholt cd7dd45bfe vc4: Fix compiler warnings on release builds. 2015-07-14 11:39:28 -07:00
Eric Anholt 1e80c9fab9 vc4: Add better debug for register allocation failure. 2015-07-14 11:33:54 -07:00
Eric Anholt 3df7892878 vc4: Drop reloc_count tracking for debug asserts on non-debug builds.
Cuts another 88 bytes of compiled code.
2015-07-14 11:31:57 -07:00
Eric Anholt 7432017f65 vc4: Rework cl handling to be friendlier to the compiler.
Drops 680 bytes of code, from avoiding a bunch of extra updates to the
next pointer in the struct.
2015-07-14 11:31:57 -07:00
Eric Anholt a0d3915663 vc4: Make a helper function for getting the current offset in the CL.
I needed to rewrite this a bit for safety checking in the next commit.
Despite being a static inline of the same thing that was being done, we
lose 36 bytes of code for some reason.
2015-07-14 11:31:57 -07:00
Eric Anholt 748bf459b4 vc4: Drop separate cl*_reloc_hindex().
Now that RCL generation is in the kernel, we don't have any other
callers.  Oddly, the compiler generates another 8 bytes of code for
this, but the simplification is worth it.
2015-07-14 11:31:57 -07:00
Eric Anholt e4c540f6d0 vc4: Store reloc pointers as pointers, not offsets.
Now that we don't resize the CL as we build (it's set up at the top by
vc4_start_draw()), we can store the pointers instead of offsets from
the base.  Saves a bit of math in emitting relocs (about 60 bytes of
code).
2015-07-14 11:31:57 -07:00
Eric Anholt ab80519b3c vc4: Add perf debug for when we wait on BOs. 2015-07-14 11:31:57 -07:00
Emil Velikov 9027d53b2a radeonsi: directly include radeon/* headers
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-07-13 20:01:16 +01:00
Dave Airlie de5c2b6f2b radeonsi: direct emit intrinsic for DFRAC.
Michel reported this still failed, and this fixed it

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-07-13 09:21:43 +01:00
Dave Airlie 4cbf0a0ccf radeonsi: ARB_gpu_shader_fp64 + ARB_vertex_attrib_64bit support.
This adds the translation from TGSI to AMDGPU llvm backend, for the
64-bit opcodes. The backend pretty much handles everything for us
fine. There is one patch required for SI DFRAC support, that I know
off.

[airlied: fixed missing comma, updated relnotes]

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-07-12 22:40:51 +01:00
Dave Airlie e70d051560 r600g: move sampler/ubo index registers before temp reg
temp_reg needs to be last, as we increment things
away from it, otherwise on cayman some tests were overwriting
the index regs.

Fixes 2 piglit with ARB_gpu_shader5 forced on cayman.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-07-11 16:31:02 +10:00
Dave Airlie c397bd1407 r600g: fix sampler/ubo indexing on cayman
Cayman needs a different method to upload the CF IDX0/1

This fixes 31 piglits when ARB_gpu_shader5 is forced on
with cayman.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-07-11 16:30:39 +10:00
Ilia Mirkin 1bfa25e88d nv50, nvc0: enable at least one color RT if alphatest is enabled
Fixes the following piglits:
  fbo-alphatest-nocolor
  fbo-alphatest-nocolor-ff

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2015-07-10 22:15:56 -04:00
Rob Clark 15d3524ad2 freedreno/a4xx: occlusion query support
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-07-10 11:57:31 -04:00
Rob Clark 2b7a54452f freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-07-10 11:57:31 -04:00
Rob Clark e44845472a freedreno/ir3/sched: fixup new instr's block
If we split addr/pred, the original instruction could have originated
from a different block.  If we don't fixup the block ptr we hit asserts
later (in debug builds).

NOTE: perhaps we don't want to try to preserve addr/pred reg's across
block boundaries.. this at least needs some thought in case addr/pred
writes end up inside a conditional block..

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-07-10 11:57:31 -04:00
Rob Clark a1a6f00782 freedreno/ir3/ra: fix failed assert for a0/p0
The address and predicate register are special, they don't get assigned
in RA.  So do a better job of ignoring them rather than hitting later
asserts.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-07-10 11:57:31 -04:00
Rob Clark 65b2ae510b freedreno/ir3: shader-db traces
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-07-10 11:57:31 -04:00
Rob Clark 422296e38d freedreno: fix crash in fd_invalidate_resource()
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-07-10 11:57:30 -04:00
Rob Clark ab3ba21f97 vc4: unref old fence
Some, but not all, state trackers will explicitly unref (and set to
NULL) the previous *fence before calling pipe->flush().  So driver
should use fence_ref() which will unref the old fence if not NULL.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Acked-by: Eric Anholt <eric@anholt.net>
2015-07-10 11:57:30 -04:00
Rob Clark 749dced4b3 ilo: unref old fence
Some, but not all, state trackers will explicitly unref (and set to
NULL) the previous *fence before calling pipe->flush().  So driver
should use fence_ref() which will unref the old fence if not NULL.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Acked-by: Chia-I Wu <olvaffe@gmail.com>
2015-07-10 11:57:30 -04:00
Rob Clark 7e0a26defe freedreno: unref old fence
Some, but not all, state trackers will explicitly unref (and set to
NULL) the previous *fence before calling pipe->flush().  So driver
should use fence_ref() which will unref the old fence if not NULL.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-07-10 11:57:30 -04:00
Samuel Pitoiset adc816a1e4 nv50: avoid segfault with enabled but unbound vertex attrib
Before validating vertex arrays we need to check if a VBO is present.
Checking if vb->buffer is not NULL fixes the issue.

Fixes the following piglit test:
  gl-3.1-vao-broken-attrib

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-07-08 21:03:23 +02:00