Commit Graph

92609 Commits

Author SHA1 Message Date
Dave Airlie 87b3799493 radv: add GFX9 to initialisation cmd buffer.
This just adds support for initialising some GFX9 registers,
and handles the different init for the VGT reuse reg.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 09:43:35 +10:00
Dave Airlie 98f27b9cce radv: don't setup raster_config on gfx9.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 09:43:32 +10:00
Dave Airlie 77b8aa4d95 radv: add gfx9 cp dma support.
This adds support to the CP dma code for GFX9, ported from
radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 09:43:29 +10:00
Dave Airlie 41eba750ba radv: add gfx9 depth/stencil surface support.
This is ported from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 09:43:27 +10:00
Dave Airlie ac3e18916f radv: add GFX9 support for color surfaces.
This is ported from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 09:43:24 +10:00
Dave Airlie 0063da8393 radv: add some misc gfx9 pieces.
This just adds the strings and includes the gfx9 register defs
in some files that we need them in.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 09:43:21 +10:00
Dave Airlie a83f28d536 radv: set offchip hs param like radeonsi.
radeonsi never uses 512 here anymore.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 09:43:18 +10:00
Dave Airlie 04924c09be radv: fix typo in comment. 2017-06-06 08:59:30 +10:00
Dave Airlie 114d29e7fe radv: add a comment from radeonsi before cp dma function.
This is just copied over.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 08:44:01 +10:00
Dave Airlie da3330662f radv: remove doubled up prototype.
Must have snuck in during a rebase.
2017-06-06 08:27:35 +10:00
Dave Airlie d1a4d229ec radv: split metadata struct into legacy/gfx9 parts.
This is just ported from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 08:22:45 +10:00
Dave Airlie d987f90354 radv: refactor some texture descriptor state.
This just splits out some non-gfx9 bits in advance to avoid
regressions.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 08:22:42 +10:00
Dave Airlie a5d181f60b radv: refactor color surface init before gfx9.
This just moves the code around in preparation for gfx9 support.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 08:22:38 +10:00
Dave Airlie d3ab239099 radv: refactor depth/stencil state setup
In advance of GFX9 to reduce chances for regression, refactor
this code out so adding the GFX9 changes will be more obvious.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 08:22:33 +10:00
Dave Airlie b50ab49723 radv: use radv_foreach_stage in a couple of places.
This just collapses a few per-stage things into a loop,
shouldn't affect anything.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 08:20:22 +10:00
Emil Velikov 065dea70e5 radeon: remove out of date LLVM_REVISION.txt
The file was introduced to track which LLVM revision was required, yet
that has quickly gone out of shape.

It has seen no updates since 2013.

Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Aaron Watry <awatry@gmail.com>
2017-06-05 17:12:36 -05:00
Juan A. Suarez Romero d1df9a595e docs: update calendar, add news item and link release notes for 17.1.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-06-05 21:22:15 +00:00
Juan A. Suarez Romero 3255b9d348 docs: add sha256 checksums for 17.1.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 4908b1e909ba4cfd5391f61ea551d21cccb52e2f)
2017-06-05 21:22:15 +00:00
Juan A. Suarez Romero 373c309c24 docs: add release notes for 17.1.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 97f6404e50212fb65fe047e467f5497bcba5b8ac)
2017-06-05 21:22:15 +00:00
Brian Paul af4017665b gallium/u_threaded: fixes for MSVC
Replace some static assertions with runtime assertions.  The static
asserts don't work/fail on MSVC, despite the offsets being multiples
of 16 (checked with softpipe).

Use correct parameter types for a few gallium context functions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-05 15:06:15 -06:00
Dave Airlie d8212f847a r600: refactor out some compressed resource state code.
This just takes this out to a separate function as it will
get more complex with images.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
2017-06-06 06:09:44 +10:00
Dave Airlie 7a26a0bf09 r600: document some of the missing shader constants.
These are used for fragment shader thread calculations.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
2017-06-06 06:09:41 +10:00
Dave Airlie 95c1e57a18 r600: add register info for atomic counters.
The atomic counters on evergreen are implemented via append/consume
UAV counters. This just adds the register info for them. The EOS
packets are used to get the atomic totals extracted post shader
execution for storing into a buffer.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
2017-06-06 06:09:37 +10:00
Dave Airlie a6b71f7588 r600: add missing RAT registers and operations.
This just documents in the headers the RAT operation list,
and the RAT encoding for exports.

The immediate registers are used to point to buffers for the
RAT return values (_RTN instructions).

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
2017-06-06 06:09:10 +10:00
Dave Airlie e119c445da r600/sb: fix typo in field definitions
Pointed out by glennk.
2017-06-06 05:46:14 +10:00
Marek Olšák 4b1e6ed49a tgsi/scan: fix scanning fragment shaders with PrimID and Position/Face
Not relevant to radeonsi, because Position/Face are system values
with radeonsi, while this codepath is for drivers where Position and
Face are ordinary inputs.

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-06-05 18:29:42 +02:00
Jason Ekstrand 708664159e i965: Finalize miptrees before prepare_texture
In order to do resolves for texture views with different formats, we
need intel_texture_object::_Format to be valid.  Calling
intel_finalize_mipmap_tree can safely be done multiple times in a row
and should be a fairly cheap operation.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-05 09:26:22 -07:00
Marek Olšák 9275b2233f gallium/u_threaded: remove 16 bytes from tc_batch
All other sentinels occupy what is otherwise unused space.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-06-05 18:25:57 +02:00
Marek Olšák 3b1ce49bc1 gallium/u_threaded: align batches and call slots to 16 bytes
not sure if this helps

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-06-05 18:25:57 +02:00
Marek Olšák 2ec50f98a9 st/mesa: don't load cached TGSI shaders on demand
This fixes a performance issue with the shader cache that delayed Gallium
shader create calls until draw calls.

I'd like this in stable, but it's not a showstopper.

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-05 18:25:57 +02:00
Chih-Wei Huang bb0452442a Android: use bionic pthread_barrier_* if possible
The pthread_barrier_* functions were introduced to bionic
since Nougat.

Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-05 14:06:35 +01:00
Dave Airlie 06f4251925 r600: fix incorrect and missing bit field in register headers.
The compression field was incorrect, and we were missing the
depth before shader field.
2017-06-05 13:19:18 +10:00
Nicolai Hähnle df30123794 radv: use ac_compute_surface
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:44:30 +10:00
Dave Airlie 607e61c40e radv: prepare fmask surface creation
The old code copied over all the surface info from the image
surface, we only want some bits of it, and to modify the flags.

This prevents a regression in dEQP-VK.api.copy_and_blit.resolve_image.*
and others in the subsequent switch to ac_compute_surface.

v2:
- also disable opt4Space in radv_amdgpu_surface, so that we can
  apply this patch separately *before* switching to ac_compute_surface
  and hopefully avoid intermittent regressions (Nicolai)

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-05 10:44:24 +10:00
Nicolai Hähnle 8354f287db radv: use amdgpu_addr_create
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:44:22 +10:00
Nicolai Hähnle 40e94847a5 radv: stop using radv_amdgpu_winsys::family
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:44:18 +10:00
Nicolai Hähnle bd4493b169 radv: use ac_gpu_info
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:44:15 +10:00
Nicolai Hähnle eeb075d662 radv: remove radeon_info::name
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:44:13 +10:00
Nicolai Hähnle dfc06d2fac radv: use ac_surface data structures
This is mostly mechanical changes of renaming types and introducing
"legacy" everywhere.

It doesn't use the ac_surface computation functions yet.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:44:09 +10:00
Nicolai Hähnle 543de22f4b radv: rename radeon_surf::bo_{size,alignment} to surf_{size,alignment}
To match radeonsi / ac_surface.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:44:05 +10:00
Nicolai Hähnle 8417c21d0a radv: remove unused RADEON_SURF_HAS_SBUFFER_MIPTREE
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:44:02 +10:00
Nicolai Hähnle e156eaedb4 radv: remove radeon_surf_level::nblk_z
We're not using thick tiling modes, so we can just derive the value
ourselves.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:43:59 +10:00
Nicolai Hähnle 34b7fb47b6 radv: remove radeon_surf_level::dcc_enabled
Like radeonsi; replace with radeon_surf::num_dcc_levels.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:43:56 +10:00
Nicolai Hähnle 59f72e158a radv: remove radeon_surf_level::pitch_bytes
Like radeonsi. This saves memory, and the information can easily be
recomputed on the fly where necessary.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:43:53 +10:00
Nicolai Hähnle a12d288bff radv: add surface helper variable in radv_GetImageSubresourceLayout
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:43:50 +10:00
Nicolai Hähnle 388d36dfd1 radv: fewer than 8 RBs are possible
This fixes the subsequent assertion on Bonaire.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:43:47 +10:00
Nicolai Hähnle e07d5c7296 ac/surface/gfx6: explicitly support S8 surfaces
This is needed by radv for dEQP-VK.renderpass.simple.stencil

Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-05 10:43:29 +10:00
Dave Airlie 72f0830ecd ac/nir: set workgroup size attribute to correct value.
This ports: 55445ff189 from radeonsi

    radeonsi: tell LLVM not to remove s_barrier instructions

    LLVM 5.0 removes s_barrier instructions if the max-work-group-size
    attribute is not set. What a surprise.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-05 01:37:44 +01:00
Dave Airlie 68c812f699 ac: add new helper function to add a integer target dependent function attr.
This is needed to add the max workgroup size attribute.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-05 01:37:29 +01:00
Dave Airlie 4ba2e6cbfa radv: add external memory support.
This adds support for exporting 2D images, to an
opaque fd.

This implements the:
VK_KHX_external_memory_capabilities
VK_KHX_external_memory
VK_KHX_external_memory_fd

extensions.

These are used by SteamVR, we should work with anv
to decide if we should ship these under an env
var or something.

v2 (Bas): - Don't expose the semaphore ext without implementing it.
          - Only export the capabilities ext as instance ext.
          - Implement radv_GetPhysicalDeviceExternalBufferPropertiesKHX.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
2017-06-05 02:26:43 +02:00