Commit Graph

106305 Commits

Author SHA1 Message Date
Rob Clark 9e3fc0c1e0 nir: fix spelling typo
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-12-11 15:51:34 -05:00
Jason Ekstrand 8f401b0ce6 anv,radv: Disable VK_EXT_pci_bus_info
The Vulkan working group recently discovered that we made a mistake in
assuming that PCI domains are 16-bit even though they can potentially be
32-bit values.  To fix this, the next spec update will change the types
in the VK_EXT_pci_bus_info struct to be 32 bits which will be a
backwards-incompatible change.  Normally, Khronos tries very hard to
never make backwards incompatible changes to specs.  Hopefully, the
extension is new enough (2 months) that there are no shipping apps which
use the extension so this should be safe.

This commit disables the extension for both anv and radv in mesa and
should be back-ported to 18.3 ASAP so we avoid any potential issues with
new apps running on old drivers.  I'll send out a commit (which we can
also back-port to 18.3 if we really care) to re-enable the extension in
both drivers once this week's spec update ships.  The one known use of
this extension is internal to mesa and will continue working with the
extension disabled and will naturally update when we get a new header.

Cc: "18.3" <mesa-stable@lists.freedesktop.org>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-12-11 11:30:05 -06:00
Juan A. Suarez Romero fb88dcf5ca docs: extends 18.2 lifecycle
As 18.3 was published with some delay, let's extend 18.2 life for
another extra release.

CC: Andres Gomez <agomez@igalia.com>
CC: Dylan Baker <dylan@pnwbakers.com>
CC: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2018-12-11 15:20:10 +01:00
Kristian H. Kristensen c0de7c21a3 glapi: fixup EXT_multisampled_render_to_texture dispatch
There's a few missing and convoluted bits:

 - FramebufferTexture2DMultisampleEXT
Missing sanity check, should be desktop="false"

 - RenderbufferStorageMultisampleEXT
Missing sanity check, is aliased to RenderbufferStorageMultisample.
Thus it's set only when desktop GL or GLES2 v3.0+, while the extension
is GLES2 2.0+.

If we flip the aliasing we'll break indirect GLX, so loosen the version
to 2.0. Not perfect, yet this is the most sane thing I could think of.

v2: [Emil] Fixup RenderbufferStorageMultisampleEXT, commmit message

Cc: Kristian H. Kristensen <hoegsberg@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108974
Fixes: 1b331ae505 ("mesa: Add core support for EXT_multisampled_render_to_texture{,2}")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-10 15:09:07 -08:00
Kristian H. Kristensen 9578dde1c8 freedreno: Fix the Makefile.am fix
Commit b028ce29f0 fixed a typo in
src/freedreno/Makefile.am, but ended up breaking the build for
freedreno.  The typo inadvertently made things work, as we were not
supposed to link with libnir or libmesautil to begin with.  Those come
in through libmesagallium and the typo prevented the duplicated
linkage.

Fixes: b028ce29f ("freedreno: add the missing _la in libfreedreno_ir3_la")
Cc: Emil Velikov <emil.velikov@collabora.com>
2018-12-10 14:28:09 -08:00
Matt Turner f447a13032 i965/fs: Handle V/UV immediates in dump_instructions() 2018-12-10 10:46:56 -08:00
Sagar Ghuge 694eb342a2 intel/compiler: Always print flag subregister number
While disassembling the predicate always print flag subregister number
to keep grammar same across the generation for assembler tool.

v2: Combine consecutive format calls (Matt Turner)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2018-12-10 10:07:11 -08:00
Sagar Ghuge e7598c5a62 intel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for scalar region
When RepCtrl is set, the swizzle field is ignored by the hardware. In
order to ensure a 1-to-1 correspondence between the human-readable
disassembly and the binary instruction encoding always set the swizzle
to XXXX (all zeros) when it is unused due to RepCtrl

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2018-12-10 10:06:55 -08:00
Dylan Baker 6d3cbbbe15 meson: Add nir_algebraic_parser_test to suites
Just to make it easier to run a nir tests together.

Fixes: a0ae12ca91
       ("nir/algebraic: Add unit tests for bitsize validation")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-12-10 09:14:44 -08:00
Emil Velikov 27c4fdfdf8 amd/addrlib: drop si_ci_vi_merged_enum.h from the list
Fixes: 776b911365 ("amd/addrlib: update Mesa's copy of addrlib")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-10 16:35:01 +00:00
Emil Velikov b028ce29f0 freedreno: add the missing _la in libfreedreno_ir3_la
Fixes: aa0fed10d3 ("freedreno: move ir3 to common location")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-10 16:35:01 +00:00
Emil Velikov b30e37ec64 freedreno: drop duplicate MKDIR_GEN declaration
Fixes: aa0fed10d3 ("freedreno: move ir3 to common location")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-10 16:35:01 +00:00
Rhys Kidd 05c7e726f7 travis: radeonsi and radv require LLVM 7.0
Fixes: 3fbdcd942f ("amd: remove support for LLVM 6.0")
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Jan Vesely <jan.vesely@rutgers.edu>
Cc: Andres Gomez <agomez@igalia.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-10 16:20:12 +00:00
Kirill Burtsev a539316485 loader: free error state, when checking the drawable type
Currently we distinguish if the drawable is a window or pixmap by
checking xcb_present_select_input throws an error or not.

Yet, we don't always free the error state returned by xcb.

Cc: Kirill Burtsev <kirill.burtsev@qt.io>
Cc: Boyan Ding <boyan.j.ding@gmail.com>
Fixes: 6bd9ba7d07 ("loader: Add dri3 helper")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil: add commit message, fixes tag]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-10 16:19:55 +00:00
Timothy Arceri 032f247921 nir: make use of new nir_cf_list_clone_and_reinsert() helper
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-12-10 13:59:50 +11:00
Timothy Arceri 6b961eb534 nir: add a new nir_cf_list_clone_and_reinsert() helper
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-12-10 13:59:50 +11:00
Timothy Arceri 03d7c65ad8 nir: clarify some nit_loop_info member names
Following commits will introduce additional fields such as
guessed_trip_count. Renaming these will help avoid confusion
as our unrolling feature set grows.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-12-10 13:59:50 +11:00
Timothy Arceri de0aee7638 nir: small tidy ups for nir_loop_analyze()
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-12-10 13:59:50 +11:00
Kenneth Graunke 41a4a6ba6f i965: Flip arguments to load_register_reg helpers.
load_register_imm and load_register_mem take the destination as the
first argument, so I'd like load_register_reg to do the same the sake
of consistency.  Otherwise, reading sequences of mixed LRI/LRM/LRR is
needlessly confusing.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-12-09 18:39:16 -08:00
Kenneth Graunke 34c9dc2537 i965: Delete dead brw_meta_resolve_color prototype.
Dead since commit 09e041d61d (May 2016).
2018-12-09 18:39:16 -08:00
Karol Herbst 77944fb2b7 nv50/ir: fix use-after-free in ConstantFolding::visit
opnd() might delete the passed in instruction, but it's used through
i->srcExists() later in visit

v2: use continue instead return
v3: use brackets for the outer if/else chain

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-12-09 18:19:59 +01:00
Karol Herbst d63a133082 nouveau: use atomic operations for driver statistics
multiple threads can write to those at the same time

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-12-09 04:43:20 +01:00
Karol Herbst a28ff22295 nv50/ir: initialize relDegree staticly
this race condition is pretty harmless, but also pretty trivial to fix

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-12-09 04:43:17 +01:00
Eric Anholt cc6a5e937b shader-packing 2018-12-07 16:51:12 -08:00
Eric Anholt 09ad0d870c tfu 2018-12-07 16:49:41 -08:00
Eric Anholt f1d98204c3 v3d: Fix a leak of the disassembled instruction string during debug dumps.
Fixes: ade416d023 ("broadcom: Add VC5 NIR compiler.")
2018-12-07 16:48:23 -08:00
Eric Anholt 7f8d8b7d27 vc4: Fix a leak of the transfer helper on screen destroy.
Fixes: d009463a65 ("vc4: Switch to using u_transfer_helper for MSAA maps.")
2018-12-07 16:48:23 -08:00
Eric Anholt 3bd73d31a8 v3d: Fix a leak of the transfer helper on screen destroy.
Fixes: 7a30517cce ("broadcom/vc5: Start adding support for rendering to Z32F_S8X24_UINT.")
2018-12-07 16:48:23 -08:00
Eric Anholt bad95bb13c v3d: Add VIR dumping of TMU config p0/p1.
I had a bit of it for V3D 3.x, but didn't update it for 4.x.
2018-12-07 16:48:23 -08:00
Eric Anholt 1fc78ff3f1 v3d: Simplify VIR uniform dumping using a temporary. 2018-12-07 16:48:23 -08:00
Eric Anholt 5932575299 v3d: Garbage collect unused uniforms code. 2018-12-07 16:48:23 -08:00
Eric Anholt 62a3192112 v3d: Split most of TEXTURE_SHADER_STATE setup out of sampler views.
For shader image load/store, we want most of this logic to be shared.
2018-12-07 16:48:23 -08:00
Eric Anholt 8cb1f3bab7 v3d: Avoid confusing auto-indenting in TEXTURE_SHADER_STATE packing
Having "v3dx_pack() {" under each #if branch would confuse emacs's
indenter.
2018-12-07 16:48:23 -08:00
Eric Anholt ee9b758053 v3d: Fix handling of texture first_layer offsets for 3D textures.
I think this bug predated adding v3d_layer_offset().  Noticed during an
unrelated refactor.
2018-12-07 16:48:23 -08:00
Eric Anholt acecee4c2d v3d: Return the right gl_SampleMaskIn[] value.
It's supposed to be the dispatched sample mask for this pixel, not the GL
state's sample mask.
2018-12-07 16:48:23 -08:00
Eric Anholt 6870111051 v3d: Fix a comment typo 2018-12-07 16:48:23 -08:00
Eric Anholt ca0e4ae4bc v3d: Convert to using nir_src_as_uint() from const_value derefs.
Follows 16870de8a0 ("nir: Use nir_src_is_const and nir_src_as_* in core
code") to clean up v3d.
2018-12-07 16:48:23 -08:00
Eric Anholt 503b55c622 v3d: Don't forget to flush writes to UBOs.
If someone did TF into a UBO, we might have left the TF job un-flushed at
the point of reading.
2018-12-07 16:48:23 -08:00
Eric Anholt 504d06e4c1 v3d: Make an array for frag/vert texture state in the context.
This simplifies a bunch of our texture handling, while introducing the
slots necessary for adding new shader stages.
2018-12-07 16:48:23 -08:00
Eric Anholt d1965344ac v3d: Re-use the wrap mode uniform on V3D 3.3. 2018-12-07 16:48:23 -08:00
Eric Anholt e94d034a38 v3d: Put default vertex attribute values into the state uploader as well.
The default attributes are long-lived (the state struct is cached), and
only 256 bytes each.
2018-12-07 16:48:23 -08:00
Eric Anholt b38e4d313f v3d: Create a state uploader for packing our shaders together.
Shaders are usually quite short, and are private to the context.  We can
save memory and reduce the work the kernel needs to do at exec time by
packing them together in a stream uploader for long-lived state.
2018-12-07 16:48:23 -08:00
Eric Anholt 1911888760 v3d: Update simulator cache flushing code to match the kernel better.
We were missing the invalidate between bin and render (possibly relevant
for SSBOs), and still trying to flush the nonexistent L2C on 3.3+.
2018-12-07 16:48:23 -08:00
Eric Anholt 2ebca177dc v3d: Use the TFU to do generatemipmap.
This is a separate, dedicated hardware unit for texture layout conversions
and mipmap generation.
2018-12-07 16:48:23 -08:00
Eric Anholt ee0549ff9a v3d: Add the V3D TFU submit interface to the simulator.
The TFU lets us format raster and SAND images into formats that can be
read by the texture engine, and do mipmap generation.

The UAPI comes from drm-next e69aa5f9b97f ("Merge tag
'drm-misc-next-2018-12-06' of git://anongit.freedesktop.org/drm/drm-misc
into drm-next")
2018-12-07 16:48:23 -08:00
Eric Anholt 42652ea51e v3d: Use combined input/output segments.
The HW apparently has some issues (or at least a much more complicated VCM
calculation) with non-combined segments, and the closed source driver also
uses combined I/O.  Until I get the last CTS failure resolved (which does
look plausibly like some VPM stomping), let's use combined I/O too.
2018-12-07 16:48:23 -08:00
Eric Anholt fb9bcf5602 v3d: Add missing OES_half_float_linear support.
We were exposing ARB_texture_float, but apparently not the OES subset
flag.  Fixes regression from GLES3 support to GLES2.

Fixes: fcf9fcee3c ("mesa/main: do not require float-texture filtering
for es3")
2018-12-07 16:48:23 -08:00
Eric Anholt 90e98295a4 v3d: Add support for RGBA_SRGB along with BGRA_SRGB.
This is the actual native format for the hardware, without swizzling.
Noticed while debugging why GLES3 disappeared.
2018-12-07 16:48:23 -08:00
Kenneth Graunke f0d51e81c9 intel/blorp: Expand blorp_address::offset to be 64 bits.
In the softpin world, surface state base address may be a fixed 64-bit
address (with no associated BO).  It makes sense to store this in the
offset field.  But it needs to be the full size.

We also update the clear color address to be consistently uint64_t
everywhere so we can continue passing intel_miptree_get_clear_color
a pointer to the blorp_address's offset field without type mismatches.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2018-12-07 16:35:51 -08:00
Rob Clark d014af98b7 freedreno/drm: fix memory leak
Fix an emberrasing memory leak with the non-softpin submit/rb
implementation.

Fixes: f3cc0d2747 freedreno: import libdrm_freedreno + redesign submit
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-07 14:12:12 -05:00