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i965: Flip arguments to load_register_reg helpers. 

load_register_imm and load_register_mem take the destination as the
first argument, so I'd like load_register_reg to do the same the sake
of consistency.  Otherwise, reading sequences of mixed LRI/LRM/LRR is
needlessly confusing.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Kenneth Graunke 2018-12-07 13:01:07 -08:00
parent 34c9dc2537
commit 41a4a6ba6f
5 changed files with 10 additions and 9 deletions
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2
src/mesa/drivers/dri/i965/brw_conditional_render.c
View File

@ -66,7 +66,7 @@ set_predicate_for_overflow_query(struct brw_context *brw,
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
hsw_overflow_result_to_gpr0(brw, query, count);
brw_load_register_reg64(brw, HSW_CS_GPR(0), MI_PREDICATE_SRC0);
brw_load_register_reg64(brw, MI_PREDICATE_SRC0, HSW_CS_GPR(0));
brw_load_register_imm64(brw, MI_PREDICATE_SRC1, 0ull);
}

8
src/mesa/drivers/dri/i965/brw_context.h
View File

@ -1428,10 +1428,10 @@ void brw_load_register_imm32(struct brw_context *brw,
uint32_t reg, uint32_t imm);
void brw_load_register_imm64(struct brw_context *brw,
uint32_t reg, uint64_t imm);
void brw_load_register_reg(struct brw_context *brw, uint32_t src,
uint32_t dest);
void brw_load_register_reg64(struct brw_context *brw, uint32_t src,
uint32_t dest);
void brw_load_register_reg(struct brw_context *brw, uint32_t dst,
uint32_t src);
void brw_load_register_reg64(struct brw_context *brw, uint32_t dst,
uint32_t src);
void brw_store_data_imm32(struct brw_context *brw, struct brw_bo *bo,
uint32_t offset, uint32_t imm);
void brw_store_data_imm64(struct brw_context *brw, struct brw_bo *bo,

2
src/mesa/drivers/dri/i965/hsw_queryobj.c
View File

@ -154,7 +154,7 @@ static void
shr_gpr0_by_2_bits(struct brw_context *brw)
{
shl_gpr0_by_30_bits(brw);
brw_load_register_reg(brw, HSW_CS_GPR(0) + 4, HSW_CS_GPR(0));
brw_load_register_reg(brw, HSW_CS_GPR(0), HSW_CS_GPR(0) + 4);
brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0);
}

3
src/mesa/drivers/dri/i965/hsw_sol.c
View File

@ -98,7 +98,8 @@ tally_prims_written(struct brw_context *brw,
brw_load_register_mem64(brw, HSW_CS_GPR(1), obj->prim_count_bo,
START_OFFSET + i * sizeof(uint64_t));
/* GPR2 = Ending Snapshot */
brw_load_register_reg64(brw, GEN7_SO_NUM_PRIMS_WRITTEN(i), HSW_CS_GPR(2));
brw_load_register_reg64(brw, HSW_CS_GPR(2),
GEN7_SO_NUM_PRIMS_WRITTEN(i));
BEGIN_BATCH(9);
OUT_BATCH(HSW_MI_MATH | (9 - 2));

4
src/mesa/drivers/dri/i965/intel_batchbuffer.c
View File

@ -1218,7 +1218,7 @@ brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm)
* Copies a 32-bit register.
*/
void
brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest)
brw_load_register_reg(struct brw_context *brw, uint32_t dest, uint32_t src)
{
assert(brw->screen->devinfo.gen >= 8 || brw->screen->devinfo.is_haswell);
@ -1233,7 +1233,7 @@ brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest)
* Copies a 64-bit register.
*/
void
brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest)
brw_load_register_reg64(struct brw_context *brw, uint32_t dest, uint32_t src)
{
assert(brw->screen->devinfo.gen >= 8 || brw->screen->devinfo.is_haswell);