Commit Graph

56434 Commits

Author SHA1 Message Date
José Fonseca 6d911a5944 mesa: Move declaration to top of block.
To fix MSVC build.  Trivial.
2014-05-01 10:00:10 +01:00
José Fonseca b0de67ad2d osmesa: Fix typo in _MaxEnabledTexImageUnit. 2014-05-01 09:55:20 +01:00
Kenneth Graunke 85ce2242cb i965/vec4: Port untyped atomic message support to Broadwell.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-01 00:24:12 -07:00
Kenneth Graunke 45367d2d09 i965/vec4: Port untyped surface reads support to Broadwell.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-01 00:24:10 -07:00
Kenneth Graunke e9e89d5756 i965/fs: Port untyped atomic message support to Broadwell.
v2: Fix SIMD mode comment (caught by Eric Anholt).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-01 00:24:08 -07:00
Kenneth Graunke 54a48984b3 i965/fs: Port untyped surface read support to Broadwell.
v2: Drop unused num_components variable; fix SIMD Mode comment
    (caught by Eric Anholt).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-01 00:24:06 -07:00
Kenneth Graunke f1cd9fee53 i965/fs: Set fs_inst::header_present for untyped atomics/surface reads.
The brw_eu_emit.c code manually forces the header present bit when
used in align1 (scalar) mode.  So, this has no effect currently.

However, it is nice to have fs_inst::header_present reflect reality.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-01 00:24:04 -07:00
Kenneth Graunke 4d9c27df45 i965: Disassemble atomic operations and other DP:DC1 stuff on Broadwell.
This is similar to what Eric did for Gen7 a little while ago; it also
has support for untyped surface reads.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-01 00:24:02 -07:00
Kenneth Graunke 3b3c46656e i965: Implement the create_raw_surface() hook on Broadwell.
Otherwise we crash when setting up atomic buffer objects.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77221
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-01 00:23:59 -07:00
Kenneth Graunke 69fd055166 i965: Drop mark_surface_used from gen8 generators.
Francisco made brw_mark_surface_used a freestanding function in
commit a32817f3c2.  We should use it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-01 00:23:57 -07:00
Kenneth Graunke b10785f9a9 i965/fs: Add support for fs_inst::force_writemask_all on Broadwell.
This must not have existed when I wrote the original code.  The atomic
operation header setup code uses this.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-01 00:23:44 -07:00
Kenneth Graunke ac30e1adb4 i965: Actually emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS.
For platforms using hardware contexts (currently Gen6+), we failed to
emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS, instead emitting MI_NOOP
for both.

During one of the context initialization reordering patches, we
accidentally moved brw_init_state before we set brw->CMD_PIPELINE_SELECT
and brw->CMD_VF_STATISTICS.  So, when brw_init_state uploaded initial
GPU state (brw_init_state -> brw_upload_initial_gpu_state ->
brw_upload_invariant_state), these would be 0 (MI_NOOP).

Storing the commands in the context is not worthwhile.  We have many
generation checks in our state upload code, and for platforms with
hardware contexts, this only gets called once per GL context anyway.
The cost is negligable, and it's easy to botch context creation
ordering.

This may fix hangs on Gen6+ when using the media pipeline.

Cc: "10.0 10.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2014-05-01 00:12:22 -07:00
Kenneth Graunke 0380ec467d i965: Don't enable reset notification support on Gen4-5.
arekm reported that using Chrome with GPU acceleration enabled on GM45
triggered the hw_ctx != NULL assertion in brw_get_graphics_reset_status.

We definitely do not want to advertise reset notification support on
Gen4-5 systems, since it needs hardware contexts, and we never even
request a hardware context on those systems.

Cc: "10.1" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75723
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 23:08:22 -07:00
Eric Anholt 862986ade3 i965: Fix state flag comments on color_buffer_write_enabled() calls.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:21 -07:00
Eric Anholt e739558c9d i965: Drop bogus state flag comment.
This was introduced with the comment and code below it, though the code
only touches prog_data (CACHE_NEW_WM_PROG).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:21 -07:00
Eric Anholt 60c5f9716c i965: Track the number of samples in the drawbuffer.
This keeps us from having to emit the nonpipelined state packet on every
FBO binding.

-4.42003% +/- 1.09961% effect on cairo-perf-trace runtime on glamor (n=110).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:21 -07:00
Eric Anholt 973345fc23 mesa: Track maximum CurrentTexUnit to reduce glDeleteTextures() overhead.
No more walking 96*6 pointers looking to see if they're the current
texture, when we only use the first 2 out of 96 units.  -6.26002% +/-
1.87817% effect on cairo runtime on no-fbo-cache glamor (n=36).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:21 -07:00
Eric Anholt 6a97deb88a mesa: Rewrite shader-based texture image state updates.
Instead of walking 6 shader stages for each of the 96 combined texture
image units, now we just walk the samplers used in each shader stage.

With cairo-perf-trace on Xephyr with glamor, I'm seeing a -6.50518% +/-
2.55601% effect on runtime (n=22) since the "drop _EnabledUnits" change.
No significant performance difference on an apitrace of minecraft (n=442).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:20 -07:00
Eric Anholt a580b500ed mesa: Split the shader texture update logic from fixed function.
I want to avoid walking the entire long array texture image units, but the
obvious way to do so means walking program samplers, and thus hitting the
units in a random order.

This change replaces the previous behavior of only setting up the fallback
texture for a fragment shader with setting up the fallback texture for any
shader that's missing a complete texture of the right target in its unit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:20 -07:00
Eric Anholt e5e50fae6a mesa: Finish removing the _ReallyEnabled field.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:20 -07:00
Eric Anholt 741f5d58e6 radeon: Drop the remaining driver usage of _ReallyEnabled.
This is kind of ugly, but I think it's worth it to finish off the last
consumers of _ReallyEnabled.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:20 -07:00
Eric Anholt 2f8749af20 swrast: Drop remaining use of _ReallyEnabled.
The _MaxEnabledTexImageUnit check assures us that Unit[0].Current != NULL.
This is the last consumer of _ReallyEnabled outside of the radeons.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:20 -07:00
Eric Anholt 8061f90a64 gallium: Drop use of _ReallyEnabled.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:20 -07:00
Eric Anholt cef82a64bd mesa: Drop _ReallyEnabled usage from ff_fragment_shader.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:20 -07:00
Eric Anholt 07b94c99a7 i915: Drop use of _ReallyEnabled.
We can just look at _Current's target.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:20 -07:00
Eric Anholt ff9c3e8e5a mesa: Replace use of _ReallyEnabled as a boolean with use of _Current.
I'm probably not the only person that has tried to kill _ReallyEnabled.
This does the mechanical part of the work, and cleans _ReallyEnabled from
i965.

I think that using _Current makes texture management clearer: You can't
have multiple targets in use in the same texture image unit at the same
time, because there's just that one pointer.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:20 -07:00
Eric Anholt 62d46332d8 mesa: Ensure that (unit->_Current != 0) == (unit->_ReallyEnabled != 0).
I'm going to try to delete _ReallyEnabled, which is this weird bitfield
with either 0 or 1 bits set with just the reference to _Current.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:20 -07:00
Eric Anholt 6bac47c05a mesa: Drop dead last_ReallyEnabled fields from drivers.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:20 -07:00
Eric Anholt c703658b39 mesa: Drop _EnabledUnits.
The field wasn't really valid, since we've got more than 32 units now.  It
turns out it was mostly just used for checking != 0, or checking for fixed
function coordinates, though.

v2: Fix mis-conversion in xm_line.c (caught by Ken).

Reviewed-by: Matt Turner <mattst88@gmail.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:33:17 -07:00
Eric Anholt 3dfe56c53b swrast: Just use _EnabledCoordUnits for figuring out which texcoords to build.
_EnabledUnits is all of the first 32 image units that are used by fixed
function or programs, while _EnabledCoordUnits is just which fixed function
fragment shader texcoords need to be generated.  This is a theoretical bugfix
in the case of a vertex shader texturing from large texture image unit number
(we'd end up flagging something other than a VARYING_SLOT_TEXn as needing to
be generated), but it's actually just motivated by trying to kill
_EnabledUnits.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:21:59 -07:00
Eric Anholt 1ad443ecdd i915: Redo texture unit walking on i830.
We now know what the max unit is in the context state.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 14:21:59 -07:00
Matt Turner 9565392031 i965/vec4: Remove 'mul_arg' from try_emit_mad().
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 11:41:29 -07:00
Matt Turner 1e50bc9ee1 i965/fs: Remove 'mul_arg' from try_emit_mad().
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-30 11:41:29 -07:00
Brian Paul 475f5ff64d mesa: change invalid texture swizzle error to GL_INVALID_ENUM
The original GL_EXT_texture_swizzle extensions said GL_INVALID_OPERATION
was to be generated when the an invalid swizzle was passed to
glTexParameter().  But in OpenGL 3.3 and later, the error should be
GL_INVALID_ENUM.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-04-30 10:09:44 -06:00
Andreas Hartmetz 1c6aa6599e translate_sse: Use the correct buffer index in this fast path.
It is possible that there are multiple input buffers but only one is
relevant for translation. Then there will be only a single translation
group, which might need to source data from a buffer index != 0.

Fixes wrong vertex shader inputs as observed while debugging with an
application and driver combination that requires translation of a
vertex attribute in a non-trivial set of attributes and input buffers.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-29 20:35:10 -04:00
Tom Stellard ca848e8bee clover: Query drivers for max clock frequency
Igor Gnatenko:

v2: PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY instead of
    PIPE_COMPUTE_MAX_CLOCK_FREQUENCY

Bruno Jiménez:

  v3: Drivers report clock in Mhz

Signed-off-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-04-29 15:28:17 -07:00
Tom Stellard 0a41054b7f radeon/compute: Implement PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
Igor Gnatenko:
  v2: in define RADEON_INFO_MAX_SCLK use 0x1a instead of 0x19 (upstream changes)

Bruno Jiménez:
  v3: Convert the frequency to MHz from kHz after getting it in
  'do_winsys_init'

Signed-off-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2014-04-29 15:25:50 -07:00
Tom Stellard 5fe1a0ebad gallium: Add PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
Bruno Jiménez:
  v2: Updated the docs
  v3: Remove trailing comma

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-04-29 15:24:53 -07:00
Kenneth Graunke 979a015bc1 i965: Fix a few base addresses on Broadwell.
We intended to set these 64-bit addresses to 0, and set the enable bit.
But, I accidentally placed the DWord with the high bits first, when it
should have been second.

This generally worked out, by luck - presumably General State Base
Address is initially zero, and ends up remaining that way in our
contexts since we bungled the "modify enable" bit.

v2: Fix MOCS shift on GSBA.  It should be 4, and I had 2.
    (Caught by Ben Widawsky.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2014-04-29 14:01:06 -07:00
EdB 7fb05f9298 clover: Stub implementation of CL 1.2 sub-devices.
The implementation is basically a NOP but it conforms with OpenCL 1.2.

[ Francisco Jerez: Initialize property return buffer for
  CL_DEVICE_PARTITION_PROPERTIES, CL_DEVICE_PARTITION_TYPE,
  CL_DEVICE_PARTITION_AFFINITY_DOMAIN, and make the latter a scalar
  rather than a vector.  Some clean-up and code style fixes. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-04-29 16:14:50 +02:00
EdB 5827781d25 clover: Add clEnqueue{Marker, Barrier}WithWaitList.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-04-29 13:12:38 +02:00
Jan Vesely 7b11c97d31 clover: Align kernel argument sizes to nearest power of 2
v2: use a new variable for aligned size
    add comment
    make both vars const
    only use the aligned value in argument constructors
    fix comment typo

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-04-29 13:09:21 +02:00
Francisco Jerez df985cc8f6 clover: Avoid warnings from references to deprecated CL 1.1 APIs.
Acked-by: Tom Stellard <thomas.stellard@amd.com>
2014-04-29 13:01:37 +02:00
Francisco Jerez beadd6b0cc clover: Update OpenCL headers to version 1.2 from Khronos.
The C++ headers are *not* updated because they rely on CL 1.2 APIs
that we do not implement yet when the core CL 1.2 headers are present.

Acked-by: Tom Stellard <thomas.stellard@amd.com>
2014-04-29 13:01:10 +02:00
Ilia Mirkin f782d6e792 nvc0/ir: offset appears to come before the Z ref
Fixes textureGatherOffset when used with a shadow sampler. Also verified
against blob compiler with textureLodOffset manually (no piglit tests
for texture[Lod]Offset + shadow samplers).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-28 20:32:36 -04:00
Ilia Mirkin f3aa999383 nv50/ir: change texture offsets to ValueRefs, allow nonconst
This allows us to have non-constant offsets for textureGatherOffset and
textureGatherOffsets.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-28 19:09:18 -04:00
Ilia Mirkin 46364a53ef nvc0/ir: do constant folding of extbf/insbf
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-28 19:05:16 -04:00
Ilia Mirkin 1c85177419 nvc0/ir: add support for MUL_HI tgsi opcodes
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-28 19:05:16 -04:00
Ilia Mirkin b4b20d42f6 nvc0/ir: add support for new bitfield manipulation opcodes
This adds support for:

IBFE, UBFE, BFI, LSB, IMSB, UMSB, BREV, POPC

Which are all required for ARB_gs5 support.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-28 19:05:16 -04:00
Ilia Mirkin 1db993f2fe tgsi: add tgsi_exec support for new bit manipulation opcodes
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-04-28 19:05:11 -04:00