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i965: Actually emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS. 

For platforms using hardware contexts (currently Gen6+), we failed to
emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS, instead emitting MI_NOOP
for both.

During one of the context initialization reordering patches, we
accidentally moved brw_init_state before we set brw->CMD_PIPELINE_SELECT
and brw->CMD_VF_STATISTICS.  So, when brw_init_state uploaded initial
GPU state (brw_init_state -> brw_upload_initial_gpu_state ->
brw_upload_invariant_state), these would be 0 (MI_NOOP).

Storing the commands in the context is not worthwhile.  We have many
generation checks in our state upload code, and for platforms with
hardware contexts, this only gets called once per GL context anyway.
The cost is negligable, and it's easy to botch context creation
ordering.

This may fix hangs on Gen6+ when using the media pipeline.

Cc: "10.0 10.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Kenneth Graunke 2014-04-29 14:29:28 -07:00
parent 0380ec467d
commit ac30e1adb4
3 changed files with 8 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mesa/drivers/dri/i965/brw_context.c
View File

@ -718,14 +718,6 @@ brwCreateContext(gl_api api,
brw_init_surface_formats(brw);
if (brw->is_g4x || brw->gen >= 5) {
brw->CMD_VF_STATISTICS = GM45_3DSTATE_VF_STATISTICS;
brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
} else {
brw->CMD_VF_STATISTICS = GEN4_3DSTATE_VF_STATISTICS;
brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
}
brw->max_vs_threads = devinfo->max_vs_threads;
brw->max_gs_threads = devinfo->max_gs_threads;
brw->max_wm_threads = devinfo->max_wm_threads;

5
src/mesa/drivers/dri/i965/brw_context.h
View File

@ -1172,11 +1172,6 @@ struct brw_context
*/
int num_samples;
/* hw-dependent 3DSTATE_VF_STATISTICS opcode */
uint32_t CMD_VF_STATISTICS;
/* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
uint32_t CMD_PIPELINE_SELECT;
/**
* Platform specific constants containing the maximum number of threads
* for each pipeline stage.

10
src/mesa/drivers/dri/i965/brw_misc_state.c
View File

@ -896,13 +896,17 @@ const struct brw_tracked_state brw_line_stipple = {
void
brw_upload_invariant_state(struct brw_context *brw)
{
const bool is_965 = brw->gen == 4 && !brw->is_g4x;
/* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
if (brw->gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
/* Select the 3D pipeline (as opposed to media) */
const uint32_t _3DSTATE_PIPELINE_SELECT =
is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
BEGIN_BATCH(1);
OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16 | 0);
OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | 0);
ADVANCE_BATCH();
if (brw->gen < 6) {
@ -926,8 +930,10 @@ brw_upload_invariant_state(struct brw_context *brw)
ADVANCE_BATCH();
}
const uint32_t _3DSTATE_VF_STATISTICS =
is_965 ? GEN4_3DSTATE_VF_STATISTICS : GM45_3DSTATE_VF_STATISTICS;
BEGIN_BATCH(1);
OUT_BATCH(brw->CMD_VF_STATISTICS << 16 |
OUT_BATCH(_3DSTATE_VF_STATISTICS << 16 |
(unlikely(INTEL_DEBUG & DEBUG_STATS) ? 1 : 0));
ADVANCE_BATCH();
}