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radeon: Drop the remaining driver usage of _ReallyEnabled. 

This is kind of ugly, but I think it's worth it to finish off the last
consumers of _ReallyEnabled.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt 2014-04-23 16:37:03 -07:00
parent 2f8749af20
commit 741f5d58e6
8 changed files with 40 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/mesa/drivers/dri/r200/r200_fragshader.c
View File

@ -362,7 +362,7 @@ static void r200UpdateFSRouting( struct gl_context *ctx ) {
if (shader->NumPasses < 2) {
for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) {
GLbitfield targetbit = ctx->Texture.Unit[reg]._ReallyEnabled;
struct gl_texture_object *texObj = ctx->Texture.Unit[reg]._Current;
R200_STATECHANGE( rmesa, tex[reg] );
rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = 0;
if (shader->SetupInst[0][reg].Opcode) {
@ -387,10 +387,10 @@ static void r200UpdateFSRouting( struct gl_context *ctx ) {
}
rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
}
else if (targetbit == TEXTURE_3D_BIT) {
else if (texObj && texObj->Target == GL_TEXTURE_3D) {
txformat_x |= R200_TEXCOORD_VOLUME;
}
else if (targetbit == TEXTURE_CUBE_BIT) {
else if (texObj && texObj->Target == GL_TEXTURE_CUBE_MAP) {
txformat_x |= R200_TEXCOORD_CUBIC_ENV;
}
else if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI ||
@ -403,7 +403,7 @@ static void r200UpdateFSRouting( struct gl_context *ctx ) {
rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] = txformat;
rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] = txformat_x;
/* enabling texturing when unit isn't correctly configured may not be safe */
if (targetbit)
if (texObj)
rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
}
}
@ -411,7 +411,7 @@ static void r200UpdateFSRouting( struct gl_context *ctx ) {
} else {
/* setup 1st pass */
for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) {
GLbitfield targetbit = ctx->Texture.Unit[reg]._ReallyEnabled;
struct gl_texture_object *texObj = ctx->Texture.Unit[reg]._Current;
R200_STATECHANGE( rmesa, tex[reg] );
GLuint txformat_multi = 0;
if (shader->SetupInst[0][reg].Opcode) {
@ -428,10 +428,10 @@ static void r200UpdateFSRouting( struct gl_context *ctx ) {
}
rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= R200_PPX_TEX_0_ENABLE << reg;
}
else if (targetbit == TEXTURE_3D_BIT) {
else if (texObj && texObj->Target == GL_TEXTURE_3D) {
txformat_multi |= R200_PASS1_TEXCOORD_VOLUME;
}
else if (targetbit == TEXTURE_CUBE_BIT) {
else if (texObj && texObj->Target == GL_TEXTURE_CUBE_MAP) {
txformat_multi |= R200_PASS1_TEXCOORD_CUBIC_ENV;
}
else if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI ||
@ -441,7 +441,7 @@ static void r200UpdateFSRouting( struct gl_context *ctx ) {
else {
txformat_multi |= R200_PASS1_TEXCOORD_PROJ;
}
if (targetbit)
if (texObj)
rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= R200_PPX_TEX_0_ENABLE << reg;
}
rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = txformat_multi;
@ -449,7 +449,7 @@ static void r200UpdateFSRouting( struct gl_context *ctx ) {
/* setup 2nd pass */
for (reg=0; reg < R200_MAX_TEXTURE_UNITS; reg++) {
GLbitfield targetbit = ctx->Texture.Unit[reg]._ReallyEnabled;
struct gl_texture_object *texObj = ctx->Texture.Unit[reg]._Current;
if (shader->SetupInst[1][reg].Opcode) {
GLuint coord = shader->SetupInst[1][reg].src;
GLuint txformat = rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT]
@ -468,10 +468,10 @@ static void r200UpdateFSRouting( struct gl_context *ctx ) {
}
rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
}
else if (targetbit == TEXTURE_3D_BIT) {
else if (texObj && texObj->Target == GL_TEXTURE_3D) {
txformat_x |= R200_TEXCOORD_VOLUME;
}
else if (targetbit == TEXTURE_CUBE_BIT) {
else if (texObj && texObj->Target == GL_TEXTURE_CUBE_MAP) {
txformat_x |= R200_TEXCOORD_CUBIC_ENV;
}
else if (shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STR_ATI ||
@ -492,7 +492,7 @@ static void r200UpdateFSRouting( struct gl_context *ctx ) {
}
rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] = txformat_x;
rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] = txformat;
if (targetbit)
if (texObj)
rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
}
}

2
src/mesa/drivers/dri/r200/r200_tex.c
View File

@ -306,7 +306,7 @@ static void r200TexEnv( struct gl_context *ctx, GLenum target,
/* This is incorrect: Need to maintain this data for each of
* GL_TEXTURE_{123}D, GL_TEXTURE_RECTANGLE_NV, etc, and switch
* between them according to _ReallyEnabled.
* between them according to _Current->Target.
*/
switch ( pname ) {
case GL_TEXTURE_ENV_COLOR: {

9
src/mesa/drivers/dri/r200/r200_texstate.c
View File

@ -935,8 +935,8 @@ static GLboolean r200UpdateAllTexEnv( struct gl_context *ctx )
/* don't enable texture sampling for units if the result is not used */
for (i = 0; i < R200_MAX_TEXTURE_UNITS; i++) {
if (ctx->Texture.Unit[i]._ReallyEnabled && !texregfree[i])
rmesa->state.texture.unit[i].unitneeded = ctx->Texture.Unit[i]._ReallyEnabled;
if (ctx->Texture.Unit[i]._Current && !texregfree[i])
rmesa->state.texture.unit[i].unitneeded = 1 << _mesa_tex_target_to_index(ctx, ctx->Texture.Unit[i]._Current->Target);
else rmesa->state.texture.unit[i].unitneeded = 0;
}
@ -1554,7 +1554,10 @@ void r200UpdateTextureState( struct gl_context *ctx )
if (ctx->ATIFragmentShader._Enabled) {
GLuint i;
for (i = 0; i < R200_MAX_TEXTURE_UNITS; i++) {
rmesa->state.texture.unit[i].unitneeded = ctx->Texture.Unit[i]._ReallyEnabled;
if (ctx->Texture.Unit[i]._Current)
rmesa->state.texture.unit[i].unitneeded = 1 << _mesa_tex_target_to_index(ctx, ctx->Texture.Unit[i]._Current->Target);
else
rmesa->state.texture.unit[i].unitneeded = 0;
}
ok = GL_TRUE;
}

3
src/mesa/drivers/dri/radeon/radeon_maos_arrays.c
View File

@ -269,7 +269,8 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs )
if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) )
vtx |= RADEON_Q_BIT(unit);
else if ((VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) &&
((ctx->Texture.Unit[unit]._ReallyEnabled & (TEXTURE_CUBE_BIT)) == 0)) {
(!ctx->Texture.Unit[unit]._Current ||
ctx->Texture.Unit[unit]._Current->Target != GL_TEXTURE_CUBE_MAP)) {
GLuint swaptexmatcol = (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size - 3);
if (((rmesa->NeedTexMatrix >> unit) & 1) &&
(swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1)))

3
src/mesa/drivers/dri/radeon/radeon_maos_verts.c
View File

@ -355,7 +355,8 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs )
if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) )
vtx |= RADEON_Q_BIT(unit);
else if ((VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) &&
((ctx->Texture.Unit[unit]._ReallyEnabled & (TEXTURE_CUBE_BIT)) == 0)) {
(!ctx->Texture.Unit[unit]._Current ||
ctx->Texture.Unit[unit]._Current->Target != GL_TEXTURE_CUBE_MAP)) {
GLuint swaptexmatcol = (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size - 3);
if (((rmesa->NeedTexMatrix >> unit) & 1) &&
(swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1)))

4
src/mesa/drivers/dri/radeon/radeon_state.c
View File

@ -1850,7 +1850,9 @@ void radeonUploadTexMatrix( r100ContextPtr rmesa,
GLfloat *src = rmesa->tmpmat[unit].m;
rmesa->TexMatColSwap &= ~(1 << unit);
if ((tUnit._ReallyEnabled & (TEXTURE_3D_BIT | TEXTURE_CUBE_BIT)) == 0) {
if (!tUnit._Current ||
(tUnit._Current->Target != GL_TEXTURE_3D &&
tUnit._Current->Target != GL_TEXTURE_CUBE_MAP)) {
if (swapcols) {
rmesa->TexMatColSwap |= 1 << unit;
/* attention some elems are swapped 2 times! */

18
src/mesa/drivers/dri/radeon/radeon_state_init.c
View File

@ -206,9 +206,9 @@ CHECK( tex0_mm, GL_TRUE, 3 )
CHECK( tex1_mm, GL_TRUE, 3 )
/* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
CHECK( tex2_mm, GL_TRUE, 3 )
CHECK( cube0_mm, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
CHECK( cube1_mm, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
CHECK( cube2_mm, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
CHECK( cube0_mm, (ctx->Texture.Unit[0]._Current && ctx->Texture.Unit[0]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE )
CHECK( cube1_mm, (ctx->Texture.Unit[1]._Current && ctx->Texture.Unit[1]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE )
CHECK( cube2_mm, (ctx->Texture.Unit[2]._Current && ctx->Texture.Unit[2]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE )
CHECK( fog_add4, ctx->Fog.Enabled, 4 )
TCL_CHECK( tcl_add4, GL_TRUE, 4 )
TCL_CHECK( tcl_tex0_add4, ctx->Texture.Unit[0]._Current, 4 )
@ -233,9 +233,9 @@ TCL_CHECK( tcl_ucp4_add4, (ctx->Transform.ClipPlanesEnabled & 0x10), 4 )
TCL_CHECK( tcl_ucp5_add4, (ctx->Transform.ClipPlanesEnabled & 0x20), 4 )
TCL_CHECK( tcl_eyespace_or_fog_add4, ctx->_NeedEyeCoords || ctx->Fog.Enabled, 4 )
CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT), 0 )
CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT), 0 )
CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT), 0 )
CHECK( txr0, (ctx->Texture.Unit[0]._Current && ctx->Texture.Unit[0]._Current->Target == GL_TEXTURE_RECTANGLE), 0 )
CHECK( txr1, (ctx->Texture.Unit[1]._Current && ctx->Texture.Unit[1]._Current->Target == GL_TEXTURE_RECTANGLE), 0 )
CHECK( txr2, (ctx->Texture.Unit[2]._Current && ctx->Texture.Unit[2]._Current->Target == GL_TEXTURE_RECTANGLE), 0 )
#define OUT_VEC(hdr, data) do { \
drm_radeon_cmd_header_t h; \
@ -422,7 +422,8 @@ static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
radeon_mipmap_level *lvl;
uint32_t base_reg;
if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT))
if (!ctx->Texture.Unit[i]._Current ||
ctx->Texture.Unit[i]._Current->Target != GL_TEXTURE_CUBE_MAP)
return;
if (!t)
@ -477,7 +478,8 @@ static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
if (hastexture) {
OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0));
if (t->mt && !t->image_override) {
if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
if (ctx->Texture.Unit[i]._Current &&
ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
lvl = &t->mt->levels[t->minLod];
OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);

6
src/mesa/drivers/dri/radeon/radeon_swtcl.c
View File

@ -189,7 +189,8 @@ static void radeonSetVertexFormat( struct gl_context *ctx )
radeon_cp_vc_frmts[i][0] );
break;
case 3:
if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
if (ctx->Texture.Unit[i]._Current &&
ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
radeon_cp_vc_frmts[i][1] );
} else {
@ -198,7 +199,8 @@ static void radeonSetVertexFormat( struct gl_context *ctx )
}
break;
case 4:
if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
if (ctx->Texture.Unit[i]._Current &&
ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
radeon_cp_vc_frmts[i][1] );
} else {