Commit Graph

101927 Commits

Author SHA1 Message Date
Marek Olšák 6d19120da8 radeonsi/gfx9: workaround for INTERP with indirect indexing
and clean up the conditions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
2018-04-27 17:56:04 -04:00
Marek Olšák 2d69b485f5 radeonsi: rewrite DCC format compatibility checking code
It might be better to use a slow compressed clear when clearing to 1.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák c732d069b3 radeonsi: implement DCC fast clear swizzle constraints more accurately
Reduce swizzle constraints to the ALPHA_IS_ON_MSB constraint and the clear
value of 1.

This significantly changes the DCC fast clear code, and fixes fast clear
for RGB formats without alpha.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák 9ef423f720 radeonsi: rename variables and document stuff around DCC fast clear
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák 1cc2e0cc6b radeonsi: fully enable 2x DCC MSAA for array and non-array textures
The clear code is exactly the same as for 1 sample buffers -
just clear the whole thing.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák ca33d961a4 radeonsi: enable fast color clear for level 0 of mipmapped textures on <= VI
GFX9 is more complicated and needs a compute shader that we should just
copy from amdvlk.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák 174e11c3f5 ac/surface: handle DCC subresource fast clear restriction on VI
v2: require the previous level to be clearable for determining whether
    the last unaligned level is clearable

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
George Kyriazis 838f15650e swr/rast: No need to export GetSimdValidIndicesGfx
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 7caeee3432 swr/rast: Small editorial changes
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis f276517ebf swr/rast: Use new processor detection mechanism
Use specific avx512 selection mechanism based on avx512er bit instead of
getHostCPUName().  LLVM 6.0.0 has a bug that reports wrong string for KNL
(fixed in 6.0.1).

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 8ace547e8d swr/rast: Output rasterizer dir to console since it's process specific
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis c328c5d0f4 swr/rast: Add TranslateGfxAddress for shader
Also add GFX_MEM_CLIENT_SHADER

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis edc41f73b8 swr/rast: jit PRINT improvements.
Sign-extend integer types to 32bit when specifying "%d" and add new %u
which zero-extends to 32bit. Improves  printing of sub 32bit integer types
(i1 specifically).

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 5d403178e6 swr/rast: Fix regressions.
Bump jit cache revision number to force recompile.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 577af2bed4 swr/rast: Cleanup old cruft.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis aeab9db50a swr/rast: Package events.proto with core output
However only if the file exists in DEBUG_OUTPUT_DIR. The expectation is
that AR rasterizerLauncher will start placing it there when launching
a workload (which is in a subsequent checkin)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis b97bb0ea6d swr/rast: Fix init in EventHandlerWorkerStats
Make sure we initialize variables.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 9a72d4c03e swr/rast: Fix return type of VCVTPS2PH.
expecting <8xi16> return.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 3f008c5505 swr/rast: WIP Translation handling
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 7986519d50 swr/rast: Use different handing for stream masks
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 6b1c852ebc swr/rast: Silence warnings
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis e6daa62a48 swr/rast: Add support for TexelMask evaluation
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis cec1b52cac swr/rast: Internal core change
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 7b343a215e swr/rast: Fix x86 lowering 64-bit float handling
- 64-bit cvt-to-float needs to be explicitly handled
- gathers need the right parameter types to work with doubles

Fixes draw-vertices piglit tests

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis fa4ab7910e swr/rast: Add some SIMD_T utility functors
VecEqual and VecHash

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 18c9cb85d1 swr/rast: Fix wrong type allocation
ALLOCA pointer elements, not pointers.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 1cdbce8805 swr: touch generated files to update timestamp
previous change in generators necessitates this change

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
George Kyriazis 9ceeb671a3 swr/rast: Fix byte offset for non-indexed draws
for the case when USE_SIMD16_SHADERS == FALSE

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-27 14:36:41 -05:00
Marek Olšák 7083ac7290 util/u_queue: fix a deadlock in util_queue_finish
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 13:28:17 -04:00
Dylan Baker 7772de5283 meson: fix race condition revealed by using 0.44
Previously there was a special target that blocked for the generation of
anv_entrypoints.h, with meson 0.44 we don't need this, we can use a new
language feature instead. The problem is that previously that blocking
target would hide a race condition for the generation of another header,
anv_extensions.h. Now the build sometimes fails when anv_extensions.h is
not generated in time.

v2: - clarify the race condition in the commit message (Emil)

CC: Mark Janes <mark.a.janes@intel.com>
Fixes: 92550d9b16
       ("meson: remove workaround for custom target creating .h and .c files")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-04-27 10:24:51 -07:00
Dylan Baker 0c23bd76d1 bin: force git show to use default pretty setting
I have pretty default to short, which breaks this script.

v2: - Fix both places that don't define a --pretty (Emil)

cc: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Andres Gomez <agomez@igalia.com> (v1)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-04-27 10:19:55 -07:00
Tapani Pälli b3ad4b6971 mesa: add TBO support for GL_EXT_texture_norm16
Earlier plumbing missed interaction with texture buffer objects.

Fixes: 7f467d4f73 "mesa: GL_EXT_texture_norm16 extension plumbing"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-04-27 14:34:43 +03:00
Samuel Pitoiset d38425ce87 ac: fix texture query LOD for 1D textures on GFX9
1D textures are allocated as 2D which means we only need
one coordinate for texture query LOD.

Fixes: 625dcbbc45 ("amd/common: pass address components individually to
ac_build_image_intrinsic")
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 11:15:35 +02:00
Christian Gmeiner 3e69127939 etnaviv: remove not needed includes
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-04-27 09:04:56 +02:00
Christian Gmeiner 2ba587aac7 etnaviv: remove redundant include
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-04-27 09:04:53 +02:00
Timothy Arceri 79b0556f29 glsl: replace some asserts with unreachable when processing the ast
Reviewed-by: Matt Turner <mattst88@gmail.com>
2018-04-27 10:18:47 +10:00
Timothy Arceri 410f901bee mesa: drop the buffer mode param from the DrawBuffer driver function
No drivers used it.

Reviewed-by: Brian Paul <brianp@vmware.com>
2018-04-27 10:09:10 +10:00
Anuj Phogat b695a7bd8e anv/icl: Enable Vulkan on Ice Lake
This patch enables the Vulkan driver on Ice Lake h/w
with added warning about preliminary support.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-04-26 16:31:27 -07:00
Caio Marcelo de Oliveira Filho c9bdc7f7e2 anv: enable VK_EXT_shader_viewport_index_layer
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-26 15:32:05 -07:00
Jason Ekstrand 3db93f9128 anv/allocator: Don't shrink either end of the block pool
Previously, we only tried to ensure that we didn't shrink either end
below what was already handed out.  However, due to the way we handle
relocations with block pools, we can't shrink the back end at all.  It's
probably best to not shrink in either direction.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105374
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106147
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Cc: mesa-stable@lists.freedesktop.org
2018-04-26 13:17:14 -07:00
Eric Anholt 76ee9edcb4 broadcom/vc5: Add support for centroid varyings.
It would be nice to share the flags packet emit logic with flat shade
flags, but I couldn't come up with a good way while still using our pack
macros.  We need to refactor this to shader record setup at compile time,
anyway.

Fixes ext_framebuffer_multisample-interpolation * centroid-*
2018-04-26 11:30:22 -07:00
Eric Anholt e2f3317801 broadcom/vc5: Add an assert about GFXH-1559.
Our TF outputs always start at 6 or 7 currently, so we don't hit the
broken 8 case.  Let's make sure that doesn't change somehow.
2018-04-26 11:30:22 -07:00
Eric Anholt 77b4f30bae broadcom/vc5: Add validation that we don't violate GFXH-1633 requirements.
We don't use ldunifa yet, but we will eventually for UBOs.
2018-04-26 11:30:22 -07:00
Eric Anholt 089c32eefd broadcom/vc5: Add validation that we don't violate GFXH-1625 requirements.
We don't use TMUWT yet, but we will once we do SSBOs.
2018-04-26 11:30:22 -07:00
Eric Anholt 57ceb95c84 broadcom/vc5: Implement GFXH-1742 workaround (emit 2 dummy stores on 4.x).
This should fix help with intermittent GPU hangs in tests switching
formats while rendering small frames.  Unfortunately, it didn't help with
the tests I'm having troubles with.
2018-04-26 11:30:22 -07:00
Eric Anholt dc4cb04ee5 broadcom/vc5: Add QPU validation for register writes after thrend.
The next shader gets to start writing the register file during these
slots, so make sure we don't stomp over them.

The only case of hitting this that I could imagine would be dead writes.
2018-04-26 11:30:22 -07:00
Eric Anholt 8adf813f83 st: Choose a 2101010 format for GL_RGB/GL_RGBA with a 2_10_10_10 type.
GLES's GL_EXT_texture_type_2_10_10_10_REV allows uploading this type to an
unsized internalformat, and it should be non-color-renderable.
fbobject.c's implementation of the check for color-renderable is checks
that the texture has a 2101010 mesa format, so make sure that we have
chosen a 2101010 format so that check can do what it meant to.

Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgb on vc5.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-04-26 11:30:22 -07:00
Charmaine Lee 8aef7fccb7 st/mesa: fix missing setting of _ElementSize in new_draw_rasterpos_stage
With this patch, _ElementSize is initialized along with the rest
of the vertex array attributes in new_draw_rasterpos_stage().
This fixes a crash in st_pipe_vertex_format() when running
topogun-1.06-orc-84k-resize trace file with VMware svga driver.

Reviewed-by: Brian Paul <brianp@vmware.com>
2018-04-26 10:29:02 -07:00
Drew Davenport e923e8151d st/va: Fix typos
s/attibute/attribute/
s/suface/surface/

v2: rebased(Leo)

Reviewed-by: Leo Liu <leo.liu@amd.com>
2018-04-26 11:16:05 -04:00
Drew Davenport 893808006a st/va: Fix potential buffer overread
VASurfaceAttribExternalBuffers.pitches is indexed by
plane. Current implementation only supports single plane layout.

Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2018-04-26 11:16:05 -04:00