swr/rast: Use new processor detection mechanism

Use specific avx512 selection mechanism based on avx512er bit instead of
getHostCPUName().  LLVM 6.0.0 has a bug that reports wrong string for KNL
(fixed in 6.0.1).

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
This commit is contained in:
George Kyriazis 2018-04-24 11:13:54 -05:00
parent 8ace547e8d
commit f276517ebf
2 changed files with 51 additions and 1 deletions

View File

@ -80,7 +80,55 @@ JitManager::JitManager(uint32_t simdWidth, const char *arch, const char* core)
StringRef hostCPUName;
hostCPUName = sys::getHostCPUName();
// force JIT to use the same CPU arch as the rest of swr
if(mArch.AVX512F())
{
#if USE_SIMD16_SHADERS
if(mArch.AVX512ER())
{
hostCPUName = StringRef("knl");
}
else
{
hostCPUName = StringRef("skylake-avx512");
}
mUsingAVX512 = true;
#else
hostCPUName = StringRef("core-avx2");
#endif
if (mVWidth == 0)
{
mVWidth = 8;
}
}
else if(mArch.AVX2())
{
hostCPUName = StringRef("core-avx2");
if (mVWidth == 0)
{
mVWidth = 8;
}
}
else if(mArch.AVX())
{
if (mArch.F16C())
{
hostCPUName = StringRef("core-avx-i");
}
else
{
hostCPUName = StringRef("corei7-avx");
}
if (mVWidth == 0)
{
mVWidth = 8;
}
}
else
{
SWR_INVALID("Jitting requires at least AVX ISA support");
}
auto optLevel = CodeGenOpt::Aggressive;

View File

@ -69,6 +69,7 @@ public:
bool AVX2(void) { return bForceAVX ? 0 : InstructionSet::AVX2(); }
bool AVX512F(void) { return (bForceAVX | bForceAVX2) ? 0 : InstructionSet::AVX512F(); }
bool AVX512ER(void) { return (bForceAVX | bForceAVX2) ? 0 : InstructionSet::AVX512ER(); }
bool BMI2(void) { return bForceAVX ? 0 : InstructionSet::BMI2(); }
private:
@ -142,6 +143,7 @@ struct JitManager
uint32_t mVWidth;
bool mUsingAVX512 = false;
// fetch shader types
llvm::FunctionType* mFetchShaderTy;