Commit Graph

98144 Commits

Author SHA1 Message Date
Wladimir J. van der Laan 5cc36f9f21 etnaviv: GC7000: Make point sprites work on HALTI5
Track varying component offset of the point size output, as well as
provide the offset of the point coord input.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:33:02 +01:00
Wladimir J. van der Laan 3d09bb390a etnaviv: GC7000: State changes for HALTI3..5
Update state objects to add new state, and emit function to emit new
state.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:32:33 +01:00
Wladimir J. van der Laan acd3dff463 etnaviv: GC7000: Update screen specs for HALTI5
- This core must load shaders from memory (AFAIK)
- Yet another new location for UNIFORMS

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:32:21 +01:00
Wladimir J. van der Laan c6033e84bb etnaviv: GC7000: Update context reset for ..HALTI5
Update context reset for HALTI3..HALTI5, sorting states for the HALTI
version that has them.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:28:09 +01:00
Wladimir J. van der Laan baff59ebf0 etnaviv: GC7000: No RS align when using BLT
RS align is not necessary and might even be harmful when using the BLT
engine for blitting.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:28:02 +01:00
Wladimir J. van der Laan dd3a04c2c3 etnaviv: GC7000: BLT engine blitting support
Add an implemenation of key clear_blit functions using the BLT engine
that replaced the RS on GC7000.

Also set level->size correctly for imported resources. This is important
for the BLT resolve-in-place path to work for them.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:27:57 +01:00
Wladimir J. van der Laan 079bbaec0c etnaviv: GC7000: Factor out RS blit functionality
Prepare for BLT-based blitting path by moving RS-based
blitting to the RS implementation file, making this
self-contained.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:27:53 +01:00
Wladimir J. van der Laan 77768b1859 etnaviv: GC7000: Move etna_coalesce to emit header file
Want to be able to emit state from the texture implementation,
and the blitter implementation.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:27:48 +01:00
Wladimir J. van der Laan 571d980695 etnaviv: GC7000: Support BLT as recipient for etna_stall
When the BLT is involved as source or target, add an extra BLT
enable/disable sequence around the sync sequence.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:27:43 +01:00
Wladimir J. van der Laan 150d8766ea etnaviv: Use only DRAW_INSTANCED on GC3000+
The blob does this, as DRAW_INSTANCED can replace fully all the other
draw commands. It is also required to handle integer vertex formats.
The other path is only there for compatibility and might go away (or at
least rot to become buggy due to dis-use) in newer hardware.

As a by-effect this changes the behavior for GC3000-, by no longer using
the index offset for DRAW_INDEXED but instead adding it to INDEX_ADDR.
This should make no difference.

Preparation for GC7000 support.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-11-30 07:26:55 +01:00
Wladimir J. van der Laan 23630ab1b6 etnaviv: Emit SCALE for vertex attributes
This is used by HALTI2+ (GC3000+) when drawing with DRAW_INSTANCED.

It is also necessary when switching between integer and floating point
vertex element formats.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:26:46 +01:00
Kenneth Graunke 74e38739ca i965: Reorganize batch/state BO fields into a 'brw_growing_bo' struct.
We're about to add more of them, and need to pass the whole lot of them
around together when growing them.  Putting them in a struct makes this
much easier.

brw->batch.batch.bo is a bit of a mouthful, but it's nice to have things
labeled 'batch' and 'state' now that we have multiple buffers.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103101
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-11-29 17:30:35 -08:00
Kenneth Graunke ca43616586 i965: Don't grow batch/state buffer on every emit after an overflow.
Once we reach the intended size of the buffer (BATCH_SZ or STATE_SZ), we
try and flush.  If we're not allowed to flush, we resort to growing the
buffer so that there's space for the data we need to emit.

We accidentally got the threshold wrong.  The first non-wrappable call
beyond (e.g.) STATE_SZ would grow the buffer to floor(1.5 * STATE_SZ),
The next call would see we were beyond STATE_SZ and think we needed to
grow a second time - when the buffer was already large enough.

We still want to flush when we hit STATE_SZ, but for growing, we should
use the actual size of the buffer as the threshold.  This way, we only
grow when actually necessary.

v2: Simplify the control flow (suggested by Jordan)

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-11-29 17:30:35 -08:00
Kenneth Graunke 52d32917e1 i965: Preserve EXEC_OBJECT_CAPTURE when growing the BO.
The original state buffer was marked with EXEC_OBJECT_CAPTURE.  When
growing it, we want to preserve that flag so we continue to capture it
in GPU hang reports.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-11-29 17:30:35 -08:00
Kenneth Graunke 2af7085460 i965: Use old_bo->align when growing batch/state buffer instead of 4096.
The intention here is make the new BO use the same alignment as the old
BO.  This isn't strictly necessary, but we would have to update the
'alignment' field in the validation list when swapping it out, and we
don't bother today.

The batch and state buffers use an alignment of 4096, so this should be
equivalent - it's just clearer than cut and pasting a magic constant.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-11-29 17:30:35 -08:00
Dave Airlie 2c4861e453 r600: no need to reinit compute regs
Compute setup gets emitted into the normal gfx state buffer,
so no need to reinit the basics.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-30 09:53:22 +10:00
Dave Airlie ea355e29f7 r600: split cb setup code out from evergreen compute path.
This just makes it easier to bypass for TGSI later.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-30 09:39:25 +10:00
Dave Airlie 77c70e5fe5 r600: add support for compute pkt flags to debug dumping.
This just lets us see packets marked for compute.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-30 09:32:31 +10:00
Dave Airlie 779306c8b6 r600: fix bfe where src/dst are same.
This fixes overlaps where src/dst are the same.

Fixes a bunch of the deqp bitfield tests.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-30 09:32:31 +10:00
Adam Jackson 0d044351b7 gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control
Reviewed-and-tested-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2017-11-29 16:00:24 -05:00
Kenneth Graunke cfc5af588c i965: Program the dynamic state heap size to MAX_STATE_SIZE.
STATE_BASE_ADDRESS specifies a maximum size of the dynamic state
section, beyond which data supposedly reads back as 0.  On Gen8+,
we were programming it to the size of the buffer.  This worked fine
until we started growing the state buffer in commit 2dfc119f22.
When the state buffer grows, the value in STATE_BASE_ADDRESS becomes
too small, and our state beyond STATE_SZ bytes would read back as 0.

To avoid having to update the value, we program it to MAX_STATE_SIZE.
We used to program the upper bound to the maximum on older hardware
anyway, so programming it too large isn't a big deal.

Bogus SURFACE_STATE can easily lead to GPU hangs and misrendering.
DiRT Rally was hitting the statebuffer growth path, and suffered from
bad texture corruption and GPU hangs (usually around the same time).

This patch fixes both issues.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103101
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-11-29 11:48:29 -08:00
Marek Olšák 2c5f2936af r300,r600,radeonsi: replace RADEON_FLUSH_* with PIPE_FLUSH_*
and handle PIPE_FLUSH_HINT_FINISH in r300.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 950221f923 radeonsi: remove r600_common_screen
Most files in gallium/radeon now include si_pipe.h.

chip_class and family are now here:
    sscreen->info.family
    sscreen->info.chip_class

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 4d1fe8f964 radeonsi: remove r600_pipe_common::barrier_flags::compute_to_L2
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák c0d44fe0e9 radeonsi: remove query/apply_opaque_metadata callbacks
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 2208b760f3 radeonsi: move shader debug helpers out of r600_pipe_common.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák e4cce7dbba radeonsi: dismantle si_common_screen_init/destroy
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák e32d3a648e radeonsi: document our vendor string situation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák eae85b99fc radeonsi: set all pipe buffer functions in r600_buffer_common.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 63f88644a5 radeonsi/uvd: don't call ws->query_info
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák b86feec390 radeonsi: move video queries into si_get.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 30d5f2c942 radeonsi: remove more functions from r600_pipe_common.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 757ea3e613 radeonsi: move/remove ac_shader_binary helpers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 03e2adc990 radeonsi: move all get functions to si_get.c; disk_cache_create to si_pipe.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 1823bbbb1a radeonsi: remove R600_CONTEXT_* flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák d96c7e7822 radeonsi: just include si_pipe.h in r600_query.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák c63e225bff radeonsi: remove some definitions and helpers from r600_pipe_common.h
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 175ee084ff radeonsi: don't use fast color clear for small surfaces
This removes 35+ clear eliminate passes from DOTA 2.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 8a58724ac9 radeonsi: unify code setting dirty_level_mask for fast clear
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 980bf9a27e radeonsi: clean up si_do_fast_color_clear parameters
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 092756f23f radeonsi: remove r600_common_context::clear_buffer
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák b191e2d79d radeonsi: move r600_test_dma.c into si_test_dma.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 132471bde1 radeonsi: move si_pipe_clear_buffer into si_cp_dma.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 7aa2366b70 radeonsi: move all clear() code into si_clear.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 3c4d871ca2 radeonsi: enable DCC with MSAA for VI
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 373f4a48ae radeonsi: implement fast color clear for DCC with MSAA for VI
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 36ac7a1b0e radeonsi: add a workaround for blending with DCC and MSAA
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák d1f65e5e99 radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe side
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák e3c0a5b6e8 ac/surface: enable DCC computation for MSAA
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák 6863651bbd radeonsi: fix layered DCC fast clear
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00