Commit Graph

98558 Commits

Author SHA1 Message Date
Samuel Pitoiset 24601810e9 amd/common: more use of i32_1
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:24:42 +01:00
Samuel Pitoiset ec4e566560 amd/common: more use of i32_0
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:24:41 +01:00
Samuel Pitoiset d43e72fd8c radeonsi: make use of ac_build_fdiv()
And move the comment to amd/common.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:24:38 +01:00
Samuel Pitoiset 88522e2bcd radv: export SampleMask from pixel shaders at full rate
Use 16_ABGR instead of 32_ABGR if Z isn't written.

Ported from RadeonSI.

No CTS regressions on Polaris.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:23:28 +01:00
Samuel Pitoiset 45872a0a6d radeonsi: make use of ac_get_spi_shader_z_format()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:23:25 +01:00
Samuel Pitoiset 91f4d746e4 amd/common: add ac_get_spi_shader_z_format()
ac_shader_util.c will contain shader helpers for RadeonSI
and RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:23:23 +01:00
Samuel Pitoiset 90c3bf0789 radv: do not load the local invocation index when it's unused
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:22:26 +01:00
Samuel Pitoiset 2294d35b24 radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components
We should also not load the input SGPRs and VGPRS, but
let's start with this for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:22:06 +01:00
Samuel Pitoiset e001944410 amd/common: scan which components of gl_LocalInvocationID are used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:22:04 +01:00
Samuel Pitoiset 42285ed8c3 amd/common: scan which components of gl_WorkGroupID are used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:22:02 +01:00
Samuel Pitoiset 5a761167f5 radv: set FORCE_SIMD_DIST(1) for compute when profitable
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:20:59 +01:00
Samuel Pitoiset 75b1c4997f radv: calculate best compute resource limits
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:20:57 +01:00
Samuel Pitoiset 9fdc1437ba radv: store the dispatch initiator into the device
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:20:55 +01:00
Samuel Pitoiset 2e58ef46a8 radv: replace grid_components_used by uses_grid_size
Use a boolean instead because the number of needed SGPRs
is always 3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:19:42 +01:00
Samuel Pitoiset 97e57740d8 radv: always emit all compute block components
The number of grid components is always 3 when gl_NumWorkGroups
is declared, because it relies on the number of components of
nir_instrinsic_load_num_work_groups.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-14 22:19:39 +01:00
Emil Velikov 271fc8606a docs: update calendar, add news item and link release notes for 17.2.7
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-12-14 13:52:11 +00:00
Emil Velikov 7ddc3d9f15 docs: add sha256 checksums for 17.2.7
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-12-14 13:49:32 +00:00
Emil Velikov 0811bb3bd3 docs: add release notes for 17.2.7
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-12-14 13:49:30 +00:00
Harish Krupo 96fc5fbf23 egl/android: Provide an option for the backend to expose KHR_image
From android cts 8.0_r4, a new test case checks if all the required egl
extensions are exposed. In the current implementation we expose KHR_image
if KHR_image_base and KHR_image_pixmap are supported but KHR_image spec
does not mandate the existence of both the extensions.
This patch preserves the current check and also provides the backend
with an option to expose the KHR_image extension.

Test: run cts -m CtsOpenGLTestCases -t \
android.opengl.cts.OpenGlEsVersionTest#testRequiredEglExtensions

Signed-off-by: Harish Krupo <harish.krupo.kps@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-12-14 13:43:03 +02:00
Bas Nieuwenhuizen 4eb0dca46b radv: Don't advertise VK_EXT_debug_report.
We never supported it. Missed during copy and pasting.

Fixes: 17201a2eb0 "radv: port to using updated anv entrypoint/extension generator."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-12-14 10:05:22 +01:00
Kenneth Graunke fd3fc5f547 i965: Don't allocate an MCS for 16x MSAA and width > 8192.
The hardware doesn't support this, and isl_surf_get_mcs_surf will fail.

I feel a bit bad replicating this logic, but we want to decide up front.

This fixes the following test when run with --deqp-surface-width=16384:
- GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_sample_count

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2017-12-14 00:37:33 -08:00
Rob Herring 546633dce2 Android: fix missing generation of vtn_gather_types.c
Commit bb1e6ff161 ("spirv: Add a prepass to set types on vtn_values")
added generation of vtn_gather_types.c, but forgot to add it to the
Android build files.

Fixes: bb1e6ff161 ("spirv: Add a prepass to set types on vtn_values")
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-12-13 16:20:15 -06:00
Dylan Baker e5d8ffdda6 mesa: Add glSpecializeShaderARB to common_desktop_functions
CC: Nicolai Hähnle <nicolai.haehnle@amd.com>
CC: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104231
Fixes: 46b21b8f90 ("mesa: add GL_ARB_gl_spirv boilerplate")
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-12-13 13:24:57 -08:00
Tomasz Figa 5364e73624 egl/android: Partially handle HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED
There is no API available to properly query the IMPLEMENTATION_DEFINED
format. As a workaround we rely here on gralloc allocating either
an arbitrary YCbCr 4:2:0 or RGBX_8888, with the latter being recognized
by lock_ycbcr failing.

Reviewed-on: https://chromium-review.googlesource.com/566793

Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-12-13 14:51:48 -06:00
Bruce Cherniak ea2ee9cd19 swr: Correct texture allocation and limit max size to 2GB
This patch fixes piglit tex3d-maxsize by correcting 4 things:

The total_size calculation was using 32-bit math, therefore a >4GB
allocation request overflowed and was not returning false (unsupported).

Changed AlignedMalloc arguments from "unsigned int" to size_t, to handle
>4GB allocations.

Added error checking on texture allocations to fail gracefully.

Finally, temporarily decreased supported max texture size from 4GB to 2GB.
The gallivm texture-sampler needs some additional work to correctly handle
larger than 2GB textures (offsets to LLVMBuildGEP are signed).

I'm working on a follow-on patch to allow up to 4GB textures, as this is
useful in HPC visualization applications.

Fixes piglit tex3d-maxsize.

v2: Updated patch description to clarify ">4GB".

Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
2017-12-13 14:44:04 -06:00
Bruce Cherniak 709f5bdc4a swr: Fix KNOB_MAX_WORKER_THREADS thread creation override.
Environment variable KNOB_MAX_WORKER_THREADS allows the user to override
default thread creation and thread binding.  Previous commit to adjust
linux cpu topology caused setting this KNOB to bind all threads to a single
core.

This patch restores correct functionality of override.

Cc: <mesa-stable@lists.freedesktop.org>

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2017-12-13 14:44:01 -06:00
Dylan Baker 1774c10361 meson: fix glx-test race
This test should rely on dispatch.h being generated, but it doesn't.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-12-13 09:37:12 -08:00
Brian Paul c27a6c45c2 gallium/docs: document behavior of set_sample_mask()
The sample mask is used even if msaa is not explicity enabled when we
have a framebuffer with multisampled surfaces.  That's DX behavior and
what the Radeon drivers do.  Not sure about other drivers at this point.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-12-13 08:38:07 -07:00
Brian Paul 0f2bd31baf glsl: trivial whitespace fixes in link_varyings.cpp 2017-12-13 08:38:07 -07:00
Jordan Justen dc07bb5fd1 program: Don't reset SamplersValidated when restoring from shader cache
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103988
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-12-13 00:31:06 -08:00
Kai Wasserbäch 729fec6eab mesa: remove second include of errors.h in src/mesa/main/glspirv.c
Fixes: 5bc03d2508 ("mesa: implement SPIR-V loading in glShaderBinary")
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-12-12 23:42:53 -08:00
Timothy Arceri 3308f4b81a radeonsi: create get_tcs_tes_buffer_address helper
This will be shared between the NIR and TGSI backends.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-12-13 13:41:53 +11:00
Timothy Arceri a5f9ac2928 ac: fix nir_op_f2f64
Without this we get the error "FPExt only operates on FP" when
converting the following:

   vec1 32 ssa_5 = b2f ssa_4
   vec1 64 ssa_6 = f2f64 ssa_5

Which results in:

   %44 = and i32 %43, 1065353216
   %45 = fpext i32 %44 to double

With this patch we now get:

   %44 = and i32 %43, 1065353216
   %45 = bitcast i32 %44 to float
   %46 = fpext float %45 to double

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-13 13:20:28 +11:00
Timothy Arceri cab5513b47 nir: fix shift for uint64_t
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-12-13 13:20:28 +11:00
Timothy Arceri dd119a4263 st/glsl_to_nir: skip forced array splitting for tcs
nir_lower_io_to_temporaries() does not support tcs so we cannot
assume there are no indirects here. Also the radeonsi backend
(the only backend to support tess) has support for tcs indirects
so there is no need to lower them anyway.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-12-13 13:20:28 +11:00
Francisco Jerez acab52f520 intel/fs/bank_conflicts: Don't touch Gen7 MRF hack registers.
Fixes: af2c320190 "intel/fs: Implement GRF bank conflict mitigation pass."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104199
Reported-by: Darius Spitznagel <d.spitznagel@goodbytez.de>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-12-12 12:05:45 -08:00
Kevin Rogovin b1ce812c51 i965: compute scratch space size correctly for Gen9+
Fixes: 8ecdbb6136 "i965: Pretend there are 4 subslices for compute shader threads on Gen9+."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104005
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
2017-12-12 10:02:43 -08:00
Kevin Rogovin eea9027f87 i965: Program MEDIA_VFE_STATE in a more readable fashion.
This patch is purely for readability improvements when programming
the MEDIA_VFE_STATE.

Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-12-12 10:02:31 -08:00
Brian Paul 7469966ed2 cso: add point rasterization sanity check assertion
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-12-12 09:46:18 -07:00
Brian Paul 38a4fd8ad6 gallium/u_blitter: replace tabs with spaces
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-12 09:46:18 -07:00
Brian Paul 7a46063803 xlib: call _mesa_warning() instead of fprintf()
We use _mesa_warning() everywhere else in this code.  Change requested
by Rick Irons of Mathworks.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-12-12 09:44:59 -07:00
Brian Paul 63b03dc924 gallium/util: don't pass a pipe_resource to util_resource_is_array_texture()
No need to pass a pipe_resource when we can just pass the target.
This makes the function potentially more usable.  Rename it too.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-12 09:44:59 -07:00
Brian Paul dde8309cde gallium/aux: include nr_samples in util_resource_size() computation
This function is only used in two places:
1. VMware driver, but only for HUD reporting
2. st/nine state tracker, used for texture memory accounting

Fixes: a69efa9482 ("util: add new util_resource_size() function in
u_resource.[ch]")

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-12 09:44:59 -07:00
Brian Paul 09b69828a3 svga: trivial whitespace/formatting fixes in svga_pipe_rasterizer.c 2017-12-12 09:44:59 -07:00
Brian Paul 71ac73ce76 st/mesa: trivial whitespace/formatting fixes in st_atom_rasterizer.c 2017-12-12 09:44:59 -07:00
Jason Ekstrand 9718ce44c2 spirv: Handle image and sampler function parameters 2017-12-12 07:34:46 -08:00
Jason Ekstrand 7d3ebd1286 spirv/cfg: Refactor the function parameter loop a bit 2017-12-12 07:34:46 -08:00
Jason Ekstrand e6ba457c99 spirv/cfg: Be a bit more precise about function parameters
Pointers with no storage type are converted to inout variables but SSA
values and pointers with a storage type (which turns into a uint or
uvec2) are just input variables.
2017-12-12 07:34:46 -08:00
Jason Ekstrand aaeda8d7d4 spirv: Make sampled images a real type
Previously, we just gave them exactly the same type as the respective
image (which already had a sampler2D or similar type).  Now they have
their own base type and a pointer to the vtn_type for the image.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2017-12-12 07:34:46 -08:00
Eric Engestrom ec0a4fcec0 i915: add missing 0 defines
Thanks to Emil's -Wundef, t_dd_dmatmp.h now complains that intel_render.c
is missing a couple `#define`s.

Assigning them to 0 keeps the existing behaviour; I'll let someone else
turn them on if this is the behaviour that was intended.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-12-12 13:59:46 +00:00