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i965: compute scratch space size correctly for Gen9+ 

Fixes: 8ecdbb6136 "i965: Pretend there are 4 subslices for compute shader threads on Gen9+."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104005
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
This commit is contained in:
Kevin Rogovin 2017-12-12 14:17:27 +02:00 committed by Kenneth Graunke
parent eea9027f87
commit b1ce812c51
1 changed files with 5 additions and 1 deletions
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6
src/mesa/drivers/dri/i965/brw_program.c
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@ -368,9 +368,13 @@ brw_alloc_stage_scratch(struct brw_context *brw,
*
* According to the other driver team, this applies to compute shaders
* as well. This is not currently documented at all.
*
* brw->screen->subslice_total is the TOTAL number of subslices
* and we wish to view that there are 4 subslices per slice
* instead of the actual number of subslices per slice.
*/
if (devinfo->gen >= 9)
subslices = 4;
subslices = 4 * brw->screen->devinfo.num_slices;
/* WaCSScratchSize:hsw
*